CN117894777A - 堆叠型封装结构及其制造方法 - Google Patents
堆叠型封装结构及其制造方法 Download PDFInfo
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- CN117894777A CN117894777A CN202211632452.2A CN202211632452A CN117894777A CN 117894777 A CN117894777 A CN 117894777A CN 202211632452 A CN202211632452 A CN 202211632452A CN 117894777 A CN117894777 A CN 117894777A
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- Prior art keywords
- layer
- chip
- mold seal
- package structure
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- 238000000034 method Methods 0.000 claims abstract description 47
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- 239000010949 copper Substances 0.000 description 8
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910007637 SnAg Inorganic materials 0.000 description 2
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- 230000002159 abnormal effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
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- 229920001721 polyimide Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
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- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
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Classifications
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Abstract
本申请提供一种堆叠型封装结构及其制造方法。堆叠型封装结构包括上重布线层、第一芯片和上模封层。所述第一芯片设置在所述上重布线层上且与所述上重布线层电连接。所述上模封层设置在所述第一芯片和所述上重布线层上,配置为封装所述第一芯片。所述上模封层包含凹槽,所述凹槽相对于所述上模封层远离所述上重布线层的表面凹陷,以及所述凹槽环绕地形成在所述上模封层的外侧边。本申请确保了在不增加封装尺寸的前提下实现多个元件之间的电连接,以及可有效地解决堆叠封装结构发生翘曲的问题。
Description
技术领域
本申请涉及一种半导体领域,特别是关于一种堆叠型封装结构及其制造方法。
背景技术
目前,先进封装主要有两种发展方向,一是减少封装面积,使其接近芯片大小,另一种则是将多个芯片整合在同一封装内,增加封装内部整合程度。使用多芯片堆叠封装技术或系统级封装技术可实现将多种不同功能的芯片整合在产品中,进而制造出轻质、紧凑、高速、多功能和高性能的产品。因此,对于多芯片的封装结构,如何在不增加封装宽度的前提下实现多个元件之间的电连接,为目前产业界研究的焦点和需解决的技术问题。
有鉴于此,本申请提供一种堆叠型封装结构及其制造方法,以解决上述技术问题。
发明内容
本申请提供一种堆叠型封装结构及其制造方法,其确保了在不增加封装尺寸的前提下实现多个元件之间的电连接。
在一方面,本申请提供一种堆叠型封装结构,包括:上重布线层、第一芯片和上模封层。所述上重布线层包含第一面和相对所述第一面的第二面。所述第一芯片设置在所述上重布线层的所述第一面上且与所述上重布线层电连接。所述上模封层设置在所述第一芯片和所述上重布线层的所述第一面上,配置为封装所述第一芯片。所述上模封层包含凹槽,所述凹槽相对于所述上模封层远离所述上重布线层的表面凹陷,以及所述凹槽环绕地形成在所述上模封层的外侧边。
在一些实施例中,所述上模封层远离所述上重布线层的所述表面至少包含第一阶梯面和第二阶梯面,且所述第一阶梯面为所述凹槽的底面。
在一些实施例中,所述堆叠型封装结构还包含封盖,所述封盖设置在所述上模封层上。
在一些实施例中,所述上模封层还包含开口,所述开口用于曝露出所述第一芯片的非有源面。所述堆叠型封装结构还包含热介面材料,所述热介面材料设置在所述上模封层上且覆盖所述第一芯片的所述非有源面,以及所述热介面材料设置在所述封盖和所述上模封层之间。
在一些实施例中,所述堆叠型封装结构还包含电磁干扰(EMI)屏蔽层,所述EMI屏蔽层覆盖所述上模封层的所述表面。
在一些实施例中,所述堆叠型封装结构还包含第二芯片和第三芯片。所述第二芯片和所述第三芯片设置在所述上重布线层的所述第二面上且与所述上重布线层电连接,所述第二芯片与所述第三芯片横向相邻,以及所述第一芯片通过所述上重布线层与所述第三芯片和所述第二芯片电连接。
在一些实施例中,所述堆叠型封装结构还包含下模封层。所述下模封层设置在所述上重布线层的所述第二面上,配置为封装所述第二芯片和所述第三芯片,以及其中所述下模封层的材料不同于所述上模封层的材料。
在一些实施例中,所述下模封层的所述材料的热膨胀系数大于所述上模封层的所述材料的热膨胀系数。
在一些实施例中,所述堆叠型封装结构还包含:下重布线层、至少一导电柱和多个焊球。所述下重布线层设置在所述下模封层远离所述上重布线层的表面。所述至少一导电柱电连接所述上重布线层和所述下重布线层。所述多个焊球设置在所述下重布线层远离所述下模封层的表面。
在一些实施例中,所述至少一导电柱在所述下重布线层的正投影与所述第一芯片在所述下重布线层的正投影重叠,并且所述第一芯片通过所述上重布线层与所述至少一导电柱电连接。
在另一方面,本申请还提供一种堆叠型封装结构的制造方法,包含:提供载板;在所述载板上设置第一芯片;在所述第一芯片和所述载板上形成模封层,其中所述模封层配置为封装所述第一芯片;在所述第一芯片和所述模封层远离所述载板的表面形成上重布线层,其中所述第一芯片与所述上重布线层电连接;移除所述载板;以及去除部分的模封层以形成上模封层,其中所述上模封层包含凹槽,所述凹槽相对于所述上模封层远离所述上重布线层的表面凹陷,以及所述凹槽环绕地形成在所述上模封层的外侧边。
在一些实施例中,所述上模封层远离所述上重布线层的所述表面至少包含第一阶梯面和第二阶梯面,且所述第一阶梯面为所述凹槽的底面。
在一些实施例中,在形成所述上模封层之后,所述制造方法还包含:在所述上模封层上设置封盖。
在一些实施例中,所述上模封层还包含开口,所述开口用于曝露出所述第一芯片的非有源面。所述制造方法还包含:在所述上模封层上设置一热介面材料,其中所述热介面材料覆盖所述第一芯片的所述非有源面,以及所述热介面材料设置在所述封盖和所述上模封层之间。
在一些实施例中,在形成所述上模封层之后,所述制造方法还包含:在所述上模封层的所述表面形成电磁干扰(EMI)屏蔽层。
在一些实施例中,形成所述上重布线层之后,所述制造方法还包含:在所述上重布线层的远离所述第一芯片的一面设置第二芯片和第三芯片,其中所述第二芯片和所述第三芯片与所述上重布线层电连接,所述第二芯片和所述第三芯片横向相邻,以及所述第一芯片通过所述上重布线层与所述第三芯片和所述第二芯片电连接。
在一些实施例中,所述制造方法还包含:在所述上重布线层的远离所述第一芯片的一面形成下模封层,其中所述下模封层配置为封装所述第二芯片和所述第三芯片,以及所述下模封层的材料不同于所述上模封层的材料。
在一些实施例中,所述下模封层的所述材料的热膨胀系数大于所述上模封层的所述材料的热膨胀系数。
在一些实施例中,在形成所述下模封层之前,所述制造方法还包含:在所述上重布线层的远离所述第一芯片的一面形成至少一导电柱;在形成所述下模封层之后,所述制造方法还包含:在所述下模封层远离所述上重布线层的表面形成下重布线层,其中所述至少一导电柱电连接所述上重布线层和所述下重布线层;以及在所述下重布线层远离所述下模封层的表面形成多个焊球。
在一些实施例中,所述至少一导电柱在所述下重布线层的正投影与所述第一芯片在所述下重布线层的正投影重叠,并且所述第一芯片通过所述上重布线层与所述至少一导电柱电连接。
相较于现有技术,在本申请的堆叠型封装结构及其制造方法中,采用内埋式技术将导电柱、第一芯片、第二芯片和第三芯片等设置在堆叠封装结构内部,最大限度地减少了堆叠封封装结构的外形尺寸,进而保持封装高度要求。再者,通过上重布线层和下重布线层实现了小型化且紧凑设计的多芯片的三维封装。另一方面,本申请通过限定上模封层和下模封层的材料及结构,可有效地解决堆叠封装结构发生翘曲的问题。此外,通过设置散热材料和EMI屏蔽层可进一步提升堆叠封封装结构的整体性能。
附图说明
图1显示根据本申请第一实施例的堆叠型封装结构的示意图;
图2A至图2P显示一系列的剖面图,用于阐明图1的堆叠型封装结构的制造流程;以及
图3显示根据本申请第二实施例的堆叠型封装结构的示意图。
具体实施方式
现参考附图更全面地描述示例实施方式。然而,示例实施方式能够以多种形式实施,且不应被理解为限于在此阐述的范例。相反,提供这些实施方式使得本申请将更加全面和完整,并将示例实施方式的构思全面地传达给本领域的技术人员。附图仅为本申请的示意性图解,并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分,因而将省略对它们的重复描述。
参照图1,其显示根据本申请第一实施例的堆叠型封装结构的示意图。堆叠型封装结构10包含上重布线层(redistribution layer,RDL)110、第一芯片180、上模封层190、导电柱120、第二芯片130、第三芯片140、下模封层150、下重布线层160和焊球170。
如图1所示,上重布线层110包含第一面111和相对第一面111的第二面112。通过对应的工艺使得上重布线层110的内部形成有导线以及位于第一面111和第二面112的多个连接垫,其中导线配置为连接位于第一面111的连接垫和位于第二面112的连接垫。
如图1所示,多个导电柱120设置在上重布线层110的第二面112上且与上重布线层110电连接。具体来说,上重布线层110的第二面112通过其对应的连接垫与多个导电柱120电连接。在本实施例中导电柱120的数量为三个,惟不局限于此。导电柱120可由铜、铝、锡、金、银或上述的组合所构成。
如图1所示,第二芯片130和第三芯片140设置在上重布线层110的第二面112上且与上重布线层110电连接。第二芯片130和第三芯片140横向相邻。具体来说,第二芯片130的有源面包括多个第二凸块132以及第三芯片140的有源面包括多个第三凸块142。第二凸块132和第三凸块142的材料可以是或可包括铜、金、镍、锡银合金、金属合金等。第二芯片130和第三芯片140执行倒装芯片接合以将第二凸块132和第三凸块142接合到上重布线层110,以实现第二芯片130和第三芯片140与上重布线层110的电连接。具体来说,上重布线层110的第二面112设置有暴露在外的多个连接垫。所述多个连接垫亦与第二芯片130的第二凸块132以及第三芯片140的第三凸块142对应设置,并且可通过焊接等技术将上重布线层110的连接垫与第二凸块132和第三凸块142对应连接。在本实施例中,透过第二凸块132和第三凸块142实现第二芯片130和第三芯片140与上重布线层110的电连接,可避免因外部施加应力或工艺内含应力,致使第二芯片130和第三芯片140的低介电系数(low-k)材料破裂(cracking),进而造成芯片的功能异常或失效和可靠度低的问题。应当注意的是,上重布线层110的第二面112还可连接三个以上的芯片,即与第二芯片130和第三芯片140横向相邻的额外芯片,不局限于此。
如图1所示,在第二芯片130和上重布线层110之间包括第一导电端子133,以及在第三芯片140和上重布线层110之间包括第二导电端子143。第一导电端子133配置为连接第二芯片130的第二凸块132和上重布线层110,以及第二导电端子143配置为连第三芯片140的第三凸块142和上重布线层110。第一导电端子133和第二导电端子143可通过使用植球工艺、电镀工艺或其他合适的工艺形成。在本实施例中,第一导电端子133和第二导电端子143是使用例如SnAg的焊接材料并且采用回焊技术而形成,从而降低制造成本并提高制造效率。应当理解的是,根据设计要求,第一导电端子133和第二导电端子143可采用其他可能的材料和形状,不局限于此。可选地,通过焊接工艺和回焊工艺以增强第一导电端子133和第二导电端子143和上重布线层110的对应连接垫之间的接合力。
如图1所示,在上重布线层110和第二芯片130之间设置有第一底胶层131。第一底胶层131形成在第二芯片130的有源面和上重布线层110的第二面112之间的间隙中,且横向地覆盖第二芯片130的有源面和上重布线层110的第二面112之间的连接件,例如第二芯片130的第二凸块132、上重布线层110的连接垫和第一导电端子133。通过设置第一底胶层131可增强第二芯片130和上重布线层110之间的接合力和增强接合的可靠性。
如图1所示,相似地,在上重布线层110和第三芯片140之间设置有第二底胶层141。第二底胶层141形成在第三芯片140的有源面和上重布线层110的第二面112之间的间隙中,且横向地覆盖第三芯片140的有源面和上重布线层110的第二面112之间的连接件,例如第三芯片140的第三凸块142、上重布线层110的连接垫和第二导电端子143。通过设置第二底胶层141可增强第三芯片140和上重布线层110之间的接合力和增强接合的可靠性。
如图1所示,下模封层150设置在上重布线层110的第二面112、第二芯片130和第三芯片140上。下模封层150将上重布线层110的第二面112和设置在其上的元件(导电柱120、第二芯片130和第三芯片140)包封,并仅仅曝露出导电柱120的对应的表面,以用于与后续形成的元件电连接。
如图1所示,下重布线层160设置在下模封层150远离上重布线层110的表面。下重布线层160包含相对的两表面。通过对应的工艺使得下重布线层160的内部形成有导线以及位于所述两表面的多个连接垫,其中导线配置为连接位于所述两表面的连接垫。导电柱120连接下重布线层160的连接垫和上重布线层110的连接垫,进而电连接上重布线层110和下重布线层160。在本实施例中,第二芯片130和第三芯片140的背面(非有源面)不与下重布线层160直接接触。也就是说,第二芯片130和第三芯片140的背面与下重布线层160之间具有模具间隙(mold clearance)。
如图1所示,多个焊球170设置在下重布线层160远离下模封层150的表面。焊球170可通过使用植球工艺、电镀工艺或其他合适的工艺形成。在一些实施例中,焊球170是通过植球工艺所形成的焊球,从而降低制造成本并提高制造效率。应当理解的是,根据设计要求,焊球170可采用其他可能的材料和形状,不局限于此。
如图1所示,第一芯片180设置在上重布线层110的第一面111上且与上重布线层110电连接。第一芯片180包含有源面和相对有源面的非有源面181。在本实施例中,第一芯片180的有源面与第二芯片130和第三芯片140的有源面采用面对面的设置。第一芯片180的有源面上设置有多个第一凸块182。应当理解的是,在制造时,第一芯片180是采用面朝上(face-up)配置,因此在一些实施例中,第一芯片180可不包含第一凸块182。第一凸块182的材料可以是或可包括铜、金、镍、金属合金等。在制造时,第一芯片180先被设置在载板上,接着依序形成上模封层190和上重布线层110。第一芯片180的第一凸块182接合到上重布线层110,以实现第一芯片180与上重布线层110的电连接。具体来说,先在第一芯片180上涂布一层介电材料(如Polyimide),接着再形成上重布线层110。后续形成的上重布线层110具有与第一芯片180的第一凸块182对应形成的多个连接垫,并且可通过适当地连接技术将连接垫与第一凸块182对应连接。在本实施例中,从图1的顶部观视时,第一芯片180与第二芯片130部分重叠,并且第一芯片180也与第三芯片140部分重叠。藉此设计,有利于实现小型化且紧凑设计的多芯片的三维封装。
在本实施例中,第一芯片180可为系统单芯片(system on a chip,SoC)。第二芯片130和第三芯片140可为存储器芯片等,例如非易失性和/或易失性存储器。非易失性存储器可包括只读存储器(read only memory,ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦可编程ROM(EEPROM)或闪存。易失性存储器可包括随机存取存储器(RAM)等。
如图1所示,第一芯片180通过所述上重布线层110与导电柱120、第二芯片130和第三芯片140电连接。具体来说,第一芯片180的部分的第一凸块182通过上重布线层110和导电柱120连接到信号/电源/接地的I/O端子的焊球170。第一芯片180的其余的第一凸块182通过上重布线层110的内部细间距导线连接到第二芯片130和第三芯片140。第二芯片130和第三芯片140通过朝向上重布线层110的第二凸块132和第三凸块142连接第一芯片180的第一凸块182与上重布线层110中较短的信号路径。
再者,其中之一导电柱120在下重布线层160的正投影与第一芯片180在下重布线层160的正投影重叠。通过尺寸较大的导电柱120纵向地且直接地连接第一芯片180、上重布线层110和下重布线层160,可以有效地降低阻抗、缩短电源路径和降低功率衰退(powerdrop),进而获得良好的电源完整性能。
如图1所示,上模封层190设置在第一芯片180和上重布线层110的第一面111上,配置为封装第一芯片180。在本实施例中,导电柱120、第一芯片180、第二芯片130和第三芯片140采用内埋(embedded)式技术堆叠地设置,以最大限度地减少了堆叠型封装结构10的外形尺寸,并且确保多芯片之间的坚固互连,进而保持封装高度要求。也就是说,多芯片在不同的扇出重布线层上进行三维堆叠。因此,在本申请的堆叠型封装结构10中,在符合封装宽度的条件下,通过上重布线层110和下重布线层160实现了小型化且紧凑设计的多芯片的三维封装,进而为本申请的堆叠型封装结构10在高端产品的应用提供更多的设计灵活性和自由度。另一方面,内埋式技术的优点包括可提升电性、降低杂信、缩小产品尺寸(包括长度和宽度),以及降低成本等。再者,本申请通过上重布线层110和下重布线层160的精细布线作为多芯片之间的信号传递路径,可有效地提高信号传递的速度和缩小布线面积,进而确保了多芯片之间的电连接,和实现了高电路密度和细间距的设计。因此,多芯片之间的信号传递速度和信号完整性可以得到更好的表现。
在本实施例中,下模封层150的材料可不同于上模封层190的材料。具体来说,下模封层150的所述材料的热膨胀系数大于上模封层190的所述材料的热膨胀系数。在堆叠型封装结构10中,由于下模封层150内包封的元件数量多于上模封层190内包封的元件数量,因此下模封层150的材料的使用量少于上模封层190的材料的使用量。由于模封层150/190和模封层150/190内部的元件(如导电柱120、第一芯片180、第二芯片130和第三芯片140)的热膨胀系数不同,通过将下模封层150的所述材料的热膨胀系数设置于大于上模封层190的所述材料的热膨胀系数可避免因为上下两模封层及内部元件的整体热膨胀程度的差异而导致堆叠型封装结构10翘曲变形。
如图1所示,上模封层190包含凹槽191。凹槽191相对于上模封层190远离上重布线层110的表面凹陷,以及凹槽191环绕地形成在上模封层190的外侧边。具体来说,上模封层190远离上重布线层110的所述表面至少包含第一阶梯面1921和第二阶梯面1922,且第一阶梯面1921为凹槽191的底面。在本实施例的堆叠型封装结构10中,下模封层150的材料的使用量少于上模封层190的材料的使用量,并且封装结构的翘曲变形通常是发生在其外周围。因此,通过将上模封层190的部分去除以在其外表面的周缘形成凹槽191,可有效地平衡上模封层190内部的应力,进而避免堆叠型封装结构10翘曲变形。
如图1所示,堆叠型封装结构10还包含热介面材料101和封盖102。热介面材料101和封盖102依序设置在上模封层190上,并且热介面材料101设置在封盖102和上模封层190之间。封盖102较佳地以金属材料制成。封盖102的外周缘通过热介面材料101与第一阶梯面1921接触。在本实施例中,通过封盖102覆盖住第一芯片180和上模封层190可避免第一芯片180和上模封层190受损,以及提高堆叠型封装结构10的散热性能。再者,封盖102纵向地覆盖住第一芯片180和上模封层190,尤其是覆盖住上模封层190的周缘。由于封盖102由强度较高的金属材质制成,因此封盖102的设置可有效地增强堆叠型封装结构10的稳定性,抑制堆叠型封装结构10发生翘曲变形。
如图1所示,在本实施例中,对应于第一阶梯面1921的位置,上模封层190与上重布线层110之间不包含额外的元件。也就是说,对应于第一阶梯面1921的位置,没有额外的元件设置在上重布线层110的第一面111上。因此,还确保了封盖102在形成时或者在抑制变形时产生的内应力不会损坏额外的元件。
如图1所示,上模封层190还包含开口193,所述开口193用于曝露出第一芯片180的非有源面181。热介面材料101覆盖第一芯片180的非有源面181,并且热介面材料101设置在封盖102与上模封层190和第一芯片180接触的表面。因此,通过热介面材料101的设计,确保堆叠型封装结构10具有良好的散热性能。
在本实施例中,采用内埋式技术将导电柱120、第一芯片180、第二芯片130和第三芯片140等设置在堆叠封装结构10内部,最大限度地减少了堆叠封封装结构10的外形尺寸,进而保持封装高度要求。再者,通过上重布线层110和下重布线层160实现了小型化且紧凑设计的多芯片的三维封装。另一方面,本申请通过限定上模封层190和下模封层150的材料及结构,可有效地解决堆叠封装结构发生翘曲的问题。
参照图2A至图2P,其显示一系列的剖面图,用于阐明图1的堆叠型封装结构的制造流程。
如图2A所示,提供一载板301,并且在载板301的一表面形成分离层302。分离层302配置为将后续形成的膜层从载板301的表面分离。此外,分离层302还可以为载板301和后续形成的膜层之间提供足够的结合力(通过粘合和/或其他结合力),使得后续的膜层可顺利形成。
如图2B所示,在载板301上设置第一芯片180。具体来说,第一芯片180设置在分离层302远离载板301的表面上。第一芯片180包含有源面和相对有源面的非有源面181。第一芯片180的有源面上设置有多个第一凸块182。第一凸块182的材料可以是或可包括铜、金、镍、金属合金等。应当理解的是,在制造时,第一芯片180是采用面朝上(face-up)配置,因此在一些实施例中,第一芯片180可不包含第一凸块182。
如图2C所示,在第一芯片180和载板301上形成模封层190’。模封层190’配置为封装第一芯片180。
如图2D所示,对模封层190’施加一薄化工艺,以减少模封层190’的厚度和曝露出第一芯片180的第一凸块182的对应表面,以用于与后续形成的元件电连接。可选地,薄化工艺可通过使用研磨机来实现。
如图2E所示,在第一芯片180和模封层190’远离载板301的表面形成上重布线层110。第一芯片180与上重布线层110电连接。上重布线层110包含第一面111和相对第一面111的第二面112。通过对应的工艺使得上重布线层110的内部形成有导线以及位于第一面111和第二面112的多个连接垫,其中导线配置为连接位于第一面111的连接垫和位于第二面112的连接垫。
如图2E所示,第一芯片180的第一凸块182接合到上重布线层110,以实现第一芯片180与上重布线层110的电连接。具体来说,先在第一芯片180上涂布一层介电材料(如Polyimide),接着再形成上重布线层110。后续形成的上重布线层110具有与第一芯片180的第一凸块182对应形成的多个连接垫,并且可通过适当地连接技术将连接垫与第一芯片180的第一凸块182对应连接。
如图2F所示,在上重布线层110的第二面112上形成多个导电柱120,并且多个导电柱120与上重布线层110电连接。具体来说,上重布线层110的第二面112通过其对应的连接垫与多个导电柱120电连接。在本实施例中导电柱120的数量为六个,惟不局限于此。导电柱120可由铜、铝、锡、金、银或上述的组合所构成。
如图2G所示,形成上重布线层110之后,所述制造方法还包含:在上重布线层110的第二面112上形成第二芯片130和第三芯片140,并且第二芯片130和第三芯片140与上重布线层110电连接。应当理解的是,在本实施例中是采用先形成导电柱120再形成第二芯片130和第三芯片140,然而,在其他实施例中,亦可以采用先形成第二芯片130和第三芯片140再形成导电柱120,惟不局限于此。在本实施例中,从图2G的顶部观视时,第一芯片180与第二芯片130部分重叠,并且第一芯片180也与第三芯片140部分重叠。藉此设计,有利于实现小型化且紧凑设计的多芯片的三维封装。
如图2G所示,第二芯片130和第三芯片140横向相邻。具体来说,第二芯片130的有源面包括多个第二凸块132以及第三芯片140的有源面包括多个第三凸块142。第二凸块132和第三凸块142的材料可以是或可包括铜、金、镍、锡银合金、金属合金等。第二芯片130和第三芯片140执行倒装芯片接合以将第二凸块132和第三凸块142接合到上重布线层110,以实现第二芯片130和第三芯片140与上重布线层110的电连接。具体来说,上重布线层110的第二面112设置有暴露在外的多个连接垫。所述多个连接垫亦与第二芯片130的第二凸块132以及第三芯片140的第三凸块142对应设置,并且可通过焊接等技术将上重布线层110的连接垫与第二凸块132和第三凸块142对应连接。在本实施例中,透过第二凸块132和第三凸块142实现第二芯片130和第三芯片140与上重布线层110的电连接,可避免因外部施加应力或工艺内含应力,致使第二芯片130和第三芯片140的低介电系数(low-k)材料破裂(cracking),进而造成芯片的功能异常或失效和可靠度低的问题。应当注意的是,上重布线层110的第二面112还可连接三个以上的芯片,即与第二芯片130和第三芯片140横向相邻的额外芯片,不局限于此。在本实施例中,第一芯片180的有源面与第二芯片130和第三芯片140的有源面采用面对面的设置。
如图2G所示,在第二芯片130和上重布线层110之间包括第一导电端子133,以及在第三芯片140和上重布线层110之间包括第二导电端子143。第一导电端子133配置为连接第二芯片130的第二凸块132和上重布线层110,以及第二导电端子143配置为连接第三芯片140的第三凸块142和上重布线层110。第一导电端子133和第二导电端子143可通过使用植球工艺、电镀工艺或其他合适的工艺形成。在本实施例中,第一导电端子133和第二导电端子143是使用例如SnAg的焊接材料并且采用回焊技术而形成,从而降低制造成本并提高制造效率。应当理解的是,根据设计要求,第一导电端子133和第二导电端子143可采用其他可能的材料和形状,不局限于此。可选地,通过焊接工艺和回焊工艺以增强第一导电端子133和第二导电端子143和下重布线层110的对应连接垫之间的接合力。
如图2G所示,在上重布线层110和第二芯片130之间设置有第一底胶层131。第一底胶层131形成在第二芯片130的有源面和上重布线层110的第二面112之间的间隙中,且横向地覆盖第二芯片130的有源面和上重布线层110的第二面112之间的连接件,例如第二芯片130的第二凸块132、上重布线层110的连接垫和第一导电端子133。通过设置第一底胶层131可增强第二芯片130和上重布线层110之间的接合力和增强接合的可靠性。
如图2G所示,相似地,在上重布线层110和第三芯片140之间设置有第二底胶层141。第二底胶层141形成在第三芯片140的有源面和上重布线层110的第二面112之间的间隙中,且横向地覆盖第三芯片140的有源面和上重布线层110的第二面112之间的连接件,例如第三芯片140的第三凸块142、上重布线层110的连接垫和第二导电端子143。通过设置第二底胶层141可增强第三芯片140和上重布线层110之间的接合力和增强接合的可靠性。
如图2H所示,在上重布线层110的第二面112、第二芯片130和第三芯片140上形成下模封层150。下模封层150将上重布线层110的第二面112和设置在其上的元件(导电柱120、第二芯片130和第三芯片140)包封。
如图2I所示,对下模封层150施加一薄化工艺,以减少下模封层150的厚度和曝露出导电柱120的对应表面,以用于与后续形成的元件电连接。可选地,薄化工艺可通过使用研磨机来实现。
如图2J所示,在下模封层150远离上重布线层110的表面形成下重布线层160。下重布线层160包含相对的两表面。通过对应的工艺使得上重布线层110的内部形成有导线以及位于所述两表面上的多个连接垫,其中导线配置为连接分别位于相对的两表面的连接垫。导电柱120连接下重布线层160的连接垫和上重布线层110的连接垫,进而电连接上重布线层110和下重布线层160。在本实施例中,第二芯片130和第三芯片140的背面(非有源面)不与下重布线层160直接接触。也就是说,第二芯片130和第三芯片140的背面与下重布线层160之间具有模具间隙(mold clearance)。
在本实施例中,第一芯片180可为系统单芯片(system on a chip,SoC)。第二芯片130和第三芯片140可为存储器芯片等,例如非易失性和/或易失性存储器。非易失性存储器可包括只读存储器(read only memory,ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦可编程ROM(EEPROM)或快闪存储器。易失性存储器可包括随机存取存储器(RAM)等。
如图2K所示,移除载板301。具体来说,通过分离层302将载板301与模封层190’分离。载板301可对其上方形成的元件提供良好的支撑性,以避免在图2A至图2J对应的步骤中结构发生形变的风险。如图2K所示,模封层190’还包含开口193,所述开口193用于曝露出第一芯片180的非有源面181。
如图2L所示,在下重布线层160远离下模封层150的表面形成多个焊球170。焊球170可通过使用植球工艺、电镀工艺或其他合适的工艺形成。在一些实施例中,焊球170是通过植球工艺所形成的焊球,从而降低制造成本并提高制造效率。应当理解的是,根据设计要求,焊球170可采用其他可能的材料和形状,不局限于此。
如图2L所示,第一芯片180通过所述上重布线层110与导电柱120、第二芯片130和第三芯片140电连接。具体来说,第一芯片180的部分的第一凸块182通过上重布线层110和导电柱120连接到信号/电源/接地的I/O端子的焊球170。第一芯片180的其余的第一凸块182通过上重布线层110的内部细间距导线连接到第二芯片130和第三芯片140。第二芯片130和第三芯片140通过朝向上重布线层110的第二凸块132和第三凸块142连接第一芯片180的第一凸块182与上重布线层110中较短的信号路径。
再者,如图2L所示,其中之一导电柱120在下重布线层160的正投影与第一芯片180在下重布线层160的正投影重叠。通过尺寸较大的导电柱120纵向地且直接地连接第一芯片180、上重布线层110和下重布线层160,可以有效地降低阻抗、缩短电源路径和降低功率衰退(power drop),进而获得良好的电源完整性能。
如图2L所示,导电柱120、第一芯片180、第二芯片130和第三芯片140采用内埋(embedded)式技术堆叠地设置,以最大限度地减少了堆叠型封装结构10的外形尺寸,并且确保多芯片之间的坚固互连,进而保持封装高度要求。也就是说,多芯片在不同的扇出重布线层上进行三维堆叠。因此,在本申请的堆叠型封装结构10中,在符合封装宽度的条件下,通过上重布线层110和下重布线层160实现了小型化且紧凑设计的多芯片的三维封装,进而为本申请的堆叠型封装结构10在高端产品的应用提供更多的设计灵活性和自由度。另一方面,内埋式技术的优点包括可提升电性、降低杂信、缩小产品尺寸(包括长度和宽度),以及降低成本等。再者,本申请通过上重布线层110和下重布线层160的精细布线作为多芯片之间的信号传递路径,可有效地提高信号传递的速度和缩小布线面积,进而确保了多芯片之间的电连接,和实现了高电路密度和细间距的设计。因此,多芯片之间的信号传递速度和信号完整性可以得到更好的表现。
如图2M所示,将图2L对应的半成品沿着分离线L断开,以形成多个独立的堆叠型封装结构10。可选地,半成品的断开可通过切割机来实现。
如图2N所示,去除部分的模封层190’以形成上模封层190。上模封层190包含凹槽191,凹槽191相对于上模封层190远离上重布线层110的表面凹陷,以及凹槽191环绕地形成在上模封层190的外侧边。具体来说,上模封层190远离上重布线层110的所述表面至少包含第一阶梯面1921和第二阶梯面1922,且第一阶梯面1921为凹槽191的底面。在本实施例的堆叠型封装结构10中,下模封层150的材料的使用量少于上模封层190的材料的使用量,并且封装结构的翘曲变形通常是发生在其外周围。因此,通过将上模封层190的部分去除以在其外表面的周缘形成凹槽191,可有效地平衡上模封层190内部的应力,进而避免堆叠型封装结构10翘曲变形。
在本实施例中,下模封层150的材料不同于上模封层190的材料。具体来说,下模封层150的所述材料的热膨胀系数大于上模封层190的所述材料的热膨胀系数。在堆叠型封装结构10中,由于下模封层150内包封的元件数量多于上模封层190内包封的元件数量,因此下模封层150的材料的使用量少于上模封层190的材料的使用量。由于模封层150/190和模封层150/190内部的元件(如导电柱120、第一芯片180、第二芯片130和第三芯片140)的热膨胀系数不同,通过将下模封层150的所述材料的热膨胀系数设置于大于上模封层190的所述材料的热膨胀系数可避免因为上下两模封层及内部元件的整体热膨胀程度的差异而导致堆叠型封装结构10翘曲变形。
如图2O所示,在形成上模封层190之后,所述制造方法还包含:在上模封层190上依序设置热介面材料101和封盖102,其中热介面材料101位于上模封层190与封盖102之间。封盖102较佳地以金属材料制成。封盖102的外周缘通过热介面材料101与第一阶梯面1921接触。在本实施例中,通过封盖102覆盖住第一芯片180和上模封层190可避免第一芯片180和上模封层190受损,以及提高堆叠型封装结构10的散热性能。再者,封盖102纵向地覆盖住第一芯片180和上模封层190,尤其是覆盖住上模封层190的周缘。由于封盖102由强度较高的金属材质制成,因此封盖102的设置可有效地增强堆叠型封装结构10的稳定性,以及抑制堆叠型封装结构10发生翘曲变形。如图2O所示,在本实施例中,对应于第一阶梯面1921的位置,上模封层190与上重布线层110之间不包含额外的元件。也就是说,对应于第一阶梯面1921的位置,没有额外的元件设置在上重布线层110的第一面111上。因此,确保了封盖102在形成时或者在抑制变形时产生的内应力不会损坏额外的元件。
如图2P所示,将封盖102设置在上模封层190上之后,形成了本申请的堆叠型封装结构10。热介面材料101覆盖第一芯片180的非有源面181,并且热介面材料101设置在封盖102与上模封层190和第一芯片180接触的表面。因此,通过热介面材料101的设计,确保堆叠型封装结构10具有良好的散热性能。
在本实施例中,采用内埋式技术将导电柱120、第一芯片180、第二芯片130和第三芯片140等设置在堆叠封装结构10内部,最大限度地减少了堆叠封封装结构10的外形尺寸,进而保持封装高度要求。再者,通过上重布线层110和下重布线层160实现了小型化且紧凑设计的多芯片的三维封装。另一方面,本申请通过限定上模封层190和下模封层150的材料及结构,可有效地解决堆叠封装结构发生翘曲的问题。
图3显示根据本申请第二实施例的堆叠型封装结构的示意图。第二实施例的堆叠型封装结构20包括上重布线层110、第一芯片180、上模封层190、导电柱120、第二芯片130、第三芯片140、下模封层150、下重布线层160和焊球170,其中所述多个元件的特征与的造方法与第一实施例的堆叠型封装结构10的对应元件相同,在此不加以赘述。
如图3所示,第二实施例的堆叠型封装结构20与第一实施例的堆叠型封装结构10的结构大致相同,两者差别在于,第二实施例的堆叠型封装结构20整面设置的电磁干扰(EMI)屏蔽层201。EMI屏蔽层201覆盖上模封层190的远离上重布线层110的表面。具体来说,EMI屏蔽层201为整面形成,并且覆盖上模封层190的第一阶梯面1921和第二阶梯面1922。可选地,EMI屏蔽层201为多层金属层结构,使用例如Ti/Cu或Ti/Cu/Ti的材料并且采用物理气相沉积(PVD)技术而形成。在本实施例中,通过设置EMI屏蔽层201可提高堆叠型封装结构20的抗电磁干扰的能力。
在本申请的堆叠型封装结构及其制造方法中,采用内埋式技术将导电柱、第一芯片、第二芯片和第三芯片等设置在堆叠封装结构内部,最大限度地减少了堆叠封封装结构的外形尺寸,进而保持封装高度要求。再者,通过上重布线层和下重布线层实现了小型化且紧凑设计的多芯片的三维封装。另一方面,本申请通过限定上模封层和下模封层的材料及结构,可有效地解决堆叠封装结构发生翘曲的问题。此外,通过设置散热材料和EMI屏蔽层可进一步提升堆叠封封装结构的整体性能。
Claims (20)
1.一种堆叠型封装结构,其特征在于,包括:
上重布线层,包含第一面和相对所述第一面的第二面;
第一芯片,设置在所述上重布线层的所述第一面上且与所述上重布线层电连接;以及
上模封层,设置在所述第一芯片和所述上重布线层的所述第一面上,配置为封装所述第一芯片,其中所述上模封层包含凹槽,所述凹槽相对于所述上模封层远离所述上重布线层的表面凹陷,以及所述凹槽环绕地形成在所述上模封层的外侧边。
2.如权利要求1所述的堆叠型封装结构,其特征在于,所述上模封层远离所述上重布线层的所述表面至少包含第一阶梯面和第二阶梯面,且所述第一阶梯面为所述凹槽的底面。
3.如权利要求2所述的堆叠型封装结构,其中其特征在于,所述堆叠型封装结构还包含封盖,所述封盖设置在所述上模封层上。
4.如权利要求3所述的堆叠型封装结构,其特征在于,所述上模封层还包含开口,所述开口用于曝露出所述第一芯片的非有源面;以及
其中所述堆叠型封装结构还包含热介面材料,所述热介面材料设置在所述上模封层上且覆盖所述第一芯片的所述非有源面,以及所述热介面材料设置在所述封盖和所述上模封层之间。
5.如权利要求1所述的堆叠型封装结构,其特征在于,所述堆叠型封装结构还包含电磁干扰(EMI)屏蔽层,所述EMI屏蔽层覆盖所述上模封层的所述表面。
6.如权利要求1所述的堆叠型封装结构,其特征在于,所述堆叠型封装结构还包含第二芯片和第三芯片,其中所述第二芯片和所述第三芯片设置在所述上重布线层的所述第二面上且与所述上重布线层电连接,所述第二芯片与所述第三芯片横向相邻,以及所述第一芯片通过所述上重布线层与所述第三芯片和所述第二芯片电连接。
7.如权利要求6所述的堆叠型封装结构,其特征在于,所述堆叠型封装结构还包含:下模封层,设置在所述上重布线层的所述第二面上,配置为封装所述第二芯片和所述第三芯片,以及其中所述下模封层的材料不同于所述上模封层的材料。
8.如权利要求7所述的堆叠型封装结构,其特征在于,所述下模封层的所述材料的热膨胀系数大于所述上模封层的所述材料的热膨胀系数。
9.如权利要求6所述的堆叠型封装结构,其特征在于,所述堆叠型封装结构还包含:
下重布线层,设置在所述下模封层远离所述上重布线层的表面;
至少一导电柱,电连接所述上重布线层和所述下重布线层;以及
多个焊球,设置在所述下重布线层远离所述下模封层的表面。
10.如权利要求9所述的堆叠型封装结构,其特征在于,所述至少一导电柱在所述下重布线层的正投影与所述第一芯片在所述下重布线层的正投影重叠,并且所述第一芯片通过所述上重布线层与所述至少一导电柱电连接。
11.一种堆叠型封装结构的制造方法,其特征在于,包含:
提供载板;
在所述载板上设置第一芯片;
在所述第一芯片和所述载板上形成模封层,其中所述模封层配置为封装所述第一芯片;
在所述第一芯片和所述模封层远离所述载板的表面形成上重布线层,其中所述第一芯片与所述上重布线层电连接;
移除所述载板;以及
去除部分的模封层以形成上模封层,其中所述上模封层包含凹槽,所述凹槽相对于所述上模封层远离所述上重布线层的表面凹陷,以及所述凹槽环绕地形成在所述上模封层的外侧边。
12.如权利要求11所述的堆叠型封装结构的制造方法,其特征在于,所述上模封层远离所述上重布线层的所述表面至少包含第一阶梯面和第二阶梯面,且所述第一阶梯面为所述凹槽的底面。
13.如权利要求12所述的堆叠型封装结构的制造方法,其特征在于,在形成所述上模封层之后,所述制造方法还包含:在所述上模封层上设置封盖。
14.如权利要求13所述的堆叠型封装结构的制造方法,其特征在于,所述上模封层还包含开口,所述开口用于曝露出所述第一芯片的非有源面;以及
所述制造方法还包含:在所述上模封层上设置热介面材料,其中所述热介面材料覆盖所述第一芯片的所述非有源面,以及所述热介面材料设置在所述封盖和所述上模封层之间。
15.如权利要求11所述的堆叠型封装结构的制造方法,其特征在于,在形成所述上模封层之后,所述制造方法还包含:在所述上模封层的所述表面形成电磁干扰(EMI)屏蔽层。
16.如权利要求11所述的堆叠型封装结构的制造方法,其特征在于,形成所述上重布线层之后,所述制造方法还包含:在所述上重布线层的远离所述第一芯片的一面设置第二芯片和第三芯片,其中所述第二芯片和所述第三芯片与所述上重布线层电连接,所述第二芯片和所述第三芯片横向相邻,以及所述第一芯片通过所述上重布线层与所述第三芯片和所述第二芯片电连接。
17.如权利要求16所述的堆叠型封装结构的制造方法,其特征在于,所述制造方法还包含:在所述上重布线层的远离所述第一芯片的一面形成下模封层,其中所述下模封层配置为封装所述第二芯片和所述第三芯片,以及所述下模封层的材料不同于所述上模封层的材料。
18.如权利要求17所述的堆叠型封装结构的制造方法,其特征在于,所述下模封层的所述材料的热膨胀系数大于所述上模封层的所述材料的热膨胀系数。
19.如权利要求17所述的堆叠型封装结构的制造方法,其特征在于,在形成所述下模封层之前,所述制造方法还包含:在所述上重布线层的远离所述第一芯片的一面形成至少一导电柱;
在形成所述下模封层之后,所述制造方法还包含:
在所述下模封层远离所述上重布线层的表面形成下重布线层,其中所述至少一导电柱电连接所述上重布线层和所述下重布线层;以及
在所述下重布线层远离所述下模封层的表面形成多个焊球。
20.如权利要求19所述的堆叠型封装结构的制造方法,其特征在于,所述至少一导电柱在所述下重布线层的正投影与所述第一芯片在所述下重布线层的正投影重叠,并且所述第一芯片通过所述上重布线层与所述至少一导电柱电连接。
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