TWI824764B - 堆疊型封裝結構及其製造方法 - Google Patents
堆疊型封裝結構及其製造方法 Download PDFInfo
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- TWI824764B TWI824764B TW111138309A TW111138309A TWI824764B TW I824764 B TWI824764 B TW I824764B TW 111138309 A TW111138309 A TW 111138309A TW 111138309 A TW111138309 A TW 111138309A TW I824764 B TWI824764 B TW I824764B
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- 238000000465 moulding Methods 0.000 claims abstract description 116
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- 238000009713 electroplating Methods 0.000 description 4
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- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 2
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- 230000015572 biosynthetic process Effects 0.000 description 1
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Classifications
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Abstract
本申請提供一種堆疊型封裝結構及其製造方法。堆疊型封裝結構包括上重佈線層、第一晶片和上模封層。該第一晶片設置在該上重佈線層上且與該上重佈線層電連接。該上模封層設置在該第一晶片和該上重佈線層上,配置為封裝該第一晶片。該上模封層包含凹槽,該凹槽相對於該上模封層遠離該上重佈線層的表面凹陷,以及該凹槽環繞地形成在該上模封層的外側邊。
Description
本申請涉及一種半導體領域,特別是關於一種堆疊型封裝結構及其製造方法。
目前,先進封裝主要有兩種發展方向,一是減少封裝面積,使其接近晶片大小,另一種則是將多個晶片整合在同一封裝內,增加封裝內部整合程度。使用多晶片堆疊封裝技術或系統級封裝技術可實現將多種不同功能的晶片整合在產品中,進而製造出輕質、緊湊、高速、多功能和高性能的產品。因此,對於多晶片的封裝結構,如何在不增加封裝寬度的前提下實現多個元件之間的電連接,為目前產業界研究的焦點和需解決的技術問題。
有鑑於此,本申請提供一種堆疊型封裝結構及其製造方法,以解決上述技術問題。
本申請提供一種堆疊型封裝結構及其製造方法,其確保了在不增加封裝尺寸的前提下實現多個元件之間的電連接。
在一方面,本申請提供一種堆疊型封裝結構,包括:上重佈線層、第一晶片和上模封層。該上重佈線層包含第一面和相對該第一面之第二面。該第
一晶片設置在該上重佈線層之該第一面上且與該上重佈線層電連接。該上模封層設置在該第一晶片和該上重佈線層之該第一面上,配置為封裝該第一晶片。該上模封層包含凹槽,該凹槽相對於該上模封層遠離該上重佈線層的表面凹陷,以及該凹槽環繞地形成在該上模封層的外側邊。
在一些實施例中,該上模封層遠離該上重佈線層的該表面至少包含第一階梯面和第二階梯面,且該第一階梯面為該凹槽之底面。
在一些實施例中,該堆疊型封裝結構還包含封蓋,該封蓋設置在該上模封層上。
在一些實施例中,該上模封層還包含開口,該開口用於曝露出該第一晶片的非主動面。該堆疊型封裝結構還包含一熱介面材料,該熱介面材料設置在該上模封層上且覆蓋該第一晶片的該非主動面,以及該熱介面材料設置在該封蓋和該上模封層之間。
在一些實施例中,該堆疊型封裝結構還包含一電磁干擾(EMI)屏蔽層,該EMI屏蔽層覆蓋該上模封層的該表面。
在一些實施例中,該堆疊型封裝結構還包含第二晶片和第三晶片。該第二晶片和該第三晶片設置在該上重佈線層之該第二面上且與該上重佈線層電連接,該第二晶片與該第三晶片橫向相鄰,以及該第一晶片通過該上重佈線層與該第三晶片和該第二晶片電連接。
在一些實施例中,該堆疊型封裝結構還包含下模封層。該下模封層設置在該上重佈線層之該第二面上,配置為封裝該第二晶片和該第三晶片,以及其中該下模封層的材料不同於該上模封層的材料。
在一些實施例中,該下模封層的該材料的熱膨脹係數大於該上模封層的該材料的熱膨脹係數。
在一些實施例中,該堆疊型封裝結構還包含:下重佈線層、至少一導電柱和複數個焊球。該下重佈線層設置在該下模封層遠離該上重佈線層的表面。該至少一導電柱電連接該上重佈線層和該下重佈線層。該複數個焊球設置在該下重佈線層遠離該下模封層的表面。
在一些實施例中,該至少一導電柱在該下重佈線層的正投影與該第一晶片在該下重佈線層的正投影重疊,並且該第一晶片通過該上重佈線層與該至少一導電柱電連接。
在另一方面,本申請還提供一種堆疊型封裝結構之製造方法,包含:提供一載板;在該載板上設置第一晶片;在該第一晶片和該載板上形成模封層,其中該模封層配置為封裝該第一晶片;在該第一晶片和該模封層遠離該載板的表面形成上重佈線層,其中該第一晶片與該上重佈線層電連接;移除該載板;以及去除部分的模封層以形成上模封層,其中該上模封層包含凹槽,該凹槽相對於該上模封層遠離該上重佈線層的表面凹陷,以及該凹槽環繞地形成在該上模封層的外側邊。
在一些實施例中,該上模封層遠離該上重佈線層的該表面至少包含第一階梯面和第二階梯面,且該第一階梯面為該凹槽之底面。
在一些實施例中,在形成該上模封層之後,該製造方法還包含:在該上模封層上設置封蓋。
在一些實施例中,該上模封層還包含開口,該開口用於曝露出該第一晶片的非主動面。該製造方法還包含:在該上模封層上設置一熱介面材料,
其中該熱介面材料覆蓋該第一晶片的該非主動面,以及該熱介面材料設置在該封蓋和該上模封層之間。
在一些實施例中,在形成該上模封層之後,該製造方法還包含:在該上模封層的該表面形成電磁干擾(EMI)屏蔽層。
在一些實施例中,形成該上重佈線層之後,該製造方法還包含:在該上重佈線層之遠離該第一晶片之一面設置第二晶片和第三晶片,其中該第二晶片和該第三晶片與該上重佈線層電連接,該第二晶片和該第三晶片橫向相鄰,以及該第一晶片通過該上重佈線層與該第三晶片和該第二晶片電連接。
在一些實施例中,該製造方法還包含:在該上重佈線層之遠離該第一晶片之一面形成下模封層,其中該下模封層配置為封裝該第二晶片和該第三晶片,以及該下模封層的材料不同於該上模封層的材料。
在一些實施例中,該下模封層的該材料的熱膨脹係數大於該上模封層的該材料的熱膨脹係數。
在一些實施例中,在形成該下模封層之前,該製造方法還包含:在該上重佈線層之遠離該第一晶片之一面形成至少一導電柱;在形成該下模封層之後,該製造方法還包含:在該下模封層遠離該上重佈線層的表面形成下重佈線層,其中該至少一導電柱電連接該上重佈線層和該下重佈線層;以及在該下重佈線層遠離該下模封層的表面形成複數個焊球。
在一些實施例中,該至少一導電柱在該下重佈線層的正投影與該第一晶片在該下重佈線層的正投影重疊,並且該第一晶片通過該上重佈線層與該至少一導電柱電連接。
相較於現有技術,在本申請的堆疊型封裝結構及其製造方法中,採用內埋式技術將導電柱、第一晶片、第二晶片和第三晶片等設置在堆疊封裝結構內部,最大限度地減少了堆疊封封裝結構的外形尺寸,進而保持封裝高度要求。再者,藉由上重佈線層和下重佈線層實現了小型化且緊湊設計的多晶片的三維封裝。另一方面,本申請藉由限定上模封層和下模封層的材料及結構,可有效地解決堆疊封裝結構發生翹曲的問題。此外,藉由設置散熱材料和EMI屏蔽層可進一步提升堆疊封封裝結構的整體性能。
10、20:堆疊型封裝結構
110:上重佈線層
111:第一面
112:第二面
120:導電柱
130:第二晶片
131:第一底膠層
132:第二凸塊
133:第一導電端子
140:第三晶片
141:第二底膠層
142:第三凸塊
143:第二導電端子
150:下模封層
160:下重佈線層
170:焊球
180:第一晶片
181:非主動面
182:第一凸塊
190’:模封層
190:上模封層
191:凹槽
1921:第一階梯面
1922:第二階梯面
193:開口
101:熱介面材料
102:封蓋
201:EMI屏蔽層
301:載板
302:分離層
L:分離線
圖1顯示根據本申請第一實施例之堆疊型封裝結構之示意圖;圖2A至圖2P顯示一系列的剖面圖,用於闡明圖1的堆疊型封裝結構的製造流程;以及圖3顯示根據本申請第二實施例之堆疊型封裝結構之示意圖。
現參考附圖更全面地描述示例實施方式。然而,示例實施方式能夠以多種形式實施,且不應被理解為限於在此闡述的範例。相反,提供這些實施方式使得本申請將更加全面和完整,並將示例實施方式的構思全面地傳達給本領域的技術人員。附圖僅為本申請的示意性圖解,並非一定是按比例繪製。圖中相同的附圖標記表示相同或類似的部分,因而將省略對它們的重複描述。
參照圖1,其顯示根據本申請第一實施例之堆疊型封裝結構之示意圖。堆疊型封裝結構10包含上重佈線層(redistribution layer,RDL)110、第一晶片180、上模封層190、導電柱120、第二晶片130、第三晶片140、下模封層150、下重佈線層160和焊球170。
如圖1所示,上重佈線層110包含第一面111和相對第一面111之第二面112。通過對應的製程使得上重佈線層110的內部形成有導線以及位於第一面111和第二面112的複數個連接墊,其中導線配置為連接位於第一面111的連接墊和位於第二面112的連接墊。
如圖1所示,複數個導電柱120設置在上重佈線層110之第二面112上且與上重佈線層110電連接。具體來說,上重佈線層110的第二面112通過其對應的連接墊與複數個導電柱120電連接。在本實施例中導電柱120的數量為三個,惟不侷限於此。導電柱120可由銅、鋁、錫、金、銀或上述之組合所構成。
如圖1所示,第二晶片130和第三晶片140設置在上重佈線層110之第二面112上且與上重佈線層110電連接。第二晶片130和第三晶片140橫向相鄰。具體來說,第二晶片130的主動面包括複數個第二凸塊132以及第三晶片140的主動面包括複數個第三凸塊142。第二凸塊132和第三凸塊142的材料可以是或可包括銅、金、鎳、錫銀合金、金屬合金等。第二晶片130和第三晶片140執行覆晶接合以將第二凸塊132和第三凸塊142接合到上重佈線層110,以實現第二晶片130和第三晶片140與上重佈線層110的電連接。具體來說,上重佈線層110之第二面112設置有暴露在外的複數個連接墊。該些連接墊亦與第二晶片130的第二凸塊132以及第三晶片140的第三凸塊142對應設置,並且可藉由焊接等技術將上重佈線層110之連接墊與第二凸塊132和第三凸塊142對應連接。在本實施例中,透過
第二凸塊132和第三凸塊142實現第二晶片130和第三晶片140與上重佈線層110的電連接,可避免因外部施加應力或製程內含應力,致使第二晶片130和第三晶片140的低介電係數(low-k)材料破裂(cracking),進而造成晶片的功能異常或失效和可靠度低之問題。應當注意的是,上重佈線層110之第二面112還可連接三個以上的晶片,即與第二晶片130和第三晶片140橫向相鄰的額外晶片,不侷限於此。
如圖1所示,在第二晶片130和上重佈線層110之間包括第一導電端子133,以及在第三晶片140和上重佈線層110之間包括第二導電端子143。第一導電端子133配置為連接第二晶片130的第二凸塊132和上重佈線層110,以及第二導電端子143配置為連第三晶片140的第三凸塊142和上重佈線層110。第一導電端子133和第二導電端子143可藉由使用植球製程、電鍍製程或其他合適的製程形成。在本實施例中,第一導電端子133和第二導電端子143是使用例如SnAg的焊接材料並且採用回焊技術而形成,從而降低製造成本並提高製造效率。應當理解的是,根據設計要求,第一導電端子133和第二導電端子143可採用其他可能的材料和形狀,不侷限於此。可選地,藉由焊接製程和回焊製程以增強第一導電端子133和第二導電端子143和上重佈線層110的對應連接墊之間的接合力。
如圖1所示,在上重佈線層110和第二晶片130之間設置有第一底膠層131。第一底膠層131形成在第二晶片130的主動面和上重佈線層110的第二面112之間的間隙中,且橫向地覆蓋第二晶片130的主動面和上重佈線層110的第二面112之間的連接件,例如第二晶片130的第二凸塊132、上重佈線層110的連接墊和第一導電端子133。藉由設置第一底膠層131可增強第二晶片130和上重佈線層110之間的接合力和增強接合的可靠性。
如圖1所示,相似地,在上重佈線層110和第三晶片140之間設置有第二底膠層141。第二底膠層141形成在第三晶片140的主動面和上重佈線層110的第二面112之間的間隙中,且橫向地覆蓋第三晶片140的主動面和上重佈線層110的第二面112之間的連接件,例如第三晶片140的第三凸塊142、上重佈線層110的連接墊和第二導電端子143。藉由設置第二底膠層141可增強第三晶片140和上重佈線層110之間的接合力和增強接合的可靠性。
如圖1所示,下模封層150設置在上重佈線層110的第二面112、第二晶片130和第三晶片140上。下模封層150將上重佈線層110的第二面112和設置在其上的元件(導電柱120、第二晶片130和第三晶片140)包封,並僅僅曝露出導電柱120之對應的表面,以用於與後續形成的元件電連接。
如圖1所示,下重佈線層160設置在下模封層150遠離上重佈線層110的表面。下重佈線層160包含相對的兩表面。通過對應的製程使得下重佈線層160的內部形成有導線以及位於該兩表面的複數個連接墊,其中導線配置為連接位於該兩表面的連接墊。導電柱120連接下重佈線層160的連接墊和上重佈線層110的連接墊,進而電連接上重佈線層110和下重佈線層160。在本實施例中,第二晶片130和第三晶片140的背面(非主動面)不與下重佈線層160直接接觸。也就是說,第二晶片130和第三晶片140的背面與下重佈線層160之間具有模具間隙(mold clearance)。
如圖1所示,複數個焊球170設置在下重佈線層160遠離下模封層150的表面。焊球170可藉由使用植球製程、電鍍製程或其他合適的製程形成。在一些實施例中,焊球170是藉由植球製程所形成的焊球,從而降低製造成本並提
高製造效率。應當理解的是,根據設計要求,焊球170可採用其他可能的材料和形狀,不侷限於此。
如圖1所示,第一晶片180設置在上重佈線層110之第一面111上且與上重佈線層110電連接。第一晶片180包含主動面和相對主動面的非主動面181。在本實施例中,第一晶片180的主動面與第二晶片130和第三晶片140的主動面採用面對面的設置。第一晶片180的主動面上設置有複數個第一凸塊182。應當理解的是,在製造時,第一晶片180是採用面朝上(face-up)配置,因此在一些實施例中,第一晶片180可不包含第一凸塊182。第一凸塊182的材料可以是或可包括銅、金、鎳、金屬合金等。在製造時,第一晶片180先被設置在載板上,接著依序形成上模封層190和上重佈線層110。第一晶片180的第一凸塊182接合到上重佈線層110,以實現第一晶片180與上重佈線層110的電連接。具體來說,先在第一晶片180上塗佈一層介電材料(如Polyimide),接著再形成上重佈線層110。後續形成的上重佈線層110具有與第一晶片180的第一凸塊182對應形成的複數個連接墊,並且可藉由適當地連接技術將連接墊與第一凸塊182對應連接。在本實施例中,從圖1的頂部觀視時,第一晶片180與第二晶片130部分重疊,並且第一晶片180也與第三晶片140部分重疊。藉此設計,有利於實現小型化且緊湊設計的多晶片的三維封裝。
在本實施例中,第一晶片180可為系統單晶片(system on a chip,SoC)。第二晶片130和第三晶片140可為儲存器晶片等,例如非揮發性和/或揮發性儲存器。非揮發性儲存器可包括唯讀儲存器(read only memory,ROM)、可程式化ROM(PROM)、電可程式化ROM(EPROM)、電可擦除可程式化ROM(EEPROM)或快閃儲存器。揮發性儲存器可包括隨機存取儲存器(RAM)等。
如圖1所示,第一晶片180通過該上重佈線層110與導電柱120、第二晶片130和第三晶片140電連接。具體來說,第一晶片180的部分的第一凸塊182通過上重佈線層110和導電柱120連接到訊號/電源/接地的I/O端子的焊球170。第一晶片180的其餘的第一凸塊182通過上重佈線層110的內部細間距導線連接到第二晶片130和第三晶片140。第二晶片130和第三晶片140藉由朝向上重佈線層110的第二凸塊132和第三凸塊142連接第一晶片180的第一凸塊182與上重佈線層110中較短的訊號路徑。
再者,其中之一導電柱120在下重佈線層160的正投影與第一晶片180在下重佈線層160的正投影重疊。藉由尺寸較大的導電柱120縱向地且直接地連接第一晶片180、上重佈線層110和下重佈線層160,可以有效地降低阻抗、縮短電源路徑和降低功率衰退(power drop),進而獲得良好的電源完整性能。
如圖1所示,上模封層190設置在第一晶片180和上重佈線層110之第一面111上,配置為封裝第一晶片180。在本實施例中,導電柱120、第一晶片180、第二晶片130和第三晶片140採用內埋(embedded)式技術堆疊地設置,以最大限度地減少了堆疊型封裝結構10的外形尺寸,並且確保多晶片之間的堅固互連,進而保持封裝高度要求。也就是說,多晶片在不同的扇出重佈線層上進行三維堆疊。因此,在本申請的堆疊型封裝結構10中,在符合封裝寬度的條件下,藉由上重佈線層110和下重佈線層160實現了小型化且緊湊設計的多晶片的三維封裝,進而為本申請的堆疊型封裝結構10在高端產品的應用提供更多的設計靈活性和自由度。另一方面,內埋式技術的優點包括可提昇電性、降低雜訊、縮小產品尺寸(包括長度和寬度),以及降低成本等。再者,本申請藉由上重佈線層110和下重佈線層160的精細佈線作為多晶片之間的訊號傳遞路徑,可有效地提高訊
號傳遞的速度和縮小佈線面積,進而確保了多晶片之間的電連接,和實現了高電路密度和細間距的設計。因此,多晶片之間的訊號傳遞速度和訊號完整性可以得到更好的表現。
在本實施例中,下模封層150的材料可不同於上模封層190的材料。具體來說,下模封層150的該材料的熱膨脹係數大於上模封層190的該材料的熱膨脹係數。在堆疊型封裝結構10中,由於下模封層150內包封的元件數量多於上模封層190內包封的元件數量,因此下模封層150的材料的使用量少於上模封層190的材料的使用量。由於模封層150/190和模封層150/190內部的元件(如導電柱120、第一晶片180、第二晶片130和第三晶片140)的熱膨脹係數不同,藉由將下模封層150的該材料的熱膨脹係數設置於大於上模封層190的該材料的熱膨脹係數可避免因為上下兩模封層及內部元件的整體熱膨脹程度的差異而導致堆疊型封裝結構10翹曲變形。
如圖1所示,上模封層190包含凹槽191。凹槽191相對於上模封層190遠離上重佈線層110的表面凹陷,以及凹槽191環繞地形成在上模封層190的外側邊。具體來說,上模封層190遠離上重佈線層110的該表面至少包含第一階梯面1921和第二階梯面1922,且第一階梯面1921為凹槽191之底面。在本實施例的堆疊型封裝結構10中,下模封層150的材料的使用量少於上模封層190的材料的使用量,並且封裝結構的翹曲變形通常是發生在其外周圍。因此,藉由將上模封層190的部分去除以在其外表面的周緣形成凹槽191,可有效地平衡上模封層190內部的應力,進而避免堆疊型封裝結構10翹曲變形。
如圖1所示,堆疊型封裝結構10還包含熱介面材料101和封蓋102。熱介面材料101和封蓋102依序設置在上模封層190上,並且熱介面材料101設置
在封蓋102和上模封層190之間。封蓋102較佳地以金屬材料製成。封蓋102的外周緣通過熱介面材料101與第一階梯面1921接觸。在本實施例中,藉由封蓋102覆蓋住第一晶片180和上模封層190可避免第一晶片180和上模封層190受損,以及提高堆疊型封裝結構10的散熱性能。再者,封蓋102縱向地覆蓋住第一晶片180和上模封層190,尤其是覆蓋住上模封層190的周緣。由於封蓋102由強度較高的金屬材質製成,因此封蓋102的設置可有效地增強堆疊型封裝結構10的穩定性,抑制堆疊型封裝結構10發生翹曲變形。
如圖1所示,在本實施例中,對應於第一階梯面1921的位置,上模封層190與上重佈線層110之間不包含額外的元件。也就是說,對應於第一階梯面1921的位置,沒有額外的元件設置在上重佈線層110的第一面111上。因此,還確保了封蓋102在形成時或者在抑制變形時產生的內應力不會損壞額外的元件。
如圖1所示,上模封層190還包含開口193,該開口193用於曝露出第一晶片180的非主動面181。熱介面材料101覆蓋第一晶片180的非主動面181,並且熱介面材料101設置在封蓋102與上模封層190和第一晶片180接觸的表面。因此,藉由熱介面材料101的設計,確保堆疊型封裝結構10具有良好的散熱性能。
在本實施例中,採用內埋式技術將導電柱120、第一晶片180、第二晶片130和第三晶片140等設置在堆疊型封裝結構10內部,最大限度地減少了堆疊封封裝結構10的外形尺寸,進而保持封裝高度要求。再者,藉由上重佈線層110和下重佈線層160實現了小型化且緊湊設計的多晶片的三維封裝。另一方面,本申請藉由限定上模封層190和下模封層150的材料及結構,可有效地解決堆疊封裝結構發生翹曲的問題。
參照圖2A至圖2P,其顯示一系列的剖面圖,用於闡明圖1的堆疊型封裝結構的製造流程。
如圖2A所示,提供一載板301,並且在載板301的一表面形成分離層302。分離層302配置為將後續形成的膜層從載板301的表面分離。此外,分離層302還可以為載板301和後續形成的膜層之間提供足夠的結合力(通過黏合和/或其他結合力),使得後續的膜層可順利形成。
如圖2B所示,在載板301上設置第一晶片180。具體來說,第一晶片180設置在分離層302遠離載板301的表面上。第一晶片180包含主動面和相對主動面的非主動面181。第一晶片180的主動面上設置有複數個第一凸塊182。第一凸塊182的材料可以是或可包括銅、金、鎳、金屬合金等。應當理解的是,在製造時,第一晶片180是採用面朝上(face-up)配置,因此在一些實施例中,第一晶片180可不包含第一凸塊182。
如圖2C所示,在第一晶片180和載板301上形成模封層190’。模封層190’配置為封裝第一晶片180。
如圖2D所示,對模封層190’施加一薄化製程,以減少模封層190’的厚度和曝露出第一晶片180的第一凸塊182的對應表面,以用於與後續形成的元件電連接。可選地,薄化製程可藉由使用研磨機來實現。
如圖2E所示,在第一晶片180和模封層190’遠離載板301的表面形成上重佈線層110。第一晶片180與上重佈線層110電連接。上重佈線層110包含第一面111和相對第一面111之第二面112。通過對應的製程使得上重佈線層110的內部形成有導線以及位於第一面111和第二面112的複數個連接墊,其中導線配置為連接位於第一面111的連接墊和位於第二面112的連接墊。
如圖2E所示,第一晶片180的第一凸塊182接合到上重佈線層110,以實現第一晶片180與上重佈線層110的電連接。具體來說,先在第一晶片180上塗佈一層介電材料(如Polyimide),接著再形成上重佈線層110。後續形成的上重佈線層110具有與第一晶片180的第一凸塊182對應形成的複數個連接墊,並且可藉由適當地連接技術將連接墊與第一晶片180的第一凸塊182對應連接。
如圖2F所示,在上重佈線層110之第二面112上形成複數個導電柱120,並且複數個導電柱120與上重佈線層110電連接。具體來說,上重佈線層110的第二面112通過其對應的連接墊與複數個導電柱120電連接。在本實施例中導電柱120的數量為六個,惟不侷限於此。導電柱120可由銅、鋁、錫、金、銀或上述之組合所構成。
如圖2G所示,形成上重佈線層110之後,該製造方法還包含:在上重佈線層110之第二面112上形成第二晶片130和第三晶片140,並且第二晶片130和第三晶片140與上重佈線層110電連接。應當理解的是,在本實施例中是採用先形成導電柱120再形成第二晶片130和第三晶片140,然而,在其他實施例中,亦可以採用先形成第二晶片130和第三晶片140再形成導電柱120,惟不局限於此。在本實施例中,從圖2G的頂部觀視時,第一晶片180與第二晶片130部分重疊,並且第一晶片180也與第三晶片140部分重疊。藉此設計,有利於實現小型化且緊湊設計的多晶片的三維封裝。
如圖2G所示,第二晶片130和第三晶片140橫向相鄰。具體來說,第二晶片130的主動面包括複數個第二凸塊132以及第三晶片140的主動面包括複數個第三凸塊142。第二凸塊132和第三凸塊142的材料可以是或可包括銅、金、鎳、錫銀合金、金屬合金等。第二晶片130和第三晶片140執行覆晶接合以將第二
凸塊132和第三凸塊142接合到上重佈線層110,以實現第二晶片130和第三晶片140與上重佈線層110的電連接。具體來說,上重佈線層110之第二面112設置有暴露在外的複數個連接墊。該些連接墊亦與第二晶片130的第二凸塊132以及第三晶片140的第三凸塊142對應設置,並且可藉由焊接等技術將上重佈線層110之連接墊與第二凸塊132和第三凸塊142對應連接。在本實施例中,透過第二凸塊132和第三凸塊142實現第二晶片130和第三晶片140與上重佈線層110的電連接,可避免因外部施加應力或製程內含應力,致使第二晶片130和第三晶片140的低介電係數(low-k)材料破裂(cracking),進而造成晶片的功能異常或失效和可靠度低之問題。應當注意的是,上重佈線層110之第二面112還可連接三個以上的晶片,即與第二晶片130和第三晶片140橫向相鄰的額外晶片,不侷限於此。在本實施例中,第一晶片180的主動面與第二晶片130和第三晶片140的主動面採用面對面的設置。
如圖2G所示,在第二晶片130和上重佈線層110之間包括第一導電端子133,以及在第三晶片140和上重佈線層110之間包括第二導電端子143。第一導電端子133配置為連接第二晶片130的第二凸塊132和上重佈線層110,以及第二導電端子143配置為連接第三晶片140的第三凸塊142和上重佈線層110。第一導電端子133和第二導電端子143可藉由使用植球製程、電鍍製程或其他合適的製程形成。在本實施例中,第一導電端子133和第二導電端子143是使用例如SnAg的焊接材料並且採用回焊技術而形成,從而降低製造成本並提高製造效率。應當理解的是,根據設計要求,第一導電端子133和第二導電端子143可採用其他可能的材料和形狀,不侷限於此。可選地,藉由焊接製程和回焊製程以增強第一導電端子133和第二導電端子143和上重佈線層110的對應連接墊之間的接合力。
如圖2G所示,在上重佈線層110和第二晶片130之間設置有第一底膠層131。第一底膠層131形成在第二晶片130的主動面和上重佈線層110的第二面112之間的間隙中,且橫向地覆蓋第二晶片130的主動面和上重佈線層110的第二面112之間的連接件,例如第二晶片130的第二凸塊132、上重佈線層110的連接墊和第一導電端子133。藉由設置第一底膠層131可增強第二晶片130和上重佈線層110之間的接合力和增強接合的可靠性。
如圖2G所示,相似地,在上重佈線層110和第三晶片140之間設置有第二底膠層141。第二底膠層141形成在第三晶片140的主動面和上重佈線層110的第二面112之間的間隙中,且橫向地覆蓋第三晶片140的主動面和上重佈線層110的第二面112之間的連接件,例如第三晶片140的第三凸塊142、上重佈線層110的連接墊和第二導電端子143。藉由設置第二底膠層141可增強第三晶片140和上重佈線層110之間的接合力和增強接合的可靠性。
如圖2H所示,在上重佈線層110的第二面112、第二晶片130和第三晶片140上形成下模封層150。下模封層150將上重佈線層110的第二面112和設置在其上的元件(導電柱120、第二晶片130和第三晶片140)包封。
如圖2I所示,對下模封層150施加一薄化製程,以減少下模封層150的厚度和曝露出導電柱120的對應表面,以用於與後續形成的元件電連接。可選地,薄化製程可藉由使用研磨機來實現。
如圖2J所示,在下模封層150遠離上重佈線層110的表面形成下重佈線層160。下重佈線層160包含相對的兩表面。通過對應的製程使得上重佈線層110的內部形成有導線以及位於該兩表面上的複數個連接墊,其中導線配置為連接分別位於相對的兩表面的連接墊。導電柱120連接下重佈線層160的連接墊和
上重佈線層110的連接墊,進而電連接上重佈線層110和下重佈線層160。在本實施例中,第二晶片130和第三晶片140的背面(非主動面)不與下重佈線層160直接接觸。也就是說,第二晶片130和第三晶片140的背面與下重佈線層160之間具有模具間隙(mold clearance)。
在本實施例中,第一晶片180可為系統單晶片(system on a chip,SoC)。第二晶片130和第三晶片140可為儲存器晶片等,例如非揮發性和/或揮發性儲存器。非揮發性儲存器可包括唯讀儲存器(read only memory,ROM)、可程式化ROM(PROM)、電可程式化ROM(EPROM)、電可擦除可程式化ROM(EEPROM)或快閃儲存器。揮發性儲存器可包括隨機存取儲存器(RAM)等。
如圖2K所示,移除載板301。具體來說,藉由分離層302將載板301與模封層190’分離。載板301可對其上方形成的元件提供良好的支撐性,以避免在圖2A至圖2J對應的步驟中結構發生形變的風險。如圖2K所示,模封層190’還包含開口193,該開口193用於曝露出第一晶片180的非主動面181。
如圖2L所示,在下重佈線層160遠離下模封層150的表面形成複數個焊球170。焊球170可藉由使用植球製程、電鍍製程或其他合適的製程形成。在一些實施例中,焊球170是藉由植球製程所形成的焊球,從而降低製造成本並提高製造效率。應當理解的是,根據設計要求,焊球170可採用其他可能的材料和形狀,不侷限於此。
如圖2L所示,第一晶片180通過該上重佈線層110與導電柱120、第二晶片130和第三晶片140電連接。具體來說,第一晶片180的部分的第一凸塊182通過上重佈線層110和導電柱120連接到訊號/電源/接地的I/O端子的焊球170。第一晶片180的其餘的第一凸塊182通過上重佈線層110的內部細間距導線連接到
第二晶片130和第三晶片140。第二晶片130和第三晶片140藉由朝向上重佈線層110的第二凸塊132和第三凸塊142連接第一晶片180的第一凸塊182與上重佈線層110中較短的訊號路徑。
再者,如圖2L所示,其中之一導電柱120在下重佈線層160的正投影與第一晶片180在下重佈線層160的正投影重疊。藉由尺寸較大的導電柱120縱向地且直接地連接第一晶片180、上重佈線層110和下重佈線層160,可以有效地降低阻抗、縮短電源路徑和降低功率衰退(power drop),進而獲得良好的電源完整性能。
如圖2L所示,導電柱120、第一晶片180、第二晶片130和第三晶片140採用內埋(embedded)式技術堆疊地設置,以最大限度地減少了堆疊型封裝結構10的外形尺寸,並且確保多晶片之間的堅固互連,進而保持封裝高度要求。也就是說,多晶片在不同的扇出重佈線層上進行三維堆疊。因此,在本申請的堆疊型封裝結構10中,在符合封裝寬度的條件下,藉由上重佈線層110和下重佈線層160實現了小型化且緊湊設計的多晶片的三維封裝,進而為本申請的堆疊型封裝結構10在高端產品的應用提供更多的設計靈活性和自由度。另一方面,內埋式技術的優點包括可提昇電性、降低雜訊、縮小產品尺寸(包括長度和寬度),以及降低成本等。再者,本申請藉由上重佈線層110和下重佈線層160的精細佈線作為多晶片之間的訊號傳遞路徑,可有效地提高訊號傳遞的速度和縮小佈線面積,進而確保了多晶片之間的電連接,和實現了高電路密度和細間距的設計。因此,多晶片之間的訊號傳遞速度和訊號完整性可以得到更好的表現。
如圖2M所示,將圖2L對應的半成品沿著分離線L斷開,以形成多個獨立的堆疊型封裝結構10。可選地,半成品的斷開可藉由切割機來實現。
如圖2N所示,去除部分的模封層190’以形成上模封層190。上模封層190包含凹槽191,凹槽191相對於上模封層190遠離上重佈線層110的表面凹陷,以及凹槽191環繞地形成在上模封層190的外側邊。具體來說,上模封層190遠離上重佈線層110的該表面至少包含第一階梯面1921和第二階梯面1922,且第一階梯面1921為凹槽191之底面。在本實施例的堆疊型封裝結構10中,下模封層150的材料的使用量少於上模封層190的材料的使用量,並且封裝結構的翹曲變形通常是發生在其外周圍。因此,藉由將上模封層190的部分去除以在其外表面的周緣形成凹槽191,可有效地平衡上模封層190內部的應力,進而避免堆疊型封裝結構10翹曲變形。
在本實施例中,下模封層150的材料不同於上模封層190的材料。具體來說,下模封層150的該材料的熱膨脹係數大於上模封層190的該材料的熱膨脹係數。在堆疊型封裝結構10中,由於下模封層150內包封的元件數量多於上模封層190內包封的元件數量,因此下模封層150的材料的使用量少於上模封層190的材料的使用量。由於模封層150/190和模封層150/190內部的元件(如導電柱120、第一晶片180、第二晶片130和第三晶片140)的熱膨脹係數不同,藉由將下模封層150的該材料的熱膨脹係數設置於大於上模封層190的該材料的熱膨脹係數可避免因為上下兩模封層及內部元件的整體熱膨脹程度的差異而導致堆疊型封裝結構10翹曲變形。
如圖2O所示,在形成上模封層190之後,該製造方法還包含:在上模封層190上依序設置熱介面材料101和封蓋102,其中熱介面材料101位於上模封層190與封蓋102之間。封蓋102較佳地以金屬材料製成。封蓋102的外周緣通過熱介面材料101與第一階梯面1921接觸。在本實施例中,藉由封蓋102覆蓋住第
一晶片180和上模封層190可避免第一晶片180和上模封層190受損,以及提高堆疊型封裝結構10的散熱性能。再者,封蓋102縱向地覆蓋住第一晶片180和上模封層190,尤其是覆蓋住上模封層190的周緣。由於封蓋102由強度較高的金屬材質製成,因此封蓋102的設置可有效地增強堆疊型封裝結構10的穩定性,以及抑制堆疊型封裝結構10發生翹曲變形。如圖2O所示,在本實施例中,對應於第一階梯面1921的位置,上模封層190與上重佈線層110之間不包含額外的元件。也就是說,對應於第一階梯面1921的位置,沒有額外的元件設置在上重佈線層110的第一面111上。因此,確保了封蓋102在形成時或者在抑制變形時產生的內應力不會損壞額外的元件。
如圖2P所示,將封蓋102設置在上模封層190上之後,形成了本申請的堆疊型封裝結構10。熱介面材料101覆蓋第一晶片180的非主動面181,並且熱介面材料101設置在封蓋102與上模封層190和第一晶片180接觸的表面。因此,藉由熱介面材料101的設計,確保堆疊型封裝結構10具有良好的散熱性能。
在本實施例中,採用內埋式技術將導電柱120、第一晶片180、第二晶片130和第三晶片140等設置在堆疊型封裝結構10內部,最大限度地減少了堆疊封封裝結構10的外形尺寸,進而保持封裝高度要求。再者,藉由上重佈線層110和下重佈線層160實現了小型化且緊湊設計的多晶片的三維封裝。另一方面,本申請藉由限定上模封層190和下模封層150的材料及結構,可有效地解決堆疊封裝結構發生翹曲的問題。
圖3顯示根據本申請第二實施例之堆疊型封裝結構之示意圖。第二實施例之堆疊型封裝結構20包括上重佈線層110、第一晶片180、上模封層190、導電柱120、第二晶片130、第三晶片140、下模封層150、下重佈線層160和焊球
170,其中該些元件的特徵與之造方法與第一實施例之堆疊型封裝結構10的對應元件相同,在此不加以贅述。
如圖3所示,第二實施例之堆疊型封裝結構20與第一實施例之堆疊型封裝結構10的結構大致相同,兩者差別在於,第二實施例之堆疊型封裝結構20整面設置的電磁干擾(EMI)屏蔽層201。EMI屏蔽層201覆蓋上模封層190的遠離上重佈線層110的表面。具體來說,EMI屏蔽層201為整面形成,並且覆蓋上模封層190的第一階梯面1921和第二階梯面1922。可選地,EMI屏蔽層201為多層金屬層結構,使用例如Ti/Cu或Ti/Cu/Ti的材料並且採用物理氣相沉積(PVD)技術而形成。在本實施例中,藉由設置EMI屏蔽層201可提高堆疊型封裝結構20的抗電磁干擾的能力。
在本申請的堆疊型封裝結構及其製造方法中,採用內埋式技術將導電柱、第一晶片、第二晶片和第三晶片等設置在堆疊封裝結構內部,最大限度地減少了堆疊封封裝結構的外形尺寸,進而保持封裝高度要求。再者,藉由上重佈線層和下重佈線層實現了小型化且緊湊設計的多晶片的三維封裝。另一方面,本申請藉由限定上模封層和下模封層的材料及結構,可有效地解決堆疊封裝結構發生翹曲的問題。此外,藉由設置散熱材料和EMI屏蔽層可進一步提升堆疊封封裝結構的整體性能。
10:堆疊型封裝結構
110:上重佈線層
111:第一面
112:第二面
120:導電柱
130:第二晶片
131:第一底膠層
132:第二凸塊
133:第一導電端子
140:第三晶片
141:第二底膠層
142:第三凸塊
143:第二導電端子
150:下模封層
160:下重佈線層
170:焊球
180:第一晶片
181:非主動面
182:第一凸塊
190:上模封層
191:凹槽
1921:第一階梯面
1922:第二階梯面
193:開口
101:熱介面材料
102:封蓋
Claims (20)
- 一種堆疊型封裝結構,包括:一上重佈線層,包含一第一面和相對該第一面之一第二面;一第一晶片,設置在該上重佈線層之該第一面上且與該上重佈線層電連接;以及一上模封層,設置在該第一晶片和該上重佈線層之該第一面上,配置為封裝該第一晶片,其中該上模封層包含一凹槽,該凹槽相對於該上模封層遠離該上重佈線層的表面凹陷,以及該凹槽環繞地形成在該上模封層的外表面的周緣。
- 如請求項1的堆疊型封裝結構,其中該上模封層遠離該上重佈線層的該表面至少包含第一階梯面和第二階梯面,且該第一階梯面為該凹槽之底面。
- 如請求項2的堆疊型封裝結構,其中該堆疊型封裝結構還包含一封蓋,該封蓋設置在該上模封層上。
- 如請求項3的堆疊型封裝結構,其中該上模封層還包含一開口,該開口用於曝露出該第一晶片的非主動面;以及其中該堆疊型封裝結構還包含一熱介面材料,該熱介面材料設置在該上模封層上且覆蓋該第一晶片的該非主動面,以及該熱介面材料設置在該封蓋和該上模封層之間。
- 如請求項1的堆疊型封裝結構,其中該堆疊型封裝結構還包含一電磁干擾(EMI)屏蔽層,該EMI屏蔽層覆蓋該上模封層的該表面。
- 如請求項1的堆疊型封裝結構,其中該堆疊型封裝結構還包含一第二晶片和一第三晶片,其中該第二晶片和該第三晶片設置在該上重佈線層之 該第二面上且與該上重佈線層電連接,該第二晶片與該第三晶片橫向相鄰,以及該第一晶片通過該上重佈線層與該第三晶片和該第二晶片電連接。
- 如請求項6的堆疊型封裝結構,其中該堆疊型封裝結構還包含:一下模封層,設置在該上重佈線層之該第二面上,配置為封裝該第二晶片和該第三晶片,以及其中該下模封層的材料不同於該上模封層的材料。
- 如請求項7的堆疊型封裝結構,其中該下模封層的該材料的熱膨脹係數大於該上模封層的該材料的熱膨脹係數。
- 如請求項7的堆疊型封裝結構,其中該堆疊型封裝結構還包含:一下重佈線層,設置在該下模封層遠離該上重佈線層的表面;至少一導電柱,電連接該上重佈線層和該下重佈線層;以及複數個焊球,設置在該下重佈線層遠離該下模封層的表面。
- 如請求項9的堆疊型封裝結構,其中該至少一導電柱在該下重佈線層的正投影與該第一晶片在該下重佈線層的正投影重疊,並且該第一晶片通過該上重佈線層與該至少一導電柱電連接。
- 一種堆疊型封裝結構之製造方法,包含:提供一載板;在該載板上設置一第一晶片;在該第一晶片和該載板上形成一模封層,其中該模封層配置為封裝該第一晶片;在該第一晶片和該模封層遠離該載板的表面形成一上重佈線層,其中該第一晶片與該上重佈線層電連接;移除該載板;以及 去除部分的模封層以形成一上模封層,其中該上模封層包含一凹槽,該凹槽相對於該上模封層遠離該上重佈線層的表面凹陷,以及該凹槽環繞地形成在該上模封層的外表面的周緣。
- 如請求項11的堆疊型封裝結構之製造方法,其中該上模封層遠離該上重佈線層的該表面至少包含第一階梯面和第二階梯面,且該第一階梯面為該凹槽之底面。
- 如請求項12的堆疊型封裝結構之製造方法,其中在形成該上模封層之後,該製造方法還包含:在該上模封層上設置一封蓋。
- 如請求項13的堆疊型封裝結構之製造方法,其中該上模封層還包含一開口,該開口用於曝露出該第一晶片的非主動面;以及該製造方法還包含:在該上模封層上設置一熱介面材料,其中該熱介面材料覆蓋該第一晶片的該非主動面,以及該熱介面材料設置在該封蓋和該上模封層之間。
- 如請求項11的堆疊型封裝結構之製造方法,其中在形成該上模封層之後,該製造方法還包含:在該上模封層的該表面形成一電磁干擾(EMI)屏蔽層。
- 如請求項11的堆疊型封裝結構之製造方法,其中形成該上重佈線層之後,該製造方法還包含:在該上重佈線層之遠離該第一晶片之一面設置一第二晶片和一第三晶片,其中該第二晶片和該第三晶片與該上重佈線層電連接,該第二晶片和該第三晶片橫向相鄰,以及該第一晶片通過該上重佈線層與該第三晶片和該第二晶片電連接。
- 如請求項16的堆疊型封裝結構之製造方法,其中該製造方法還包含:在該上重佈線層之遠離該第一晶片之一面形成一下模封層,其中該下模封層配置為封裝該第二晶片和該第三晶片,以及該下模封層的材料不同於該上模封層的材料。
- 如請求項17的堆疊型封裝結構之製造方法,其中該下模封層的該材料的熱膨脹係數大於該上模封層的該材料的熱膨脹係數。
- 如請求項17的堆疊型封裝結構之製造方法,其中在形成該下模封層之前,該製造方法還包含:在該上重佈線層之遠離該第一晶片之一面形成至少一導電柱;在形成該下模封層之後,該製造方法還包含:在該下模封層遠離該上重佈線層的表面形成一下重佈線層,其中該至少一導電柱電連接該上重佈線層和該下重佈線層;以及在該下重佈線層遠離該下模封層的表面形成複數個焊球。
- 如請求項19的堆疊型封裝結構之製造方法,其中該至少一導電柱在該下重佈線層的正投影與該第一晶片在該下重佈線層的正投影重疊,並且該第一晶片通過該上重佈線層與該至少一導電柱電連接。
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TWI478314B (zh) * | 2011-08-10 | 2015-03-21 | Taiwan Semiconductor Mfg Co Ltd | 半導體裝置與半導體裝置的形成方法 |
TW201727854A (zh) * | 2016-01-29 | 2017-08-01 | 台灣積體電路製造股份有限公司 | 半導體裝置及其製造方法 |
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TWI478314B (zh) * | 2011-08-10 | 2015-03-21 | Taiwan Semiconductor Mfg Co Ltd | 半導體裝置與半導體裝置的形成方法 |
TW201727854A (zh) * | 2016-01-29 | 2017-08-01 | 台灣積體電路製造股份有限公司 | 半導體裝置及其製造方法 |
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