CN110021572B - 堆叠式封装结构及其制造方法 - Google Patents

堆叠式封装结构及其制造方法 Download PDF

Info

Publication number
CN110021572B
CN110021572B CN201810886640.5A CN201810886640A CN110021572B CN 110021572 B CN110021572 B CN 110021572B CN 201810886640 A CN201810886640 A CN 201810886640A CN 110021572 B CN110021572 B CN 110021572B
Authority
CN
China
Prior art keywords
electrically connected
package
chip
packaging material
package structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201810886640.5A
Other languages
English (en)
Other versions
CN110021572A (zh
Inventor
陈明志
王啟安
许献文
蓝源富
徐宏欣
方立志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Powertech Technology Inc
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Publication of CN110021572A publication Critical patent/CN110021572A/zh
Application granted granted Critical
Publication of CN110021572B publication Critical patent/CN110021572B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8534—Bonding interfaces of the connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明为一种堆叠式封装结构及其制造方法，该堆叠式封装结构包含有数个堆叠于基座的晶片封装结构，各晶片封装结构具有成形于主动面的外导电元件，各外导电元件具有一切割端缘外露于晶片封装结构的一侧边，侧边导线贯穿成形于封装材并与晶片封装结构的切割端缘形成电连接，基座中设有内连接结构以使侧边导线与外接端子形成电连接，因此，简化了形成电连接的制程以提升堆叠式封装结构的制程的可靠度及UPH(每小时产出率)。

Description

堆叠式封装结构及其制造方法
技术领域
本发明关于一种半导体封装结构，尤指一种堆叠式封装结构及其制造方法。
背景技术
将数个晶片堆叠的技术已应用于不同的半导体封装结构中，以达成集成电路元件的微型化，现有技术中是采用打线接合(wire bonding)、或硅穿孔(through silicon via，TSV)结合微凸块的方法，以在堆叠的晶片与外接端子之间形成电连接，然而，现有技术具有其缺陷。
当晶片藉由打线接合的方式与外接端子连接时，接合导线之间必须保留间隙，以避免相邻的接合导线互相接触，则该些间隙不可避免地将增加现有技术的堆叠式封装结构的体积，因此，现有技术的具有接合导线的堆叠式封装结构较不易达成微型化。此外，由于无法同时成形所有的接合导线，故现有技术的打线接合制程须花费较多时间，因此，以打线接合制程所制的现有技术的堆叠式封装结构的每小时产出率(units per hour，UPH)相对较低。
当晶片以TSV及微凸块相互连接时，TSV增加了堆叠的高度及制程的复杂度，则使得封装结构厚度增加且降低制程良率。此外，微凸块之间的对位及定位精准度的要求很高，当现有技术的堆叠式封装结构的尺寸越来越大时，微凸块的位置偏移就随之增加，最终导致制程良率较差。
发明内容
有鉴于此，本发明针对现有技术中低可靠度及低UPH的问题加以改良。
为达到上述的发明目的，本发明所采用的技术手段为创作一种堆叠式封装结构，其中包括：
相互堆叠的数个晶片封装结构，各晶片封装结构包含有：
两侧边；
一晶片，其具有一主动面及一背面，该背面相对于该主动面；
一钝化层，其设置于晶片的主动面；以及
多个外导电元件，其设置于晶片的主动面并与晶片形成电连接，且各外导电元件具有一切割端缘，该切割端缘外露于该晶片封装结构的至少一
侧边上；
多个黏着层，其分别设置于相邻的晶片封装结构之间；
一第一封装材，其包覆所述晶片封装结构，且具有沿所述切割端缘设置的穿孔，所述穿孔形成在该第一封装材中；
一侧边导线，其设置于该第一封装材的穿孔中，并与所述晶片封装结构的切割端缘形成电连接；
一基座，其设置于所述相互堆叠的晶片封装结构中最底部的晶片封装结构的底面以及该第一封装材的底面，且其具有一内连接结构，该内连接结构与该侧边导线形成电连接；
一第三封装材，其覆盖该侧边导线；以及
一金属层，其设置于该第三封装材上且与该基座形成电连接。
本发明所采用的另一技术手段为，创作一种制造堆叠式封装结构的方法，其中包含以下步骤：
提供多个晶片封装结构，其中各晶片封装结构包含有：
一晶片，其具有一主动面及一背面，该背面相对于该主动面；
一钝化层，其设置于晶片的主动面；以及
多个外导电元件，其设置于晶片的主动面并与晶片形成电连接，且具有一切割端缘，该切割端缘外露于该晶片封装结构的至少一侧边上；
提供一基板，其中该基板包含有：
一内部电路；以及
多个上连接垫，其与内部电路及侧边导线形成电连接；
将所述晶片封装结构堆叠于该基板上，其中晶片封装结构的背面朝向与其相邻的晶片封装结构的主动面设置，多个黏着层分别设置于相邻的晶片封装结构之间，且该基板设置于所述相互堆叠的晶片封装结构中最底部的晶片封装结构的底面；
设置一第一封装材覆盖于该基板上的所述晶片封装结构上；
设置一穿孔于该第一封装材上以外露出所述切割端缘，所述穿孔形成在该第一封装材中；
设置一侧边导线于该穿孔中，以与所述切割端缘及上连接垫形成电连接；
执行单体化以形成数个堆叠式封装结构。
本发明所采用的另一技术手段为，创作一种制造堆叠式封装结构的方法，其中包含以下步骤：
提供多个晶片封装结构，其中各晶片封装结构包含有：
一晶片，其具有一主动面及一背面，该背面相对于该主动面；
一钝化层，其设置于晶片的主动面；以及
多个外导电元件，其设置于晶片的主动面并与晶片形成电连接，且具有一切割端缘，该切割端缘外露于该晶片封装结构的至少一侧边上；
将所述晶片封装结构堆叠于一载板上，其中晶片封装结构的背面朝向与其相邻的晶片封装结构的主动面设置，多个黏着层分别设置于相邻的晶片封装结构之间，且该载板设置于所述相互堆叠的晶片封装结构中最底部的晶片封装结构的底面；
设置一第一封装材覆盖于该载板上的所述晶片封装结构上；
设置一穿孔于该第一封装材上以外露出所述切割端缘，所述穿孔形成在该第一封装材中；
设置一侧边导线于该穿孔中，以与所述切割端缘形成电连接；
移除该载板以外露出该侧边导线；
设置一重布线层与侧边导线的端部形成电连接；
执行单体化以形成数个堆叠式封装结构。
本发明的优点在于，藉由侧边导线设置于封装材的穿孔中并与晶片封装结构的切割端缘形成电连接，且基座中设有内连接结构以使侧边导线与外接端子形成电连接，因而简化了用以形成电连接的制造方法，以提供堆叠式封装结构整体的可靠度以及制造堆叠式封装结构的UPH。
附图说明
图1A为本发明的堆叠式封装结构的晶片封装结构的第一实施例的上视剖面图。
图1B为图1A的晶片封装结构的前视剖面图。
图1C为图1A的晶片封装结构的侧视剖面图。
图2A为本发明的堆叠式封装结构的晶片封装结构的第二实施例的上视剖面图。
图2B为图2A的晶片封装结构的前视剖面图。
图2C为图2A的晶片封装结构的侧视剖面图。
图3A为本发明的堆叠式封装结构的晶片封装结构的第三实施例的上视剖面图。
图3B为图3A的晶片封装结构的前视剖面图。
图3C为图3A的晶片封装结构的侧视剖面图。
图4、6A、7A、8A、9A、10及11为本发明的制造方法的第一实施例的各制程中堆叠式封装结构的前视剖面图。
图5A、5B、7B、8B及9B为本发明的制造方法的第一实施例的各制程中堆叠式封装结构的上视图。
图12A为本发明堆叠式封装结构的第一实施例的前视剖面图。
图12B为本发明堆叠式封装结构的第二实施例的前视剖面图。
图13至15为本发明的制造方法的第二实施例的各制程中堆叠式封装结构的前视剖面图。
图16为本发明堆叠式封装结构的第三实施例的各制程中堆叠式封装结构的前视剖面图。
图17为本发明堆叠式封装结构的第四实施例的各制程中堆叠式封装结构的前视剖面图。
图18A、19A、20及21为本发明的制造方法的第四实施例的各制程中堆叠式封装结构的前视剖面图。
图18B及19B为本发明的制造方法的第四实施例的各制程中堆叠式封装结构的上视图。
图22为本发明的制造方法的第五实施例的制程中堆叠式封装结构的前视剖面图。
其中，附图标记：
10、10A、10B晶片封装结构 11、11A、11B晶片
111、111A、111B主动面 112背面
12、12A、12B钝化层 13外导电元件
130切割端缘 131焊垫
132外接导线 133A导电垫
134B接合垫 135B硅穿孔
100晶片堆 20黏着层
30第一封装材 40晶片封装体
50基板 51内部电路
52上连接垫 53下连接垫
50B载板 51B介电层
52B电路层 60第二封装材
61穿孔 62切割道开口
63C EMI开口 70侧边导线
71薄金属层 72光阻层
80、80C第三封装材 81外接端子
82、82C金属层 83C导电线
90、90C堆叠式封装结构 900B堆叠式封装结构半成品
901B背面
具体实施方式
以下配合图式及本发明的实施例，进一步阐述本发明为达成预定发明目的所采取的技术手段，其中图式已被简化以仅为了说明目的，而通过描述本发明的元件和组件之间的关系来说明本发明的结构或方法发明，因此，图中所示的元件不以实际数量、实际形状、实际尺寸以及实际比例呈现，尺寸或尺寸比例已被放大或简化，藉此提供更好的说明，已选择性地设计和配置实际数量、实际形状或实际尺寸比例，而详细的元件布局可能更复杂。
请参阅图12A，本发明的堆叠式封装结构90包含有数个晶片封装结构10，各晶片封装结构10包含有多个侧边、一晶片11、一钝化层(passivation layer)12及数个外导电元件13。晶片11具有一主动面111及一背面112，背面112与主动面111位于相反的面上，钝化层12设于主动面111上，外导电元件13设于主动面111上，各外导电元件13具有一切割端缘(cutedge)130，切割端缘130外露于晶片封装结构10的至少一侧边。在一实施例中，所述外导电元件13的切割端缘130外露于晶片封装结构10的多个侧边。以下所示为晶片封装结构10的各实施态样，但本发明不限于此。
如图1A至1C所示的实施例，晶片封装结构10包含有数个焊垫131、数个外接导线132、及一晶片介电层14，各焊垫131设于主动面111上且被钝化层12所包覆，各外接导线132于相对应的焊垫131上并延伸出钝化层12外，各外接导线132具有一端部外露于晶片封装结构10的其中一侧边上，晶片介电层14设于钝化层12及外接导线132上，其可为聚酰亚胺(polyimide)层。
如图2A至2C所示的实施例，晶片封装结构10A包含有数个导电垫133A，各导电垫133A设于晶片11A的主动面111A上且被钝化层12所包覆，各导电垫133A具有一端部外露于晶片封装结构10A的其中一侧边上。
如图3A至3C所示的实施例，晶片封装结构10B包含有数个接合垫134B及数个硅穿孔(through silicon vias，TSV)135B，各接合垫134B设于晶片11B的主动面111B上，且被钝化层12B所包覆，各硅穿孔135B设于晶片11B中并与相对应的接合垫134B耦合，各硅穿孔135B具有一端部外露于晶片封装结构10B的其中一侧边上。
综上所述，各外导电元件13的切割端缘130可为如图1A至1B所示的外接导线132、可为如图2A至2C所示的导电垫133A、或可为如图3A至3C所示的硅穿孔135B。如图1A至1B所示的外接导线132、如图2A至2C所示的导电垫133A、及如图3A至3C所示的硅穿孔135B的端部可外露于晶片封装结构10、10A、10B的至少一侧边。
图4至11所示为本发明的制造方法，其包含以下步骤：
请参阅图4，将数个晶片封装结构10相互堆叠后形成一晶片堆100，藉由数个黏着层20设置于相邻的晶片封装结构10之间，以将数个晶片封装结构10相互黏合，黏着层20设于晶片11的背面112，黏着层20可为晶粒贴附膜(die attach film，DAF)、环氧树脂(epoxy)、绝缘胶(insulation paste)或其类似物。各晶片封装结构10可通过精密对准程序相互对齐、或可不实施对准程序而不对齐。
请参阅图5A及5B所示，数个晶片堆100被第一封装材(encapsulant)30所包覆，切割被第一封装材30包覆后的晶片堆100以形成至少一晶片封装体40，第一封装材30可对晶片堆100提供封装保护，以避免短路或污染，且在切割过程中对结构提供稳定性。在一实施例中，当晶片堆100被切割后，所述晶片封装结构10的至少一侧边的切割端缘130外露且相互对齐。在一实施例中，当所述晶片封装结构10并未相互对齐而成形为晶片堆100时，切割所述晶片堆100时将使得所述晶片封装结构10相互对齐，如图4所示的所述晶片封装结构10之间的偏差值D1，可小于导电元件13的节距(pitch)的一半，以避免当晶片堆100切割后产生缺陷。
请参阅图6A所示，将所述晶片封装体40排列在一基板50上，所述晶片封装体40被一第二封装材60所覆盖，所述晶片封装体40可贴附于该基板50上，该载板50包含一内部电路51、数个上连接垫52、及数个下连接垫53。所述上连接垫52及下连接垫53分别成形于该基板50的相对侧边，且与该内部电路51形成电连接，所述晶片封装体40设置于该上连接垫52上，该第二封装材60可对晶片堆100提供封装保护，以避免短路或污染。
请参阅图7A及图7B所示，可在第二封装材60上成形有穿孔61以将位于至少一侧边的切割端缘130外露。在一实施例中，部份移除该第二封装材60以成形一穿孔61，该穿孔61设于所述切割端缘130的侧边，并使基板50的其中一上连接垫52露出。在一实施例中，数个穿孔61成形于该第二封装材60中，所述穿孔61分别设于所述切割端缘130的侧边，并使基板50的上连接垫52露出。在一实施例中，利用蚀刻制程将第二封装材60加以移除来成形所述穿孔61，所述蚀刻制程亦确保当所述切割端缘130外露后位于共平面上。在一实施例中，部份移除该第二封装材60以成形至少一切割道开口62，所述切割道开口62围绕设置于该晶片封装体40。
请参阅图8A至图9B所示，一侧边导线70设置于所述穿孔61中且与所述切割端缘130形成电连接。在一实施例中，数个侧边导线70分别设置所述穿孔61中，所述侧边导线70可通过溅镀(sputtering)、电镀(electroplating)等方法成形之。在另一实施例中，成形一薄金属层71于所述穿孔61及切割道开口62的壁面上，接着覆盖一光阻层72于所述切割道开口62上，再成形所述侧边导线70于所述穿孔61中(如图8A及8B所示)，所述薄金属层71及所述侧边导线70可通过溅镀(sputtering)、电镀(electroplating)等方法成形之，随后将光阻层72移除后，再进行一蚀刻制程以移除切割道开口62中的薄金属层71，由于所述侧边导线70设置于所述穿孔61中而形成较厚的金属导线，故在该蚀刻制程中，所述侧边导线70仅有其顶端的薄层会被连同该薄金属层71一并移除。
请参阅图10所示，所述第二封装材60、所述晶片封装体40及所述侧边导线70被一第三封装材80所覆盖。在一实施例中，所述切割道开口62亦被该第三封装材80所填充。
请参阅图11所示，数个外接端子81分别设置于该基板50的下连接垫53上，所述外接端子81可为多个锡球(solder ball)、多个焊锡(solder paste)、多个连接垫、或多个连接接脚。又，将所述晶片封装体40沿切割道开口62加以单体化(singulated)以形成多个堆叠式封装结构90。
藉由外露于晶片封装结构10的至少一侧边上的所述切割端缘130，所述晶片11之间的电连接，可通过设置于穿孔61中的侧边导线70、及侧边上的切割端缘130来加以达成，而晶片11与外接端子81之间的电连接，也可通过基板50、设置于穿孔61中的侧边导线70、及侧边上的切割端缘130来加以达成，因此，本发明简化了用以形成电连接的制造方法，以提高堆叠式封装结构90的可靠度以及制造堆叠式封装结构90的UPH。再者，基于所述晶片封装结构10可在如图5A及5B所示的切割流程后加以对准、且所述切割端缘130可在如图7A、7B所示的蚀刻流程后呈共平面，则在堆叠晶片封装结构10时所需的精准度也可相对要求较低，因此，本发明的制造方法更进一步简化以提升制造堆叠式封装结构90的UPH。
在如图12A所示的一实施例中，晶片堆叠封装结构90包含有层叠的数个晶片11，其被第三封装材80及第二封装材60所覆盖，层叠的晶片11可通过切割端缘130、侧边导线70、基板50的内部电路51及外接端子81与外部电路板形成电连接。
在如图12B所示堆叠式晶片封装结构90A的一实施例中，第三封装材80被一金属层82所覆盖，该金属层82接地或电连接一电压源以提供电磁干扰护罩(electromagneticinterference shield,EMI shield)，该金属层82可通过溅镀成形之。
本发明的另一实施例所示的制造堆叠式封装结构的方法包含以下步骤，但不限于此：
请参阅图13所示，所述晶片封装体40设置于一载板50B上且被该第二封装材60所覆盖，接着部份移除该第二封装材60以将侧边的切割端缘130加以外露，并成形穿孔61，接着将侧边导线70设于所述穿孔61中。在一实施例中，部份移除第二封装材60及成形侧边导线70的步骤如同图7A至9B中所示的步骤。
请参阅图14所示，该第二封装材60、所述晶片封装体40及所述侧边导线70被该第三封装材80所覆盖以形成一堆叠式封装结构半成品900B。在一实施例中，成形该第三封装材80的步骤如同图10中所示的步骤。接着将载板50B移除以露出堆叠式封装结构半成品900B的背面901B。在一实施例中，载板50B通过一研磨制程加以移除。侧边导线70的端部外露于堆叠式封装结构半成品900B的背面901B。
请参阅图15及图16所示，一重布线层(redistribution layer,RDL)及多个外接端子81成形于堆叠式封装结构半成品900B的背面901B上，该重布线层与所述侧边导线70及所述外接端子81形成电连接，该重布线层包含有介电层51B及电路层52B，电路层52B以导电金属成形之。在一实施例中，电路层52B可为多层金属堆叠，如钛(Titanium，Ti)/铜(Copper，Cu)/铜或钛/铜/铜/镍(Nickel，Ni)/金(Gold，Au)。在一实施例中，介电层51B可为一聚酰亚胺(polyimide,PI)层用来覆盖并隔绝电路层52B的多层金属堆叠。在一实施例中，该介电层51B包含有一第一介电层级一第二介电层分别成形于电路层52B之上及之下。在一实施例中，一凸块下金属(under bump metallurgy,UBM)层成形于该重布线层及该外接端子81之间并分别与之形成电连接，电路层52B的金属层的数量以及介电层51的数量并未受本实施例所揭露的限制，并可依照需求设计之。
接着进行单体化制程而成形出堆叠式封装结构90B。
在如图17所示的实施例中，第三封装材80被一金属层82所覆盖，该金属层82接地或电连接一电压源以提供电磁干扰护罩。
本发明的另一实施例所示的堆叠式封装结构90可包含有以下结构，但不限于此，且本发明的另一实施例所示的制造方法可包含相对应的步骤。
在如图6所示的步骤执行后，如图18A及图18B所示，部份移除该第二封装材60以成形一穿孔61、一切割道开口62、一EMI开口63C，该EMI开口63C可围绕该晶片封装体40。
请参阅图19A及图19B所示，一侧边导线70设置于该穿孔61中且与所述上连接垫52及切割端缘130形成电连接，一导电线83C设置于EMI开口63C中且与基板50的接地信号形成电连接。
请参阅图20所示，该晶片封装体40及该侧边导线70被该第三封装材80C所覆盖。
请参阅图21所示，该金属层82C设置于该第三封装材80C上且与导电线83C形成电连接。在一实施例中，该导电线83C及该金属层82C以溅镀方法成形之。
请参阅图22所示，多个外接端子81分别设置于基板50的下连接垫53上，接着沿切割道开口62将晶片封装体40单体化以形成多个堆叠式封装体90C。在一实施例中，具有该导电线83C及该金属层82C的该堆叠式封装体90C可具有至少一重布线层及至少一介电层来取代该基板。
以上所述仅是本发明的实施例而已，并非对本发明做任何形式上的限制，虽然本发明已以实施例揭露如上，然而并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明技术方案的范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (5)

1.一种堆叠式封装结构，其特征在于，包括：
相互堆叠的数个晶片封装结构，各晶片封装结构包含有：
两侧边；
一晶片，其具有一主动面及一背面，该背面相对于该主动面；
一钝化层，其设置于晶片的主动面；以及
多个外导电元件，其设置于晶片的主动面并与晶片形成电连接，且各外导电元件具有一切割端缘，该切割端缘外露于该晶片封装结构的至少一侧边上；
多个黏着层，其分别设置于相邻的晶片封装结构之间；
一第一封装材，其包覆所述晶片封装结构，且具有沿所述切割端缘设置的穿孔，所述穿孔形成在该第一封装材中；
一侧边导线，其设置于该第一封装材的穿孔中，并与所述晶片封装结构的切割端缘形成电连接；
一基座，其设置于所述晶片封装结构中最底部的晶片封装结构的底面以及该第一封装材的底面，且其具有一内连接结构，该内连接结构与该侧边导线形成电连接；
一第三封装材，其覆盖该侧边导线；以及
一金属层，其设置于该第三封装材上且与该基座形成电连接。
2.如权利要求1所述的堆叠式封装结构，其特征在于：
该基座包含一基板；
该内连接结构设置于该基板中且包含有：
一内部电路；
多个上连接垫，其与内部电路及侧边导线形成电连接；
多个下连接垫，其与内部电路形成电连接；以及
多个外接端子，其设置于基板的底部且与下连接垫形成电连接。
3.如权利要求1所述的堆叠式封装结构，其特征在于：
该内连接结构包含有一重布线层，该重布线层与侧边导线形成电连接；
多个外接端子，其设置于该重布线层的底部且与该重布线层形成电连接。
4.如权利要求1所述的堆叠式封装结构，其特征在于，其特征在于：该第三封装材包覆该第一封装材，该金属层包覆该第三封装材。
5.如权利要求1所述的堆叠式封装结构，其特征在于，进一步包含有：
一电磁干扰开口，其设置于该第一封装材且围绕所述晶片封装结构；
一导电线，其设置于该电磁干扰开口中，并与该金属层及该基座形成电连接。
CN201810886640.5A 2018-01-10 2018-08-06 堆叠式封装结构及其制造方法 Expired - Fee Related CN110021572B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/867,613 US20190214367A1 (en) 2018-01-10 2018-01-10 Stacked package and a manufacturing method of the same
US15/867,613 2018-01-10

Publications (2)

Publication Number Publication Date
CN110021572A CN110021572A (zh) 2019-07-16
CN110021572B true CN110021572B (zh) 2021-03-23

Family

ID=67140190

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810886640.5A Expired - Fee Related CN110021572B (zh) 2018-01-10 2018-08-06 堆叠式封装结构及其制造方法

Country Status (3)

Country Link
US (1) US20190214367A1 (zh)
CN (1) CN110021572B (zh)
TW (1) TWI671876B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210120221A (ko) 2020-03-26 2021-10-07 삼성전자주식회사 반도체 스택 및 그 제조 방법
US11935824B2 (en) * 2021-09-29 2024-03-19 Microchip Technology Incorporated Integrated circuit package module including a bonding system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106024766A (zh) * 2016-07-18 2016-10-12 华进半导体封装先导技术研发中心有限公司 高堆叠晶圆系统级封装结构及制备方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100524736C (zh) * 2005-11-11 2009-08-05 南茂科技股份有限公司 堆叠型晶片封装结构
US8546189B2 (en) * 2008-09-22 2013-10-01 Stats Chippac, Ltd. Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection
US8822281B2 (en) * 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US9318411B2 (en) * 2013-11-13 2016-04-19 Brodge Semiconductor Corporation Semiconductor package with package-on-package stacking capability and method of manufacturing the same
US9601467B1 (en) * 2015-09-03 2017-03-21 Invensas Corporation Microelectronic package with horizontal and vertical interconnections
US9659878B2 (en) * 2015-10-20 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level shielding in multi-stacked fan out packages and methods of forming same
TW201724423A (zh) * 2015-12-23 2017-07-01 力成科技股份有限公司 扇出型封裝堆疊構造與方法
TWI567897B (zh) * 2016-06-02 2017-01-21 力成科技股份有限公司 薄型扇出式多晶片堆疊封裝構造與製造方法
CN106328611B (zh) * 2016-10-21 2019-03-12 苏州日月新半导体有限公司 半导体封装构造及其制造方法
CN106783805A (zh) * 2017-03-13 2017-05-31 中国科学院微电子研究所 射频多芯片封装及屏蔽电路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106024766A (zh) * 2016-07-18 2016-10-12 华进半导体封装先导技术研发中心有限公司 高堆叠晶圆系统级封装结构及制备方法

Also Published As

Publication number Publication date
TW201931545A (zh) 2019-08-01
US20190214367A1 (en) 2019-07-11
TWI671876B (zh) 2019-09-11
CN110021572A (zh) 2019-07-16

Similar Documents

Publication Publication Date Title
KR102425720B1 (ko) 반도체 패키지 및 그 제조 방법
KR102586078B1 (ko) 반도체 디바이스 및 그 제조 방법
US20240014151A1 (en) Package structure and manufacturing method thereof
KR102660697B1 (ko) 반도체 장치 및 그 제조 방법
CN107180814B (zh) 电子装置
US9761568B2 (en) Thin fan-out multi-chip stacked packages and the method for manufacturing the same
US9899307B2 (en) Fan-out chip package with dummy pattern and its fabricating method
KR20240058061A (ko) 반도체 디바이스 및 그 제조 방법
US20170186711A1 (en) Structure and method of fan-out stacked packages
US9837384B2 (en) Fan-out multi-chip package with plurality of chips stacked in staggered stack arrangement
TWI662677B (zh) 堆疊式封裝結構及其製造方法
US20230361091A1 (en) Electronic package and manufacturing method thereof
KR101982905B1 (ko) 반도체 패키지 및 그 제조 방법
CN111477553B (zh) 隔离封装结构及其制造方法
US20080258306A1 (en) Semiconductor Device and Method for Fabricating the Same
CN110021572B (zh) 堆叠式封装结构及其制造方法
CN115513148A (zh) 半导体封装及其形成方法
US9190370B2 (en) Semiconductor device utilizing redistribution layers to couple stacked die
US20240063137A1 (en) Semiconductor Device and Method for Partial EMI Shielding
KR20220110673A (ko) 반도체 패키지 및 그 제조 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20210323

CF01 Termination of patent right due to non-payment of annual fee