TWI662677B - 堆疊式封裝結構及其製造方法 - Google Patents

堆疊式封裝結構及其製造方法 Download PDF

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TWI662677B
TWI662677B TW107121550A TW107121550A TWI662677B TW I662677 B TWI662677 B TW I662677B TW 107121550 A TW107121550 A TW 107121550A TW 107121550 A TW107121550 A TW 107121550A TW I662677 B TWI662677 B TW I662677B
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layer
cutting edge
dielectric layer
chip
package structure
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TW107121550A
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TW201931557A (zh
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陳明志
王啟安
許獻文
藍源富
徐宏欣
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力成科技股份有限公司
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Abstract

本發明為一種堆疊式封裝結構及其製造方法，該堆疊式封裝結構包含有數個以主動面相互堆疊的晶片封裝結構、一介電層、一重佈線層及數個外接端子，各晶片封裝結構具有成形於主動面的外導電元件，各外導電元件具有一切割端緣外露於晶片封裝結構之至少一側邊，介電層、重佈線層及外接端子依序成形於外露有切割端緣之側邊上，以使切割端緣、重佈線層及外接端子間形成電連接，因此，簡化了形成電連接的製程以提昇堆疊式封裝結構之製程的可靠度及UPH（每小時產出率）。

Description

堆疊式封裝結構及其製造方法
本發明係關於一種半導體封裝結構，尤指一種堆疊式封裝結構及其製造方法。
將數個晶片堆疊之技術已應用於不同的半導體封裝結構中，以達成積體電路元件的微型化，現有技術中係採用打線接合(wire bonding)、或矽穿孔(through silicon via，TSV)結合微凸塊的方法，以在堆疊的晶片與外接端子之間形成電連接，然而，現有技術係具有其缺陷。
當晶片藉由打線接合的方式與外接端子連接時，接合導線之間必須保留間隙，以避免相鄰的接合導線互相接觸，則該些間隙不可避免地將增加現有技術之堆疊式封裝結構的體積，因此，現有技術之具有接合導線的堆疊式封裝結構較不易達成微型化。此外，由於無法同時成形所有的接合導線，故現有技術之打線接合製程須花費較多時間，因此，以打線接合製程所製的現有技術之堆疊式封裝結構的每小時產出率(units per hour，UPH)相對較低。
當晶片係以TSV及微凸塊相互連接時，TSV增加了堆疊的高度及製程的複雜度，則使得封裝結構厚度增加且降低製程良率。此外，微凸塊之間的對位及定位精準度的要求很高，當現有技術之堆疊式封裝結構的尺寸越來越大時，微凸塊的位置偏移就隨之增加，最終導致製程良率較差。
有鑑於此，本發明係針對現有技術中低可靠度及低UPH的問題加以改良。
為達到上述之發明目的，本發明所採用的技術手段為創作一種堆疊式封裝結構，其中包括：相互堆疊的數個晶片封裝結構，各晶片封裝結構包含有：兩側邊；一晶片，其具有一主動面及一背面，該背面係相對於該主動面，其中一晶片封裝結構之背面係朝向與相鄰之晶片封裝結構的主動面設置；一鈍化層，其設置於晶片的主動面；一外導電元件，其設置於晶片的主動面，且具有一切割端緣，該切割端緣外露於至少一所述側邊上；一封裝材，其包覆所述晶片封裝結構，且具有開口以將所述切割端緣外露；至少一介電層，其設置於所述切割端緣上、及對應所述切割端緣之所述晶片封裝結構之側邊、與對應所述切割端緣之該封裝材之側邊，且所述介電層具有數個缺口以將所述切割端緣外露；至少一重佈線層，其設置於所述介電層上，且與所述切割端緣形成電連接。
本發明所採用的另一技術手段為，創作一種製造堆疊式封裝結構的方法，其中包含以下步驟：堆疊數個晶片封裝結構於一載板上，其中各晶片封裝結構包含有：兩側邊；一晶片，其具有一主動面及一背面，該背面係相對於該主動面；一外導電 元件，其設置於晶片的主動面，且具有一切割端緣，該切割端緣外露於至少一所述側邊上，其中一晶片封裝結構之背面係朝向與相鄰之晶片封裝結構的主動面設置；將一封裝材覆蓋於該載板上的所述晶片封裝結構上；外露出至少一側邊上的所述切割端緣；設置至少一介電層於所述至少一側邊上，且外露出所述切割端緣；設置至少一重佈線層於所述介電層上，其中所述重佈線層與所述切割端緣形成電連接；執行單體化以形成數個堆疊式封裝結構。
本發明的優點在於，藉由將介電層、重佈線層設置於晶片封裝結構上外露於至少一側邊的切割端緣上，來快速的使重佈線層與切割端緣之間形成電連接，進而構成多個晶片、重佈線層、外接端子之間的電連接，因而簡化了用以形成電連接的製造方法，以提供堆疊式封裝結構整體的可靠度以及製造堆疊式封裝結構的UPH。
10、10A、10B、10C‧‧‧晶片封裝結構
11、11A、11B‧‧‧晶片
111、111A、111B‧‧‧主動面
112‧‧‧背面
12、12A、12B‧‧‧鈍化層
13‧‧‧外導電元件
130、130C‧‧‧切割端緣
131‧‧‧焊墊
132‧‧‧外接導線
133A‧‧‧導電墊
134B‧‧‧接合墊
135B‧‧‧矽穿孔
14‧‧‧晶片介電層
100‧‧‧晶片堆
20‧‧‧黏著層
30‧‧‧第一封裝材
40‧‧‧晶片封裝體
50‧‧‧載板
51‧‧‧黏著膜
60‧‧‧第二封裝材
70‧‧‧第一介電層
71‧‧‧第二介電層
80‧‧‧重佈線層
81‧‧‧UBM層
82‧‧‧外接端子
90、90A、90B、90D‧‧‧堆疊式封裝結構
圖1A為本發明之堆疊式封裝結構的晶片封裝結構之第一實施例的上視剖面圖。
圖1B為圖1A之晶片封裝結構的前視剖面圖。
圖1C為圖1A之晶片封裝結構的側視剖面圖。
圖2A為本發明之堆疊式封裝結構的晶片封裝結構之第二實施例的上視剖面圖。
圖2B為圖2A之晶片封裝結構的前視剖面圖。
圖2C為圖2A之晶片封裝結構的側視剖面圖。
圖3A為本發明之堆疊式封裝結構的晶片封裝結構之第三實施例的上視剖面圖。
圖3B為圖3A之晶片封裝結構的前視剖面圖。
圖3C為圖3A之晶片封裝結構的側視剖面圖。
圖4為本發明之堆疊式封裝結構的晶片封裝結構之第四實施例的上視剖面圖。
圖5A、6、7、8A、9A、10A、11A、12A、13A及14A為本發明之製造方法的第一實施例之各製程中堆疊式封裝結構的立體圖。
圖5B、8B、9B、10B、11B、12B、13B及14B為本發明之製造方法的第一實施例之各製程中堆疊式封裝結構的前視剖面圖。
圖15A為本發明堆疊式封裝結構之第一實施例的前視剖面圖。
圖15B為本發明堆疊式封裝結構之第二實施例的前視剖面圖。
圖15C為本發明堆疊式封裝結構之第三實施例的前視剖面圖。
圖16A及17A為本發明之製造方法的第二實施例之各製程中堆疊式封裝結構的立體圖。
圖16B及17B為本發明之製造方法的第二實施例之各製程中堆疊式封裝結構的前視剖面圖。
圖18至21為為本發明之製造方法的第三實施例之各製程中堆疊式封裝結構的前視剖面圖。
以下配合圖式及本發明之實施例，進一步闡述本發明為達成預定發明目的所採取的技術手段，其中圖式已被簡化以僅為了說明目的，而通過 描述本發明的元件和組件之間的關係來說明本發明的結構或方法發明，因此，圖中所示的元件不以實際數量、實際形狀、實際尺寸以及實際比例呈現，尺寸或尺寸比例已被放大或簡化，藉此提供更好的說明，已選擇性地設計和配置實際數量、實際形狀或實際尺寸比例，而詳細的元件佈局可能更複雜。
請參閱圖15A，本發明之堆疊式封裝結構90包含有數個晶片封裝結構10，各晶片封裝結構10包含有至少兩個側邊、一晶片11、一鈍化層(passivation layer)12及數個外導電元件13。晶片11具有一主動面111及一背面112，背面112係與主動面111位於相反的面上，鈍化層12設於主動面111上，外導電元件13設於主動面111上，各外導電元件13具有一切割端緣(cut edge)130，切割端緣130外露於晶片封裝結構10之至少一側邊。以下所示為晶片封裝結構10的各實施態樣，但本發明不限於此。
如圖1A至1C所示之實施例，晶片封裝結構10包含有數個焊墊131、數個外接導線132、及一晶片介電層14，各焊墊131設於主動面111上且被鈍化層12所包覆，各外接導線132於相對應的焊墊131上並延伸出鈍化層12外，各外接導線132具有一端部外露於晶片封裝結構10之其中一側邊上，晶片介電層14設於鈍化層12及外接導線132上，其可為聚酰亞胺(polyimide)層。
如圖2A至2C所示之實施例，晶片封裝結構10A包含有數個導電墊133A，各導電墊133A設於晶片11A之主動面111A上且被鈍化層12所包覆，各導電墊133A具有一端部外露於晶片封裝結構10A之其中一側邊上。
如圖3A至3C所示之實施例，晶片封裝結構10B包含有數個接合墊134B及數個矽穿孔(through silicon vias，TSV)135B，各接合墊134B設於晶片11B之主動面111B上，且被鈍化層12B所包覆，各矽穿孔135B設於晶片11B中並與相對應的接合墊134B耦合，各矽穿孔135B具有一端部外露於晶片封裝結構10B之其中一側邊上。
綜上所述，各外導電元件13的切割端緣130可為如圖1A至1B所示之外接導線132、可為如圖2A至2C所示之導電墊133A、或可為如圖3A至3C所示之矽穿孔135B。
圖4所示之實施例為外導電元件之切割端緣130C相對外露於晶片封裝結構10C的兩側邊。
圖5A至14B所示為本發明之製造方法，其包含以下步驟：
請參閱圖5A及5B，將數個晶片封裝結構10相互堆疊後形成一晶片堆100，藉由數個黏著層20設至於相鄰的晶片封裝結構10之間，以將數個晶片封裝結構10相互黏合，黏著層20係設於晶片11之背面112，黏著層20可為晶粒貼附膜(die attach film，DAF)、環氧樹脂(epoxy)、絕緣膠(insulation paste)或其類似物。各晶片封裝結構10可透過精密對準程序相互對齊、或可不實施對準程序而不對齊。
請參閱圖6所示，數個晶片堆100被第一封裝材(encapsulant)30所包覆，第一封裝材30可對晶片堆100提供封裝保護，以避免短路或污染。
請參閱圖6及7，切割所述晶片堆100以形成數個晶片封裝體40。在一實施例中，當所述晶片封裝結構10並未相互對齊而成形為晶片堆100時，切割所述晶片堆100時將使得所述晶片封裝結構10相互對齊。在另一實施例中，當切割所述晶片堆100後，所述晶片封裝結構10之至少一側邊的切割端緣130外露且相互對齊。
請參閱圖8A及8B所示，將所述晶片封裝體40排列在載板50上，所述晶片封裝體40可透過一黏著膜51貼附於該載板50上，所述黏著膜51設置於晶片封裝體40及該載板50之間。各晶片封裝結構10之其中一側邊朝向該載板50，而外導電元件13之切割端緣130則背離該載板50設置。在一實施例中，所 述晶片封裝體40於載板50上排列為一矩陣。在一實施例中，該載板50可為玻璃載板、或為晶圓形式或面板形式的半導體載板。
請參閱圖9A及9B所示，所述晶片封裝體40被第二封裝材60所覆蓋，該第二封裝材60可對晶片封裝體40提供封裝保護，以避免短路或污染。
請參閱圖10A及10B所示，移除該第二封裝材60之部份以將所述外導電元件13之切割端緣130外露。在一實施例中，利用蝕刻、拋光或研磨等製程將第二封裝材60加以移除，所述蝕刻、拋光或研磨等製程亦確保當所述切割端緣130外露後係位於共平面上。在一些實施例中，所述切割端緣130在先前的切割步驟中並未外露，而係在進行圖10A及圖10B所示之步驟後才外露於第一封裝材30及第二封裝材60之外。
請參閱圖11A及11B所示，設置一第一介電層70於所述晶片封裝結構10之具有外露的切割端緣之側邊上，且被加以蝕刻以將所述切割端緣130外露。在一實施例中，藉由光微影方法來蝕刻該第一介電層70，以將所述切割端緣130外露，該第一介電層70可為一聚醯亞胺(polyimide，PI)層。
請參閱圖12A及12B所示，設置一重佈線層(redistribution layer，RDL)80於該第一介電層70上，且該重佈線層80與所述切割端緣130形成電連接，該重佈線層80可為導電金屬所成形之電路。在一實施例中，該重佈線層80可為多層金屬堆疊，如鈦(Titanium，Ti)/銅(Copper，Cu)/銅或鈦/銅/銅/鎳(Nickel，Ni)/金(Gold，Au)。
請參閱圖13A及13B所示，設置一第二介電層71於該重佈線層80上，接著設置一凸塊下金屬(under bump metallurgy，UBM)層81於該第二介電層71上，且該UBM層81與該重佈線層80形成電連接。在一實施例中，藉由光微影方法來蝕刻該第二介電層71，以將該重佈線層80外露，該第二介電層71可為一聚醯亞胺層。在一實施例中，該UBM層81係藉由濺鍍方式加以成形。如重 佈線層80之導電層以及介電層70、71的數量可視需求而定，並不限於在此所述之實施例。
請參閱圖14A及14B所示，設置數個外接端子82於第二介電層71上，且所述外接端子82與UBM層81形成電連接，接著將載板50及黏著膜51移除，將所述晶片封裝體40單體化(singulated)以形成數個堆疊式封裝結構90，外接端子82可為多個錫球(solder ball)、多個銲錫(solder paste)、多個連接墊、或多個連接接腳。
藉由外露於晶片封裝結構10之至少一側邊上的所述切割端緣130，所述晶片11之間的電連接、以及所述晶片11與外接端子82之間的電連接，係可透過設置於所述切割端緣130上之重佈線層80來達成，因此，本發明係簡化了用以形成電連接的製造方法，以提高堆疊式封裝結構90的可靠度以及製造堆疊式封裝結構90的UPH。再者，基於所述晶片封裝結構10可在如圖7所示之切割流程後加以對準、且所述切割端緣130可在如圖10A、10B所示之蝕刻、拋光、或研磨等流程後呈共平面，則在堆疊晶片封裝結構10時所需的精準度也可相對要求較低，因此，本發明之製造方法係更進一步簡化以提昇製造堆疊式封裝結構90的UPH。
本發明之另一實施例所示之堆疊式封裝結構90可包含有以下結構，但不限於此，且本發明之另一實施例所示之製造方法可包含相對應的步驟。
如圖15A所示之實施例，堆疊式封裝結構90包含第一介電層70、重佈線層80、第二介電層71、UBM層81及外接端子82，所述晶片11可透過所述切割端緣130、重佈線層80、UBM層81及外接端子82所構成的電性連接，來與外部印刷電路板形成電連接。
如圖15B所示之實施例，堆疊式封裝結構90A包含第一介電層70、重佈線層80及外接端子82，所述晶片11可透過所述切割端緣130、重佈線層80及外接端子82所構成的電性連接，來與外部印刷電路板形成電連接。
如圖15C所示之實施例，堆疊式封裝結構90B包含第一介電層70、重佈線層80、第二介電層71及外接端子82，所述晶片11可透過所述切割端緣130、重佈線層80及外接端子82所構成的電性連接，來與外部印刷電路板形成電連接。
本發明之另一實施例所示之製造堆疊式封裝結構的方法包含以下步驟，但不限於此：
在執行完如圖5A至圖7所示之步驟後，請參閱圖16A及16B所示，在排列晶片封裝體40於載板50上時，將位於所述晶片封裝結構10之其中一側邊的所述外導電元件13之切割端緣130設置於面向載板50。
請參閱圖17A及17B，在設置第二封裝材60後，移除該載板50及該黏著膜51以使位於所述晶片封裝結構10之其中一側邊的所述切割端緣130外露，後續成形重佈線層、UBM層、錫球等步驟係如圖11A至14B所示。
本發明之又一實施例所示之製造堆疊式封裝結構的方法包含以下步驟，但不限於此：
如圖4所示，晶片封裝結構10C包含有外露於第一側邊及第二側邊的切割端緣130C，在執行完如圖5A至圖7所示之步驟後，請參閱圖18所示，在排列晶片封裝體40於載板50上時，將位於所述晶片封裝結構10C之第一側邊的切割端緣130C設置於背向載板50，此時位於所述晶片封裝結構10C之第二側邊的切割端緣130C則相對面向載板50。
請參閱圖19所示，設置一第一介電層70、一重佈線層80、一第二介電層71及一UBM層81於該第一側邊上，以形成位於第一側邊之所述切割端緣130、重佈線層80、UBM層81之間的電性連接。
請參閱圖20所示，移除該載板50及黏著膜51後，再設置一第一介電層70、一重佈線層80、一第二介電層71及一UBM層81於該第二側邊上，以形成位於第二側邊之所述切割端緣130、重佈線層80、UBM層81之間的電性連接。
在如圖21所示之某些實施例中，數個外接端子82分別設置於位在第一側邊及第二側邊之第二介電層71上，並與位在第一側邊及第二側邊之UBM層81形成電連接，接著將所述晶片封裝體40單體化以形成數個堆疊式晶片封裝結構90D。
藉由所述堆疊式晶片封裝結構90D具有外接端子82設置在雙邊，則與其他半導體結構、被動元件等堆疊設置將會更加簡單。
以上所述僅是本發明的實施例而已，並非對本發明做任何形式上的限制，雖然本發明已以實施例揭露如上，然而並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明技術方案的範圍內，當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。

Claims (10)

  1. 一種堆疊式封裝結構，其中包括：相互堆疊的數個晶片封裝結構，各晶片封裝結構包含有：兩側邊；一晶片，其具有一主動面及一背面，該背面係相對於該主動面，其中一晶片封裝結構之背面係朝向與相鄰之晶片封裝結構的主動面設置；一鈍化層，其設置於晶片的主動面；一外導電元件，其設置於晶片的主動面，且具有一切割端緣，該切割端緣外露於至少一所述側邊上；一封裝材，其包覆所述晶片封裝結構，且具有開口以將所述切割端緣外露；至少一介電層，其設置於所述切割端緣上、及對應所述切割端緣之所述晶片封裝結構之側邊、與對應所述切割端緣之該封裝材之側邊，且所述介電層具有數個缺口以將所述切割端緣外露；至少一重佈線層，其設置於所述介電層上，且與所述切割端緣形成電連接。
  2. 如請求項1所述之堆疊式封裝結構，其中各晶片封裝結構之切割端緣係分別設置於兩側邊；所述介電層之數量為二，且所述介電層分別設置於位在兩側邊的所述切割端緣上；所述重佈線層之數量為二，且所述重佈線層分別設置於位在兩側邊的所述介電層上，且分別與位在兩側邊的所述切割端緣形成電連接。
  3. 如請求項2所述之堆疊式封裝結構，其進一步包含有：兩附加介電層，其分別設置於所述重佈線層上，且其分別具有數個缺口以將位於兩側邊的所述切割端緣外露；兩凸塊下金屬層，其分別設置於所述附加介電層上且分別於所述重佈線層形成電連接；數個外接端子，其設置於所述凸塊下金屬層上且與所述凸塊下金屬層形成電連接。
  4. 如請求項1所述之堆疊式封裝結構，其中所述介電層包含有一第一介電層及一第二介電層，該第一介電層設置於所述切割端緣上，該第二介電層設置於所述重佈線層與外接端子之間。
  5. 如請求項1所述之堆疊式封裝結構，其進一步包含至少一凸塊下金屬層，其中所述介電層包含一第一介電層及一第二介電層；該第一介電層設置於所述切割端緣上；所述重佈線層設置於該第一介電層上；該第二介電層設置於所述重佈線層上；所述凸塊下金屬層設置於該第二介電層上，且與所述重佈線層形成電連接；所述外接端子設置於所述凸塊下金屬層上，且與所述凸塊下金屬層形成電連接。
  6. 一種製造堆疊式封裝結構的方法，其中包含以下步驟：堆疊數個晶片封裝結構於一載板上，其中各晶片封裝結構包含有：兩側邊；一晶片，其具有一主動面及一背面，該背面係相對於該主動面；一外導電元件，其設置於晶片的主動面，且具有一切割端緣，該切割端緣外露於至少一所述側邊上，其中一晶片封裝結構之背面係朝向與相鄰之晶片封裝結構的主動面設置；將一封裝材覆蓋於該載板上的所述晶片封裝結構上；外露出至少一側邊上的所述切割端緣；設置至少一介電層於所述至少一側邊上，且外露出所述切割端緣；設置至少一重佈線層於所述介電層上，其中所述重佈線層與所述切割端緣形成電連接；執行單體化以形成數個堆疊式封裝結構。
  7. 如請求項6所述之製造堆疊式封裝結構的方法，其中：所述晶片封裝結構之側邊分別為一第一側邊及一第二側邊；各晶片封裝結構之切割端緣外露於該第一側邊上；在堆疊所述晶片封裝結構於該載板上之步驟中，所述晶片封裝結構之第一側邊朝向該載板；在外露所述切割端緣之步驟中，移除該載板以將所述切割端緣外露。
  8. 如請求項6所述之製造堆疊式封裝結構的方法，其中：所述晶片封裝結構之側邊分別為一第一側邊及一第二側邊；各晶片封裝結構之切割端緣外露於該第一側邊及該第二側邊上；在堆疊所述晶片封裝結構於該載板上之步驟中，所述晶片封裝結構之第二側邊朝向該載板；在外露所述切割端緣之步驟中，部份移除所述封裝材以將位於所述第一側邊的所述切割端緣加以外露；在設置至少一介電層之步驟中，所述介電層設置在位於所述第一側邊的所述切割端緣上；在設置至少一重佈線層的步驟中，所述重佈線層與位於所述第一側邊的所述切割端緣形成電連接；該製造堆疊式封裝結構的方法進一步包含以下步驟：在設置至少一重佈線層的步驟之後，移除該載板；設置至少一附加介電層於所述第二側邊上並使所述第二側邊的所述切割端緣外露；設置至少一附加重佈線層於所述附加介電層上，其中所述附加重佈線層與所述第二側邊的所述切割端緣形成電連接；設置數個外接端子於所述重佈線層及所述附加重佈線層上，所述外接端子分別與所述重佈線層及所述附加重佈線層形成電連接。
  9. 如請求項6所述之製造堆疊式封裝結構的方法，其進一步包含以下步驟：設置至少一輔助介電層於所述重佈線層上；設置數個外接端子與所述輔助介電層上。
  10. 如請求項6所述之製造堆疊式封裝結構的方法，其進一步包含以下步驟：在設置所述重佈線層後，設置至少一輔助介電層於所述重佈線層上；設置至少一凸塊下金屬層於所述輔助介電層上，其中所述凸塊下金屬層與所述重佈線層形成電連接；設置數個外接端子於所述凸塊下金屬層上，其中所述外接端子與所述凸塊下金屬層形成電連接。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11024603B2 (en) 2018-01-10 2021-06-01 Powertech Technology Inc. Manufacturing method and a related stackable chip package
CN112151514A (zh) * 2019-06-28 2020-12-29 西部数据技术公司 包括垂直堆叠半导体管芯的半导体器件
US11296051B2 (en) * 2019-08-22 2022-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and forming method thereof
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201027692A (en) * 2009-01-06 2010-07-16 Chipmos Technologies Inc Semiconductor package structure and method for manufacturing the same
TW201801265A (zh) * 2016-03-25 2018-01-01 三星電機股份有限公司 扇出型半導體封裝
TW201801279A (zh) * 2016-06-24 2018-01-01 台灣積體電路製造股份有限公司 積體扇出型封裝體

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5648684A (en) * 1995-07-26 1997-07-15 International Business Machines Corporation Endcap chip with conductive, monolithic L-connect for multichip stack
KR100914977B1 (ko) * 2007-06-18 2009-09-02 주식회사 하이닉스반도체 스택 패키지의 제조 방법
US8847376B2 (en) * 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
KR20150141440A (ko) * 2014-06-10 2015-12-18 삼성전자주식회사 반도체 칩, 이를 갖는 반도체 패키지 및 반도체 패키지의 제조 방법
US10283492B2 (en) 2015-06-23 2019-05-07 Invensas Corporation Laminated interposers and packages with embedded trace interconnects
US11803918B2 (en) * 2015-07-07 2023-10-31 Oracle International Corporation System and method for identifying experts on arbitrary topics in an enterprise social network
JP6321092B2 (ja) * 2015-07-15 2018-05-09 エルジー エレクトロニクス インコーポレイティド 太陽電池及び太陽電池モジュール
US9490195B1 (en) * 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9659878B2 (en) * 2015-10-20 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level shielding in multi-stacked fan out packages and methods of forming same
TW201724423A (zh) * 2015-12-23 2017-07-01 力成科技股份有限公司 扇出型封裝堆疊構造與方法
US10217728B2 (en) * 2016-11-22 2019-02-26 Advanced Semiconductor Engineering, Inc. Semiconductor package and semiconductor process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201027692A (en) * 2009-01-06 2010-07-16 Chipmos Technologies Inc Semiconductor package structure and method for manufacturing the same
TW201801265A (zh) * 2016-03-25 2018-01-01 三星電機股份有限公司 扇出型半導體封裝
TW201801279A (zh) * 2016-06-24 2018-01-01 台灣積體電路製造股份有限公司 積體扇出型封裝體

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