TW201931545A - 堆疊式封裝結構及其製造方法 - Google Patents

堆疊式封裝結構及其製造方法 Download PDF

Info

Publication number
TW201931545A
TW201931545A TW107126658A TW107126658A TW201931545A TW 201931545 A TW201931545 A TW 201931545A TW 107126658 A TW107126658 A TW 107126658A TW 107126658 A TW107126658 A TW 107126658A TW 201931545 A TW201931545 A TW 201931545A
Authority
TW
Taiwan
Prior art keywords
chip
disposed
stacked
chip packaging
packaging structure
Prior art date
Application number
TW107126658A
Other languages
English (en)
Other versions
TWI671876B (zh
Inventor
陳明志
徐宏欣
藍源富
王啟安
許獻文
方立志
Original Assignee
力成科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力成科技股份有限公司 filed Critical 力成科技股份有限公司
Publication of TW201931545A publication Critical patent/TW201931545A/zh
Application granted granted Critical
Publication of TWI671876B publication Critical patent/TWI671876B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8534—Bonding interfaces of the connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本發明為一種堆疊式封裝結構及其製造方法，該堆疊式封裝結構包含有數個堆疊於基座的晶片封裝結構，各晶片封裝結構具有成形於主動面的外導電元件，各外導電元件具有一切割端緣外露於晶片封裝結構之一側邊，側邊導線貫穿成形於封裝材並與晶片封裝結構之切割端緣形成電連接，基座中設有內連接結構以使側邊導線與外接端子形成電連接，因此，簡化了形成電連接的製程以提昇堆疊式封裝結構之製程的可靠度及UPH（每小時產出率）。

Description

堆疊式封裝結構及其製造方法
本發明係關於一種半導體封裝結構，尤指一種堆疊式封裝結構及其製造方法。
將數個晶片堆疊之技術已應用於不同的半導體封裝結構中，以達成積體電路元件的微型化，現有技術中係採用打線接合（wire bonding）、或矽穿孔（through silicon via，TSV）結合微凸塊的方法，以在堆疊的晶片與外接端子之間形成電連接，然而，現有技術係具有其缺陷。
當晶片藉由打線接合的方式與外接端子連接時，接合導線之間必須保留間隙，以避免相鄰的接合導線互相接觸，則該些間隙不可避免地將增加現有技術之堆疊式封裝結構的體積，因此，現有技術之具有接合導線的堆疊式封裝結構較不易達成微型化。此外，由於無法同時成形所有的接合導線，故現有技術之打線接合製程須花費較多時間，因此，以打線接合製程所製的現有技術之堆疊式封裝結構的每小時產出率（units per hour，UPH）相對較低。
當晶片係以TSV及微凸塊相互連接時，TSV增加了堆疊的高度及製程的複雜度，則使得封裝結構厚度增加且降低製程良率。此外，微凸塊之間的對位及定位精準度的要求很高，當現有技術之堆疊式封裝結構的尺寸越來越大時，微凸塊的位置偏移就隨之增加，最終導致製程良率較差。
有鑑於此，本發明係針對現有技術中低可靠度及低UPH的問題加以改良。
為達到上述之發明目的，本發明所採用的技術手段為創作一種堆疊式封裝結構，其中包括： 相互堆疊的數個晶片封裝結構，各晶片封裝結構包含有： 兩側邊； 一晶片，其具有一主動面及一背面，該背面係相對於該主動面； 一鈍化層，其設置於晶片的主動面； 多個外導電元件，其設置於晶片的主動面並與晶片形成電連接，且各外導電元件具有一切割端緣，該切割端緣外露於該晶片封裝結構之至少一側邊上； 多個黏著層，其分別設置於相鄰的晶片封裝結構之間； 一第一封裝材，其包覆所述晶片封裝結構，且具有沿所述切割端緣設置之穿孔； 一側邊導線，其設置於該第一封裝材之穿孔中，並與所述晶片封裝結構之切割端緣形成電連接； 一基座，其設置於所述相互堆疊之晶片封裝結構中最底部之晶片封裝結構之底面以及該第一封裝材之底面，且其具有一內連接結構，該內連接結構與該側邊導線形成電連接。
本發明所採用的另一技術手段為，創作一種製造堆疊式封裝結構的方法，其中包含以下步驟： 提供多個晶片封裝結構，其中各晶片封裝結構包含有： 一晶片，其具有一主動面及一背面，該背面係相對於該主動面； 一鈍化層，其設置於晶片的主動面； 多個外導電元件，其設置於晶片的主動面並與晶片形成電連接，且具有一切割端緣，該切割端緣外露於該晶片封裝結構之至少一側邊上； 提供一基板，其中該基板包含有： 一內部電路； 多個上連接墊，其與內部電路及側邊導線形成電連接； 將所述晶片封裝結構堆疊於該基板上，其中晶片封裝結構之背面係朝向與其相鄰之晶片封裝結構的主動面設置，多個黏著層係分別設置於相鄰的晶片封裝結構之間，且該基板設置於所述相互堆疊之晶片封裝結構中最底部之晶片封裝結構之底面； 設置一第一封裝材覆蓋於該基板上的所述晶片封裝結構上； 設置一穿孔於該第一封裝材上以外露出所述切割端緣； 設置一側邊導線於該穿孔中，以與所述切割端緣及上連接墊形成電連接； 執行單體化以形成數個堆疊式封裝結構。
本發明所採用的另一技術手段為，創作一種製造堆疊式封裝結構的方法，其中包含以下步驟： 提供多個晶片封裝結構，其中各晶片封裝結構包含有： 一晶片，其具有一主動面及一背面，該背面係相對於該主動面； 一鈍化層，其設置於晶片的主動面； 多個外導電元件，其設置於晶片的主動面並與晶片形成電連接，且具有一切割端緣，該切割端緣外露於該晶片封裝結構之至少一側邊上； 將所述晶片封裝結構堆疊於一載板上，其中晶片封裝結構之背面係朝向與其相鄰之晶片封裝結構的主動面設置，多個黏著層係分別設置於相鄰的晶片封裝結構之間，且該載板設置於所述相互堆疊之晶片封裝結構中最底部之晶片封裝結構之底面； 設置一第一封裝材覆蓋於該載板上的所述晶片封裝結構上； 設置一穿孔於該第一封裝材上以外露出所述切割端緣； 設置一側邊導線於該穿孔中，以與所述切割端緣形成電連接； 移除該載板以外露出該側邊導線； 設置一重佈線層與側邊導線之端部形成電連接； 執行單體化以形成數個堆疊式封裝結構。
本發明的優點在於，藉由側邊導線設置於封裝材之穿孔中並與晶片封裝結構之切割端緣形成電連接，且基座中設有內連接結構以使側邊導線與外接端子形成電連接，因而簡化了用以形成電連接的製造方法，以提供堆疊式封裝結構整體的可靠度以及製造堆疊式封裝結構的UPH。
以下配合圖式及本發明之實施例，進一步闡述本發明為達成預定發明目的所採取的技術手段，其中圖式已被簡化以僅為了說明目的，而通過描述本發明的元件和組件之間的關係來說明本發明的結構或方法 發明，因此，圖中所示的元件不以實際數量、實際形狀、實際尺寸以及實際比例呈現，尺寸或尺寸比例已被放大或簡化，藉此提供更好的說明，已選擇性地設計和配置實際數量、實際形狀或實際尺寸比例，而詳細的元件佈局可能更複雜。
請參閱圖12A，本發明之堆疊式封裝結構90包含有數個晶片封裝結構10，各晶片封裝結構10包含有多個側邊、一晶片11、一鈍化層（passivation layer）12及數個外導電元件13。晶片11具有一主動面111及一背面112，背面112係與主動面111位於相反的面上，鈍化層12設於主動面111上，外導電元件13設於主動面111上，各外導電元件13具有一切割端緣（cut edge）130，切割端緣130外露於晶片封裝結構10之至少一側邊。在一實施例中，所述外導電元件13之切割端緣130外露於晶片封裝結構10之多個側邊。以下所示為晶片封裝結構10的各實施態樣，但本發明不限於此。
如圖1A至1C所示之實施例，晶片封裝結構10包含有數個焊墊131、數個外接導線132、及一晶片介電層14，各焊墊131設於主動面111上且被鈍化層12所包覆，各外接導線132於相對應的焊墊131上並延伸出鈍化層12外，各外接導線132具有一端部外露於晶片封裝結構10之其中一側邊上，晶片介電層14設於鈍化層12及外接導線132上，其可為聚酰亞胺（polyimide）層。
如圖2A至2C所示之實施例，晶片封裝結構10A包含有數個導電墊133A，各導電墊133A設於晶片11A之主動面111A上且被鈍化層12所包覆，各導電墊133A具有一端部外露於晶片封裝結構10A之其中一側邊上。
如圖3A至3C所示之實施例，晶片封裝結構10B包含有數個接合墊134B及數個矽穿孔（through silicon vias，TSV）135B，各接合墊134B設於晶片11B之主動面111B上，且被鈍化層12B所包覆，各矽穿孔135B設於晶片11B中並與相對應的接合墊134B耦合，各矽穿孔135B具有一端部外露於晶片封裝結構10B之其中一側邊上。
綜上所述，各外導電元件13的切割端緣130可為如圖1A至1B所示之外接導線132、可為如圖2A至2C所示之導電墊133A、或可為如圖3A至3C所示之矽穿孔135B。如圖1A至1B所示之外接導線132、如圖2A至2C所示之導電墊133A、及如圖3A至3C所示之矽穿孔135B的端部可外露於晶片封裝結構10、10A、10B的至少一側邊。
圖4至11所示為本發明之製造方法，其包含以下步驟：
請參閱圖4，將數個晶片封裝結構10相互堆疊後形成一晶片堆100，藉由數個黏著層20設置於相鄰的晶片封裝結構10之間，以將數個晶片封裝結構10相互黏合，黏著層20係設於晶片11之背面112，黏著層20可為晶粒貼附膜（die attach film，DAF）、環氧樹脂（epoxy）、絕緣膠（insulation paste）或其類似物。各晶片封裝結構10可透過精密對準程序相互對齊、或可不實施對準程序而不對齊。
請參閱圖5A及5B所示，數個晶片堆100被第一封裝材（encapsulant）30所包覆，切割被第一封裝材30包覆後之晶片堆100以形成至少一晶片封裝體40，第一封裝材30可對晶片堆100提供封裝保護，以避免短路或污染，且在切割過程中對結構提供穩定性。在一實施例中，當晶片堆100被切割後，所述晶片封裝結構10之至少一側邊的切割端緣130外露且相互對齊。在一實施例中，當所述晶片封裝結構10並未相互對齊而成形為晶片堆100時，切割所述晶片堆100時將使得所述晶片封裝結構10相互對齊，如圖4所示之所述晶片封裝結構10之間的偏差值D1 ，可小於導電元件13之節距（pitch）的一半，以避免當晶片堆100切割後產生缺陷。
請參閱圖6A所示，將所述晶片封裝體40排列在一基板50上，所述晶片封裝體40被一第二封裝材60所覆蓋，所述晶片封裝體40可貼附於該基板50上，該載板50包含一內部電路51、數個上連接墊52、及數個下連接墊53。所述上連接墊52及下連接墊53分別成形於該基板50之相對側邊，且與該內部電路51形成電連接，所述晶片封裝體40設置於該上連接墊52上，該第二封裝材60可對晶片堆100提供封裝保護，以避免短路或污染。
請參閱圖7A及圖7B所示，可在第二封裝材60上成形有穿孔61以將位於至少一側邊的切割端緣130外露。在一實施例中，部份移除該第二封裝材60以成形一穿孔61，該穿孔61設於所述切割端緣130的側邊，並使基板50之其中一上連接墊52露出。在一實施例中，數個穿孔61成形於該第二封裝材60中，所述穿孔61分別設於所述切割端緣130之側邊，並使基板50之上連接墊52露出。在一實施例中，利用蝕刻製程將第二封裝材60加以移除來成形所述穿孔61，所述蝕刻製程亦確保當所述切割端緣130外露後係位於共平面上。在一實施例中，部份移除該第二封裝材60以成形至少一切割道開口62，所述切割道開口62圍繞設置於該晶片封裝體40。
請參閱圖8A至圖9B所示，一側邊導線70設置於所述穿孔61中且與所述切割端緣130形成電連接。在一實施例中，數個側邊導線70分別設置所述穿孔61中，所述側邊導線70可透過濺鍍（sputtering）、電鍍（electroplating）等方法成形之。在另一實施例中，成形一薄金屬層71於所述穿孔61及切割道開口62之壁面上，接著覆蓋一光阻層72於所述切割道開口62上，再成形所述側邊導線70於所述穿孔61中（如圖8A及8B所示），所述薄金屬層71及所述側邊導線70可透過濺鍍（sputtering）、電鍍（electroplating）等方法成形之，隨後將光阻層72移除後，再進行一蝕刻製程以移除切割道開口62中的薄金屬層71，由於所述側邊導線70設置於所述穿孔61中而形成較厚的金屬導線，故在該蝕刻製程中，所述側邊導線70僅有其頂端之薄層會被連同該薄金屬層71一併移除。
請參閱圖10所示，所述第二封裝材60、所述晶片封裝體40及所述側邊導線70被一第三封裝材80所覆蓋。在一實施例中，所述切割道開口62亦被該第三封裝材80所填充。
請參閱圖11所示，數個外接端子81分別設置於該基板50之下連接墊53上，所述外接端子81可為多個錫球（solder ball）、多個銲錫（solder paste）、多個連接墊、或多個連接接腳。又，將所述晶片封裝體40沿切割道開口62加以單體化（singulated）以形成多個堆疊式封裝結構90。
藉由外露於晶片封裝結構10之至少一側邊上的所述切割端緣130，所述晶片11之間的電連接，係可透過設置於穿孔61中的側邊導線70、及側邊上的切割端緣130來加以達成，而晶片11與外接端子81之間的電連接，也可透過基板50、設置於穿孔61中的側邊導線70、及側邊上的切割端緣130來加以達成，因此，本發明係簡化了用以形成電連接的製造方法，以提高堆疊式封裝結構90的可靠度以及製造堆疊式封裝結構90的UPH。再者，基於所述晶片封裝結構10可在如圖5A及5B所示之切割流程後加以對準、且所述切割端緣130可在如圖7A、7B所示之蝕刻流程後呈共平面，則在堆疊晶片封裝結構10時所需的精準度也可相對要求較低，因此，本發明之製造方法係更進一步簡化以提昇製造堆疊式封裝結構90的UPH。
在如圖12A所示之一實施例中，晶片堆疊封裝結構90包含有層疊的數個晶片11，其被第三封裝材80及第二封裝材60所覆蓋，層疊的晶片11可透過切割端緣130、側邊導線70、基板50的內部電路51及外接端子81與外部電路板形成電連接。
在如圖12B所示堆疊式晶片封裝結構90A之一實施例中，第三封裝材80被一金屬層82所覆蓋，該金屬層82係接地或電連接一電壓源以提供電磁干擾護罩（electromagnetic interference shield, EMI shield），該金屬層82可透過濺鍍成形之。
本發明之另一實施例所示之製造堆疊式封裝結構的方法包含以下步驟，但不限於此：
請參閱圖13所示，所述晶片封裝體40設置於一載板50B上且被該第二封裝材60所覆蓋，接著部份移除該第二封裝材60以將側邊之切割端緣130加以外露，並成形穿孔61，接著將側邊導線70設於所述穿孔61中。在一實施例中，部份移除第二封裝材60及成形側邊導線70之步驟如同圖7A至9B中所示之步驟。
請參閱圖14所示，該第二封裝材60、所述晶片封裝體40及所述側邊導線70被該第三封裝材80所覆蓋以形成一堆疊式封裝結構半成品900B。在一實施例中，成形該第三封裝材80之步驟如同圖10中所示之步驟。接著將載板50B移除以露出堆疊式封裝結構半成品900B之背面901B。在一實施例中，載板50B透過一研磨製程加以移除。側邊導線70之端部係外露於堆疊式封裝結構半成品900B之背面901B。
請參閱圖15及圖16所示，一重佈線層（redistribution layer, RDL）及多個外接端子81成形於堆疊式封裝結構半成品900B之背面901B上，該重佈線層與所述側邊導線70及所述外接端子81形成電連接，該重佈線層包含有介電層51B及電路層52B，電路層52B以導電金屬成形之。在一實施例中，電路層52B可為多層金屬堆疊，如鈦（Titanium，Ti）/銅（Copper，Cu）/銅或鈦/銅/銅/鎳（Nickel，Ni）/金（Gold，Au）。在一實施例中，介電層51B可為一聚醯亞胺（polyimide, PI）層用來覆蓋並隔絕電路層52B之多層金屬堆疊。在一實施例中，該介電層51B包含有一第一介電層級一第二介電層分別成形於電路層52B之上及之下。在一實施例中，一凸塊下金屬（under bump metallurgy, UBM）層成形於該重佈線層及該外接端子81之間並分別與之形成電連接，電路層52B之金屬層的數量以及介電層51之數量並未受本實施例所揭露之限制，並可依照需求設計之。
接著進行單體化製程而成形出堆疊式封裝結構90B。
在如圖17所示之實施例中，第三封裝材80被一金屬層82所覆蓋，該金屬層82係接地或電連接一電壓源以提供電磁干擾護罩。
本發明之另一實施例所示之堆疊式封裝結構90可包含有以下結構，但不限於此，且本發明之另一實施例所示之製造方法可包含相對應的步驟。
在如圖6所示之步驟執行後，如圖18A及圖18B所示，部份移除該第二封裝材60以成形一穿孔61、一切割道開口62、一EMI開口63C，該EMI開口63C可圍繞該晶片封裝體40。
請參閱圖19A及圖19B所示，一側邊導線70設置於該穿孔61中且與所述上連接墊52及切割端緣130形成電連接，一導電線83C設置於EMI開口63C中且與基板50之接地訊號形成電連接。
請參閱圖20所示，該晶片封裝體40及該側邊導線70被該第三封裝材80C所覆蓋。
請參閱圖21所示，該金屬層82C設置於該第三封裝材80C上且與導電線83C形成電連接。在一實施例中，該導電係83C及該金屬層82C以濺鍍方法成形之。
請參閱圖22所示，多個外接端子81分別設置於基板50之下連接墊53上，接著沿切割道開口62將晶片封裝體40單體化以形成多個堆疊式封裝體90C。在一實施例中，具有該導電線83C及該金屬層82C之該堆疊式封裝體90C可具有至少一重佈線層及至少一介電層來取代該基板。
以上所述僅是本發明的實施例而已，並非對本發明做任何形式上的限制，雖然本發明已以實施例揭露如上，然而並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明技術方案的範圍內，當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。
10、10A、10B‧‧‧晶片封裝結構
11、11A、11B‧‧‧晶片
111、111A、111B‧‧‧主動面
112‧‧‧背面
12、12A、12B‧‧‧鈍化層
13‧‧‧外導電元件
130‧‧‧切割端緣
131‧‧‧焊墊
132‧‧‧外接導線
133A‧‧‧導電墊
134B‧‧‧接合墊
135B‧‧‧矽穿孔
100‧‧‧晶片堆
20‧‧‧黏著層
30‧‧‧第一封裝材
40‧‧‧晶片封裝體
50‧‧‧基板
51‧‧‧內部電路
52‧‧‧上連接墊
53‧‧‧下連接墊
50B‧‧‧載板
51B‧‧‧介電層
52B‧‧‧電路層
60‧‧‧第二封裝材
61‧‧‧穿孔
62‧‧‧切割道開口
63C‧‧‧EMI開口
70‧‧‧側邊導線
71‧‧‧薄金屬層
72‧‧‧光阻層
80、80C‧‧‧第三封裝材
81‧‧‧外接端子
82、82C‧‧‧金屬層
83C‧‧‧導電線
90、90C‧‧‧堆疊式封裝結構
900B‧‧‧堆疊式封裝結構半成品
901B‧‧‧背面
圖1A為本發明之堆疊式封裝結構的晶片封裝結構之第一實施例的上視剖面圖。 圖1B為圖1A之晶片封裝結構的前視剖面圖。 圖1C為圖1A之晶片封裝結構的側視剖面圖。 圖2A為本發明之堆疊式封裝結構的晶片封裝結構之第二實施例的上視剖面圖。 圖2B為圖2A之晶片封裝結構的前視剖面圖。 圖2C為圖2A之晶片封裝結構的側視剖面圖。 圖3A為本發明之堆疊式封裝結構的晶片封裝結構之第三實施例的上視剖面圖。 圖3B為圖3A之晶片封裝結構的前視剖面圖。 圖3C為圖3A之晶片封裝結構的側視剖面圖。 圖4、6A、7A、8A、9A、10及11為本發明之製造方法的第一實施例之各製程中堆疊式封裝結構的前視剖面圖。 圖5A、5B、7B、8B及9B為本發明之製造方法的第一實施例之各製程中堆疊式封裝結構的上視圖。 圖12A為本發明堆疊式封裝結構之第一實施例的前視剖面圖。 圖12B為本發明堆疊式封裝結構之第二實施例的前視剖面圖。 圖13至15為本發明之製造方法的第二實施例之各製程中堆疊式封裝結構的前視剖面圖。 圖16為本發明堆疊式封裝結構之第三實施例之各製程中堆疊式封裝結構的前視剖面圖。 圖17為本發明堆疊式封裝結構之第四實施例之各製程中堆疊式封裝結構的前視剖面圖。 圖18A、19A、20及21為本發明之製造方法的第四實施例之各製程中堆疊式封裝結構的前視剖面圖。 圖18B及19B為本發明之製造方法的第四實施例之各製程中堆疊式封裝結構的上視圖。 圖22為本發明之製造方法的第五實施例之製程中堆疊式封裝結構的前視剖面圖。

Claims (10)

  1. 一種堆疊式封裝結構，其中包括： 相互堆疊的數個晶片封裝結構，各晶片封裝結構包含有： 兩側邊； 一晶片，其具有一主動面及一背面，該背面係相對於該主動面； 一鈍化層，其設置於晶片的主動面； 多個外導電元件，其設置於晶片的主動面並與晶片形成電連接，且各外導電元件具有一切割端緣，該切割端緣外露於該晶片封裝結構之至少一側邊上； 多個黏著層，其分別設置於相鄰的晶片封裝結構之間； 一第一封裝材，其包覆所述晶片封裝結構，且具有沿所述切割端緣設置之穿孔； 一側邊導線，其設置於該第一封裝材之穿孔中，並與所述晶片封裝結構之切割端緣形成電連接； 一基座，其設置於所述相互堆疊之晶片封裝結構中最底部之晶片封裝結構之底面以及該第一封裝材之底面，且其具有一內連接結構，該內連接結構與該側邊導線形成電連接。
  2. 如請求項1所述之堆疊式封裝結構，其中： 該基座包含一基板； 該內連接結構設置於該基板中且包含有： 一內部電路； 多個上連接墊，其與內部電路及側邊導線形成電連接； 多個下連接墊，其與內部電路形成電連接； 多個外接端子，其設置於基板之底部且與下連接墊形成電連接。
  3. 如請求項1所述之堆疊式封裝結構，其中： 該內連接結構包含有一重佈線層，該重佈線層與側邊導線形成電連接； 多個外接端子，其設置於該重佈線層之底部且與該重佈線層形成電連接。
  4. 如請求項1所述之堆疊式封裝結構，其進一步包含有一金屬層，該金屬層包覆該第一封裝材。
  5. 如請求項1所述之堆疊式封裝結構，其進一步包含有： 一第三封裝材，其覆蓋該側邊導線； 一電磁干擾開口，其設置於該第三封裝材且圍繞所述相互堆疊的晶片封裝結構； 一導電線，其設置於該電磁干擾開口中； 一金屬層，其設置於該第三封裝材上且與該導電線形成電連接。
  6. 一種製造堆疊式封裝結構的方法，其中包含以下步驟： 提供多個晶片封裝結構，其中各晶片封裝結構包含有： 一晶片，其具有一主動面及一背面，該背面係相對於該主動面； 一鈍化層，其設置於晶片的主動面； 多個外導電元件，其設置於晶片的主動面並與晶片形成電連接，且具有一切割端緣，該切割端緣外露於該晶片封裝結構之至少一側邊上； 提供一基板，其中該基板包含有： 一內部電路； 多個上連接墊，其與內部電路及側邊導線形成電連接； 將所述晶片封裝結構堆疊於該基板上，其中晶片封裝結構之背面係朝向與其相鄰之晶片封裝結構的主動面設置，多個黏著層係分別設置於相鄰的晶片封裝結構之間，且該基板設置於所述相互堆疊之晶片封裝結構中最底部之晶片封裝結構之底面； 設置一第一封裝材覆蓋於該基板上的所述晶片封裝結構上； 設置一穿孔於該第一封裝材上以外露出所述切割端緣； 設置一側邊導線於該穿孔中，以與所述切割端緣及上連接墊形成電連接； 執行單體化以形成數個堆疊式封裝結構。
  7. 如請求項6所述之製造堆疊式封裝結構的方法，其中在設置穿孔的步驟中，進一步包含設置一切割道開口於該第一封裝材，其中該穿孔設置於該切割道開口與所述晶片封裝結構之間。
  8. 如請求項6所述之製造堆疊式封裝結構的方法，其中： 在設置穿孔的步驟中，進一步包含有設置一電磁干擾開口於該第一封裝材中，且該電磁干擾開口圍繞所述相互堆疊的晶片封裝結構； 在設置側邊導線的步驟中，進一步包含有設置一導電線於該電磁干擾開口中； 在設置側邊導線的步驟之後，進一步包含有設置一第三封裝材包覆該側邊導線，設置一金屬層於該第三封裝材上且與該導電線形成電連接。
  9. 一種製造堆疊式封裝結構的方法，其中包含以下步驟： 提供多個晶片封裝結構，其中各晶片封裝結構包含有： 一晶片，其具有一主動面及一背面，該背面係相對於該主動面； 一鈍化層，其設置於晶片的主動面； 多個外導電元件，其設置於晶片的主動面並與晶片形成電連接，且具有一切割端緣，該切割端緣外露於該晶片封裝結構之至少一側邊上； 將所述晶片封裝結構堆疊於一載板上，其中晶片封裝結構之背面係朝向與其相鄰之晶片封裝結構的主動面設置，多個黏著層係分別設置於相鄰的晶片封裝結構之間，且該載板設置於所述相互堆疊之晶片封裝結構中最底部之晶片封裝結構之底面； 設置一第一封裝材覆蓋於該載板上的所述晶片封裝結構上； 設置一穿孔於該第一封裝材上以外露出所述切割端緣； 設置一側邊導線於該穿孔中，以與所述切割端緣形成電連接； 移除該載板以外露出該側邊導線； 設置一重佈線層與側邊導線之端部形成電連接； 執行單體化以形成數個堆疊式封裝結構。
  10. 如請求項9所述之製造堆疊式封裝結構的方法，其中在設置穿孔的步驟中，進一步包含設置一切割道開口於該第一封裝材，其中該穿孔設置於該切割道開口與所述晶片封裝結構之間。
TW107126658A 2018-01-10 2018-08-01 堆疊式封裝結構及其製造方法 TWI671876B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/867,613 2018-01-10
US15/867,613 US20190214367A1 (en) 2018-01-10 2018-01-10 Stacked package and a manufacturing method of the same

Publications (2)

Publication Number Publication Date
TW201931545A true TW201931545A (zh) 2019-08-01
TWI671876B TWI671876B (zh) 2019-09-11

Family

ID=67140190

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107126658A TWI671876B (zh) 2018-01-10 2018-08-01 堆疊式封裝結構及其製造方法

Country Status (3)

Country Link
US (1) US20190214367A1 (zh)
CN (1) CN110021572B (zh)
TW (1) TWI671876B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210120221A (ko) 2020-03-26 2021-10-07 삼성전자주식회사 반도체 스택 및 그 제조 방법
US11935824B2 (en) * 2021-09-29 2024-03-19 Microchip Technology Incorporated Integrated circuit package module including a bonding system

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100524736C (zh) * 2005-11-11 2009-08-05 南茂科技股份有限公司 堆叠型晶片封装结构
US8546189B2 (en) * 2008-09-22 2013-10-01 Stats Chippac, Ltd. Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection
US8822281B2 (en) * 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US9318411B2 (en) * 2013-11-13 2016-04-19 Brodge Semiconductor Corporation Semiconductor package with package-on-package stacking capability and method of manufacturing the same
US9601467B1 (en) * 2015-09-03 2017-03-21 Invensas Corporation Microelectronic package with horizontal and vertical interconnections
US9659878B2 (en) * 2015-10-20 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level shielding in multi-stacked fan out packages and methods of forming same
TW201724423A (zh) * 2015-12-23 2017-07-01 力成科技股份有限公司 扇出型封裝堆疊構造與方法
TWI567897B (zh) * 2016-06-02 2017-01-21 力成科技股份有限公司 薄型扇出式多晶片堆疊封裝構造與製造方法
CN106024766B (zh) * 2016-07-18 2018-10-02 华进半导体封装先导技术研发中心有限公司 高堆叠晶圆系统级封装结构及制备方法
CN106328611B (zh) * 2016-10-21 2019-03-12 苏州日月新半导体有限公司 半导体封装构造及其制造方法
CN106783805A (zh) * 2017-03-13 2017-05-31 中国科学院微电子研究所 射频多芯片封装及屏蔽电路

Also Published As

Publication number Publication date
US20190214367A1 (en) 2019-07-11
TWI671876B (zh) 2019-09-11
CN110021572B (zh) 2021-03-23
CN110021572A (zh) 2019-07-16

Similar Documents

Publication Publication Date Title
US10867976B2 (en) Semiconductor packages having dummy connectors and methods of forming same
CN111971792B (zh) 具有偏移3d结构的多芯片封装
US10651050B2 (en) Semiconductor device packages and structures
US11004812B2 (en) Package structure and method of forming the same
TWI654723B (zh) 封裝結構之製法
TWI695432B (zh) 封裝及其形成方法
US11291116B2 (en) Integrated circuit structure
KR20090080752A (ko) 반도체 패키지 및 그 제조방법
US10290610B2 (en) PoP device and method of forming the same
TWI662677B (zh) 堆疊式封裝結構及其製造方法
US20160049359A1 (en) Interposer with conductive post and fabrication method thereof
EP3361502B1 (en) Semiconductor package with rigid under bump metallurgy (ubm) stack
US9972606B2 (en) Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding
US9548283B2 (en) Package redistribution layer structure and method of forming same
TWI622153B (zh) 系統級封裝及用於製造系統級封裝的方法
US8361857B2 (en) Semiconductor device having a simplified stack and method for manufacturing thereof
TW201742208A (zh) 封裝結構、疊層封裝元件及其形成方法
US20230089795A1 (en) Semiconductor package
CN114765110A (zh) 封装结构及其制造方法
US20080258306A1 (en) Semiconductor Device and Method for Fabricating the Same
TWI671876B (zh) 堆疊式封裝結構及其製造方法
CN114883196A (zh) 半导体器件及其制造方法
TWI712134B (zh) 半導體裝置及製造方法
KR20220034596A (ko) 반도체 패키지
TW202011548A (zh) 電子封裝件及其製法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees