TW201742208A - 封裝結構、疊層封裝元件及其形成方法 - Google Patents

封裝結構、疊層封裝元件及其形成方法 Download PDF

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TW201742208A
TW201742208A TW105137572A TW105137572A TW201742208A TW 201742208 A TW201742208 A TW 201742208A TW 105137572 A TW105137572 A TW 105137572A TW 105137572 A TW105137572 A TW 105137572A TW 201742208 A TW201742208 A TW 201742208A
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TWI721038B (zh
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楊天中
蘇安治
陳憲偉
王若梅
陳威宇
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台灣積體電路製造股份有限公司
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    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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Abstract

揭露封裝結構、疊層封裝元件及其形成方法。一種封裝結構包括第一晶粒、重佈線層結構、多個UBM接墊、多個接點以及分隔件。重佈線層結構電性連接至第一晶粒。UBM接墊電性連接至重佈線層結構。接點電性連接至UBM接墊。分隔件位於重佈線層結構上方且環繞接點。

Description

封裝結構、疊層封裝元件及其形成方法
本發明實施例是關於封裝結構、疊層封裝元件及其形成方法。
近年來，由於各種電子組件（例如電晶體、二極體、電阻器、電容器等）的積集密度不斷提升，半導體工業因而快速成長。這種積集密度的提升，大多是因為最小特徵尺寸的持續縮小，因而允許將更多的組件整合在一特定的區域中。
相較於先前的封裝件，這些尺寸較小的電子組件佔據較小的面積，因而需要較小的封裝件。用於半導體的封裝件的類型的實例包括四方扁平封裝（quad flat pack；QFP）、針格陣列（pin grid array；PGA）、球格陣列（ball grid array；BGA）、覆晶（flip chip；FC）、三維積體電路（three dimensional integrated circuit；3DIC）、晶圓級封裝（wafer level package；WLP）以及疊層封裝（package on package；PoP）元件。在半導體晶圓級上將晶粒置放於晶粒上來製備一些三維積體電路。由於堆疊晶粒之間的內連線長度的減少，這些三維積體電路提供了改良的積集密度以及其他優勢，例如較快的速度和較高的帶寬（bandwidth）等。然而，仍存在許多與三維積體電路相關的挑戰。
根據本發明的一些實施例，一種封裝結構包括第一晶粒、重佈線層結構、多個凸點下金屬（under-ball metallurgy；UBM）接墊、多個接點以及分隔件（separator）。重佈線層結構電性連接至第一晶粒。UBM接墊電性連接至重佈線層結構。接點電性連接至UBM接墊。分隔件位於重佈線層結構上方且環繞接點。
以下揭露內容提供許多不同的實施例或實例，用於實現所提供標的之不同特徵。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在…下」、「在…下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
圖1A至圖1F為根據一些實施例所繪示的疊層封裝元件的形成方法的剖面示意圖。
請參照圖1A，提供載板C，其中載板C具有晶粒100以及多個積體扇出型穿孔（through integrated fan-out vias；through InFO vias）TIV，且積體扇出型穿孔TIV位於晶粒100側邊。在一些實施例中，積體扇出型穿孔TIV稱為封裝件穿孔（through package vias；TPV）或界面穿孔（through interface vias）。在一些實施例中，載板C具有形成於其上的剝離層DB以及介電層101，且剝離層DB位於載板C與介電層101之間。在一些實施例中，載板C為玻璃基底，形成於玻璃基底上的剝離層DB為光熱轉換（light-to-heat conversion；LTHC）釋放層，且形成於剝離層上的介電層101為聚合物層。舉例來說，介電層101包括聚苯並噁唑（polybenzoxazole；PBO）、聚醯亞胺（polyimide；PI）、合適的有機或無機材料或類似物。在一些實施例中，晶粒100具有基底100a、位於基底100a上方的接墊100b、位於基底100a上方且裸露出部分接墊100b的鈍化層100c、位於鈍化層100c上方且電性連接至接墊100b的接點100d，以及位於鈍化層100c上方且位於接點100d側邊的保護層100e。在一些實施例中，接點100d包括錫凸塊、金凸塊、銅柱或類似物，且由電鍍製程所形成。在一些實施例中，保護層100e包括聚苯並噁唑（PBO）、聚醯亞胺（PI）、合適的有機或無機材料或類似物。在一些實施例中，積體扇出型穿孔TIV包括銅、鎳、錫、其組合或類似物，且由電鍍製程所形成。在一些實施例中，取放晶粒100於載板C上之前，於載板C上形成積體扇出型穿孔TIV。在替代性實施例中，取放晶粒100於載板C上之後，於載板C上形成積體扇出型穿孔TIV。
請繼續參照圖1A，於載板C上方形成封裝體102，以囊封晶粒100以及積體扇出型穿孔TIV。在一些實施例中，封裝體102環繞晶粒100以及積體扇出型穿孔TIV，且裸露出積體扇出型穿孔TIV以及接點100d的表面。封裝體102包括模製化合物（例如環氧樹脂）、光敏材料（例如PBO）、聚醯亞胺（PI）或苯環丁烯（benzocyclobutene；BCB）、其組合或類似物。封裝體102的形成方法包括：於載板C上形成封裝體材料層（未繪示），且所述封裝體材料層覆蓋半導體晶粒100以及積體扇出型穿孔TIV；以及進行研磨製程以移除部分所述封裝體材料層，直到裸露出積體扇出型穿孔TIV以及接點100d的表面。
請參照圖1B，於晶粒100上方形成重佈線層結構117，且重佈線層結構117電性連接至晶粒100。在一些實施例中，重佈線層結構117包括交替堆疊的多個聚合物層104、108、112以及116以及多個重佈線層106、110以及114。具體地說，重佈線層106電性連接至接點100d以及積體扇出型穿孔TIV且穿過聚合物層104，重佈線層110電性連接至重佈線層106且穿過聚合物層108，重佈線層114電性連接至重佈線層110且穿過聚合物層112，以及聚合物層116覆蓋重佈線層114。在一些實施例中，聚合物層104、108、112以及116中的每一者包括光敏材料（例如PBO）、聚醯亞胺（PI）、苯環丁烯（BCB）、其組合或類似物。在一些實施例中，重佈線層106、110以及114中的每一者包括銅、鎳、鈦、其組合或類似物，且由電鍍製程所形成。本發明實施例並不對聚合物層或重佈線層的數目做限制。
請繼續參照圖1B，形成多個凸點下金屬（UBM）接墊118以及分隔件119，其中分隔件119位於UBM接墊118側邊。UBM接墊118經配置以用於植球。於電磁干擾層（electromagnetic interference layer）的形成步驟期間，分隔件119配置成將一結構與固持所述結構的托盤分開，細節將詳述於下。在一些實施例中，UBM接墊118以及分隔件119由相同材料所構成、提供為具有實質上相等的厚度，且於相同製程步驟中同時形成。具體地說，UBM接墊118以及分隔件119中的每一者包括銅、鎳、鈦、其組合或類似物，且由電鍍製程所形成。在一些實施例中，UBM接墊118以及分隔件119由相同光罩（photolithography reticle、photomask）所定義。也就是說，不需要用於定義分隔件119的額外光罩。
然後，於UBM接墊118上方形成凸塊、焊球或接點120，且接點120電性連接至UBM接墊118。在一些實施例中，接點120由具有低阻值的導電材料所構成，例如錫、鉛、銀、銅、鎳、鉍或其合金，且由合適的製程所形成，例如蒸鍍、電鍍、落球（ball drop）、或網印（screen printing）。在一些實施例中，分隔件119為環狀且環繞最外面UBM接墊118或接點120，如圖2的上視圖所示。在一些實施例中，分隔件119處於浮置電位（floating potential）且電性絕緣於重佈線層結構117以及接點120。
請參照圖1C以及圖1D，載板C從封裝結構P1 的背側剝離，且另一封裝結構P2 接合至相同封裝結構P1 的相同背側。
如圖1C所示，載板C連同晶粒100、重佈線層結構117，UBM接墊118、分隔件119以及接點120一起翻轉，剝離層DB於光熱作用下分解，接著，載板C從封裝結構P1 剝離。
如圖1D所示，提供另一封裝結構P2 。在一些實施例中，封裝結構P2 具有基底203以及安裝於基底203的一表面（例如，頂表面）上的晶粒201。打線207可用於提供晶粒201與位於基底203的頂表面部分中的一組接合墊205之間的電性連接。於這些構件上方形成封裝體209，以保護所述構件免於環境及外來污染。穿孔或積體扇出型穿孔（未繪示）可用於提供接合墊205與位於基底203的底表面部分中的另一組接合墊211之間的電性連接。接點214（例如焊料接點）可形成於基底203的底表面上以電性連接至接合墊211。
將封裝結構P2 接合至封裝結構P1 ，以形成接合結構（bonded structure）。在一些實施例中，封裝結構P2 的接點214對準並插入介電層101中的開口，且電性連接至封裝結構P1 的積體扇出型穿孔TIV。
然後，形成底膠層UF以填入封裝結構P1 與封裝結構P2 之間的空間，且底膠層UF環繞接點214。在一些實施例中，底膠層UF包括模製化合物（例如環氧樹脂），且使用點膠（dispensing）、注入（injecting），及/或噴灑（spraying）技術來形成。
請參照圖1E，將包括封裝結構P1 以及封裝結構P2 的接合結構置放於托盤（tray）T上，其中分隔件119抵靠托盤T的表面，並形成電磁干擾層EMI以覆蓋封裝結構P1 以及封裝結構P2 的外表面或裸露出的表面。電磁干擾層EMI經配置以減少或避免電磁波的發射，且因此減低元件的雜訊及/或元件的失效。在一些實施例中，形成電磁干擾層EMI以覆蓋第二封裝結構P2 的頂面以及側面，且電磁干擾層EMI電性連接至第一封裝結構P1 的重佈線層結構117的重佈線層106、110以及114。在一些實施例中，電磁干擾層EMI包括鋁、鋁合金、銅、銅合金、鈦、氮化鈦、鉭、氮化鉭、鎢、金屬矽化物、其組合或類似物，且由濺鍍或合適的技術所形成。在一些實施例中，電磁干擾層EMI僅位於封裝結構P1 以及封裝結構P2 的裸露出的頂面以及側面上方，而未延伸至封裝結構P1 下方。在替代性實施例中，電磁干擾層EMI可更延伸圍繞封裝結構P1 的底角，並以逐漸減少的厚度從封裝結構P1 的外側往內側沿著聚合物層116的表面延伸，且此厚度相當小。也就是說，電磁干擾層EMI的很少一部分（即使有的話）形成為沿著聚合物層116的表面，且此部分如此薄而不會與托盤T接觸。
請參照圖1F，於形成電磁干擾層EMI之後，從托盤T取起本發明實施例的疊層封裝元件1。
請注意，當形成電磁干擾層EMI時，本發明實施例的分隔件119扮演著將接合結構與托盤T分開的角色。於EMI形成步驟期間，此種分開有助於避免產生習知的EMI毛邊（burr），且因此改良元件效能。
具體地說，於習知的EMI形成步驟期間，將接合結構置放於EMI托盤上但沒有兩者間的分隔件，因此所形成的EMI層會沿著接合結構的外表面濺鍍，且會連續不斷地濺鍍至托盤的表面上。在此情況下，當此接合結構從EMI托盤取起時，會產生習知的EMI毛邊。此外，為了避免所形成的EMI層接觸下封裝結構的最外面接點，從下封裝結構的邊緣至其最外面接點的排除區（keep out zone；KOZ）通常大於約300 μm。
然而，通過配置本發明實施例的位於托盤T與封裝結構P1 （如圖1E以及圖1F所示）之間的分隔件119，不會產生習知的EMI毛邊，且用於EMI遮蔽（shielding）的排除區（KOZ）可大幅減少至100 μm或小於100 μm。
如圖3中區域A的放大圖所示，從最外面UBM接墊118至分隔件119的內邊界的距離為“d”，分隔件119的寬度為“W”，分隔件119的高度為“H”，且從封裝結構P1 的邊緣至分隔件119的外邊界的距離為“D”。上述參數“d”、“W”、“D”以及“H”之間的比率必須在特定範圍內方能達到所提及的效果。
此外，封裝結構P1 與托盤T之間的分開距離為“S”。在一些實施例中，分開距離（“S”）為從分隔件119的裸露出的表面至重佈線層結構117的裸露出的表面的垂直距離。當封裝結構P1 與托盤T之間的分開距離（“S”）增加時，電磁干擾層EMI接觸托盤T的機會變小。在一些實施例中，分開距離（“S”）等於分隔件119的高度（“H”），如圖3所示。
在一些實施例中，d與W的比率為約1:1至1:10。舉例來說，d與W的比率可為約1、1/2、1/3、1/4、1/5、1/6、1/7、1/8、1/9、1/10，包括任意兩個前述數值之間的任何範圍。
在一些實施例中，d與H的比率為約1:1至1:10。舉例來說，d與H的比率可為約1、1/2、1/3、1/4、1/5、1/6、1/7、1/8、1/9、1/10，包括任意兩個前述數值之間的任何範圍。
在一些實施例中，封裝結構P1 的邊緣具有實質上垂直的輪廓，分隔件119的外邊界未對齊於封裝結構P1 的邊緣，且d與D的比率為約1:0.1至1:5。舉例來說，d與D的比率的邊緣可為約10、9、8、7、6、5、4、3、2、1、1/2、1/3、1/4、1/5、包括任意兩個前述數值之間的任何範圍。然而，本發明實施例並不以此為限。在替代性實施例中，封裝結構P1-1 /P1-2 /P1-3 的邊緣具有階梯狀輪廓（例如單階梯輪廓），且分隔件119的外邊界對齊於封裝結構P1-1 /P1-2 /P1-3 的相鄰邊緣，如圖5至圖7所示。也就是說，從封裝結構P1-1 /P1-2 /P1-3 的相鄰邊緣至分隔件119的外邊界的距離（“D”）約為零。在又一些替代性實施例中，封裝結構的邊緣具有階梯狀輪廓（例如多階梯輪廓），且分隔件119的外邊界對齊於封裝結構的階梯狀邊緣的鄰接部分。
在一些實施例中，修改圖1B的步驟使得所形成的聚合物層116裸露出重佈線層114的邊緣部分，並執行類似於圖1C至圖1F中所描述的步驟。因此，如圖5所示，提供了包括封裝結構P1-1 以及封裝結構P2 的疊層封裝元件2，其中分隔件119的外邊界對齊於封裝結構P1-1 的重佈線層結構117的聚合物層116的邊緣，且電磁干擾層EMI電性連接至重佈線層結構117的重佈線層106、110以及114。如圖5所示，分開距離（“S”）為從分隔件119的裸露出的表面至重佈線層結構117的重佈線層114的裸露出的表面的垂直距離，且分開距離（“S”）大於分隔件119高度（“H”）。
在一些實施例中，修改圖1B的步驟使得所形成的聚合物層116、重佈線層114以及聚合物層112均裸露出重佈線層110的邊緣部分，並執行類似於圖1C至圖1F中所描述的步驟。因此，如圖6所示，提供了包括封裝結構P1-2 以及封裝結構P2 的疊層封裝元件3，其中分隔件119的外邊界對齊於封裝結構P1-2 的重佈線層結構117的聚合物層116、重佈線層114以及聚合物層112的邊緣，且電磁干擾層EMI電性連接至重佈線層結構117的重佈線層106以及110。如圖6所示，分開距離（“S”）為從分隔件119的裸露出的表面至重佈線層結構117的重佈線層110的裸露出的表面的垂直距離，且分開距離（“S”）大於分隔件119的高度（“H”）。
在一些實施例中，改圖1B的步驟使得所形成的聚合物層116、重佈線層114、聚合物層112、重佈線層110以及聚合物層108均裸露出重佈線層106的邊緣部分，並執行類似於圖1C至圖1F中所描述的步驟。因此，如圖7所示，提供了包括封裝結構P1-3 以及封裝結構P2 的疊層封裝元件4，其中分隔件119的外邊界對齊於封裝結構P1-3 的重佈線層結構117的聚合物層116、重佈線層114、聚合物層112、重佈線層110以及聚合物層108的邊緣，且電磁干擾層EMI電性連接至重佈線層結構117的重佈線層106。如圖7所示，分開距離（“S”）為從分隔件119的裸露出的表面至重佈線層結構117的重佈線層106的裸露出的表面的垂直距離，且分開距離（“S”）大於分隔件119的高度（“H”）。
上述圖1A至圖1F的製程步驟可參照圖4的流程圖精簡說明如下。
於步驟300，於第一晶粒（例如，晶粒100）上方形成重佈線層結構117，其中重佈線層結構117電性連接至第一晶粒，如圖1A、圖1B以及圖5至圖7所示。於步驟302，形成多個UBM接墊118以及分隔件119，其中分隔件119環繞UBM接墊118，且UBM接墊118電性連接至重佈線層結構117，如圖1B以及圖5至圖7所示。於步驟304，於UBM接墊118上方形成多個接點120，且因此提供第一封裝結構（例如，封裝結構P1 /P1-1 /P1-2 /P1-3 ），如圖1B、圖1C以及圖5至圖7所示。於步驟306，將包括第二晶粒（例如，晶粒201）的第二封裝結構（例如，封裝結構P2 ）接合至第一封裝結構，如圖1D以及圖5至圖7所示。於步驟308中，形成電磁干擾層EMI以覆蓋第一封裝結構以及第二封裝結構的裸露出的頂面以及側面，如圖1E、圖1F以及圖5至圖7所示。由此完成本發明實施例的疊層封裝元件1/2/3/4。
在上述的實施例中，分隔件以及UBM接墊於相同製程步驟中同時形成，但本發明實施例並不限於此。在替代性實施例中，分隔件以及UBM接墊可於不同製程步驟中分開形成。舉例來說，可於形成UBM接墊的步驟之後或之前，形成分隔件。
圖8A至圖8F為根據其他實施例所繪示的疊層封裝元件的形成方法的剖面示意圖。圖9為圖8B的簡化上視圖。圖10為圖8E的區域A的放大圖。圖11為根據其他實施例所繪示的疊層封裝元件的形成方法的流程圖。
圖8A至圖8F的方法與圖1A至圖1F的方法之間的差異在於：分隔件的形成方法。差異處將詳述如下，相同處則不再贅述。
請參照圖8A、圖11以及圖12至圖15，於步驟500中，於第一晶粒（例如，晶粒100）上方形成重佈線層結構117，其中重佈線層結構117電性連接至第一晶粒。
在一些實施例中，重佈線層結構117的邊緣具有實質上垂直的輪廓，如圖8A以及圖12所示。在替代性實施例中，可依先前描述方式修改形成重佈線層結構117的步驟，使重佈線層結構117的邊緣具有階梯狀輪廓，且依製程需要裸露出重佈線層114、110或106的表面，如圖13至圖15所示。
然後，於步驟502中，於重佈線層結構117上方形成多個UBM接墊118，其中UBM接墊118電性連接至重佈線層結構117。接著，於步驟504中，於UBM接墊118上方形成多個接點120。
請參照圖8B、圖8C、圖11以及圖12至圖15，於步驟506中，於形成接點120的步驟之後，形成環繞接點120的分隔件400，且因此提供第一封裝結構（例如，封裝結構P1-4 /P1-5 /P1-6 /P1-7 /P1-8 ）。如圖9的上視圖所示，分隔件400為環狀且環繞最外面UBM接墊118或接點120。在一些實施例中，分隔件400為聚合物壩（polymer dam），其包括模製化合物（例如環氧樹脂）、光敏材料（例如PBO）、聚醯亞胺（PI）或苯環丁烯（BCB）、其組合或類似物。使用點膠、注入，及/或噴灑技術來形成分隔件400。在一些實施例中，分隔件400具有圓頂狀或半球狀。
在一些實施例中，分隔件400的外邊界未對齊於封裝結構P1-4 的邊緣，如圖8B所示。在替代性實施例中，分隔件400的外邊界對齊於封裝結構P1-5 /P1-6 /P1-7 /P1-8 的邊緣，如圖12至圖15所示。如圖12所示，分隔件400的外邊界對齊於封裝結構P1-5 的實質上垂直的邊緣。如圖13至圖15所示，分隔件400的外邊界對齊於封裝結構P1-6 /P1-7 /P1-8 的階梯狀邊緣的鄰接部分。封裝結構P1-6 /P1-7 /P1-8 的階梯狀邊緣與封裝結構P1-1 /P1-2 /P1-3 的階梯狀邊緣類似，故細節於此不再贅述。
請參照圖8D、圖11以及圖12至圖15，於步驟508中，將包括第二晶粒（例如，晶粒201）的第二封裝結構（例如，封裝結構P2 ）接合至第一封裝結構。
請參照圖8E、圖8F、圖11以及圖12至圖15，於步驟510中，形成電磁干擾層EMI以覆蓋第一封裝結構以及第二封裝結構的裸露出的頂面以及側面。由此形成本發明實施例的疊層封裝元件5/6/7/8/9。圖10中區域A的放大圖繪示參數“d”、“W”、“D”以及“H”的涵義。上述參數之間的比率與圖3中所述的比率類似，故細節於此不再贅述。
請注意，在圖12的疊層封裝元件6中，雖然分隔件400的外邊界對齊於封裝結構P1-5 的筆直邊緣，但由於分隔件400具有圓頂狀，所形成的電磁干擾層EMI很難沿著分隔件400的表面延伸，因此，所形成的電磁干擾層EMI於EMI形成步驟期間不會與托盤接觸。
在上述實施例中，是以分隔件為金屬分隔件或聚合物分隔件為例來說明，但不用於限定本發明實施例。在一些實施例中，分隔件可為包含導體材料以及絕緣材料的複合分隔件。
圖16為根據又一些其他實施例所繪示的疊層封裝元件的形成方法的流程圖。圖17至圖21為根據又一些其他實施例所繪示的疊層封裝元件的剖面示意圖。
於步驟600中，於第一晶粒（例如，晶粒100）上方形成重佈線層結構117，其中重佈線層結構117電性連接至第一晶粒。於步驟602中，形成多個UBM接墊118以及第一分隔件（例如，分隔件119），其中第一分隔件環繞UBM接墊118，且UBM接墊118電性連接至重佈線層結構117。於步驟604中，於UBM接墊120上方形成多個接點120。於步驟606中，於形成接點120的步驟之後，於第一分隔件（例如，分隔件119）上形成第二分隔件（例如，分隔件400），且因此提供第一封裝結構（例如，封裝結構P1-9 /P1-10 /P1-11 /P1-12 /P1-13 ）。於步驟608中，將包括第二晶粒（例如，晶粒201）的第二封裝結構（例如，封裝結構P2 ）接合至第一封裝結構。於步驟610中，形成電磁干擾層EMI以覆蓋第一封裝結構以及第二封裝結構的裸露出的頂面以及側面。由此形成本發明實施例的疊層封裝元件10/11/12/13/14。上述參數“d”、“W”、“D”以及“H”之間的比率範圍與圖3中所述的比率範圍類似，故細節於此不再贅述。
疊層封裝元件10/11/12/13/14（如圖17至圖21所示）與疊層封裝元件5/6/7/8/9（如圖8F以及圖12至圖15所示）類似，且其差異處在於：疊層封裝元件10/11/12/13/14中的分隔件為雙層結構，其包括由金屬所構成的分隔件119以及由聚合物所構成的分隔件400；而疊層封裝元件5/6/7/8/9中的分隔件400為單層結構，其包括由聚合物所構成的分隔件400。於EMI形成步驟期間，疊層封裝元件10/11/12/13/14中的雙層分隔件可提供下封裝結構與托盤之間的較大分開距離（“S”），以避免產生習知的EMI毛邊（burr），且因此改良元件效能。
在一些實施例中，本發明實施例提供封裝結構P1 /P1-1 /P1-2 /P1-3 /P1-4 /P1-5 /P1-6 /P1-7 /P1-8 /P1-9 /P1-10 /P1-11 /P1-12 /P1-13 ，其包括晶粒100、重佈線層結構117、多個UBM接墊118、多個接點120以及分隔件119/400。封裝結構P1 /P1-1 /P1-2 /P1-3 /P1-4 /P1-5 /P1-6 /P1-7 /P1-8 /P1-9 /P1-10 /P1-11 /P1-12 /P1-1 具有第一側（例如，前側）以及與第一側相對的第二側（例如，背側）。重佈線層結構117電性連接至晶粒100。UBM接墊118電性連接至重佈線層結構117。接點120電性連接至UBM接墊118且由封裝結構的第一側裸露出。具體地說，一個UBM接墊118位於重佈線層結構117與每一個接點120之間。分隔件119/400位於封裝結構的第一側上且位於最外面接點120側邊。具體地說，分隔件119/400位於重佈線層結構117上方且環繞最外面接點120。
在封裝結構P1 /P1-1 /P1-2 /P1-3 中，分隔件119包括金屬。在封裝結構P1-4 /P1-5 /P1-6 /P1-7 /P1-8 中，分隔件400包括聚合物。在封裝結構P1-9 /P1-10 /P1-11 /P1-12 /P1-13 中，分隔部件包括由金屬所構成的分隔件119以及由聚合物所構成的分隔件400。
在一些實施例中，本發明實施例更提供疊層封裝元件1/2/3/4/5/6/7/8/9/10/11/12/13/14，其包括封裝結構P2 、封裝結構P1 /P1-1 /P1-2 /P1-3 /P1-4 /P1-5 /P1-6 /P1-7 /P1-8 /P1-9 /P1-10 /P1-11 /P1-12 /P1-13 以及電磁干擾層EMI，其中封裝結構P2 接合於且堆疊於封裝結構P1 /P1-1 /P1-2 /P1-3 /P1-4 /P1-5 /P1-6 /P1-7 /P1-8 /P1-9 /P1-10 /P1-11 /P1-12 /P1-13 上，電磁干擾層EMI覆蓋封裝結構P2 的頂面以及側面並電性連接至封裝結構P1 /P1-1 /P1-2 /P1-3 /P1-4 /P1-5 /P1-6 /P1-7 /P1-8 /P1-9 /P1-10 /P1-11 /P1-12 /P1-13 的重佈線層結構117的重佈線層106、110以及114中的至少一個。
基於上述，在本發明實施例的疊層封裝元件中，於重佈線層結構上方形成分隔件，且分隔件環繞封裝結構的接點。分隔件扮演著將疊層封裝元件與托盤分開的角色，所述托盤於EMI形成步驟期間固持住所述疊層封裝元件。以此方式，不會產生習知的EMI毛邊，且EMI遮蔽的排除區（KOZ）可為大幅減少。
根據本發明的一些實施例，一種封裝結構包括第一晶粒、重佈線層結構、多個UBM接墊、多個接點以及分隔件。重佈線層結構電性連接至第一晶粒。UBM接墊電性連接至重佈線層結構。接點電性連接至UBM接墊。分隔件位於重佈線層結構上方且環繞接點。
在上述封裝結構中，所述分隔件包括金屬、聚合物或其組合。
在上述封裝結構中，從最外面UBM接墊至所述分隔件的內邊界的距離為“d”，所述分隔件的寬度為“W”，且d與W的比率為約1:1至1:10。
在上述封裝結構中，從最外面UBM接墊至所述分隔件的內邊界的距離為“d”，所述分隔件的高度為“H”，且d與H的比率為約1:1至1:10。
在上述封裝結構中，從最外面UBM接墊至所述分隔件的內邊界的距離為“d”，從所述封裝結構的邊緣至所述分隔件的外邊界的距離為“D”，且d與D的比率為約1:0.1至1:5。
在上述封裝結構中，所述分隔件為環狀且環繞最外面接點。
在上述封裝結構中，所述封裝結構的邊緣具有階梯狀輪廓。
在上述封裝結構中，所述分隔件處於浮置電位。
根據本發明的一些替代性實施例，一種疊層封裝元件包括第一封裝結構、第二封裝結構以及電磁干擾層。第一封裝結構，具有第一側以及與所述第一側相對的第二側，且包括第一晶粒、重佈線層結構、多個接點以及分隔件。重佈線層結構電性連接至所述第一晶。多個接點電性連接至所述重佈線層結構且由所述第一側裸露出。分隔件位於所述第一封裝結構的所述第一側上，且位於所述接點側邊。第二封裝結構位於所述第一封裝結構的所述第二側上方。電磁干擾層覆蓋所述第二封裝結構的頂面以及側面，且電性連接至所述第一封裝結構的所述重佈線層結構。
在上述疊層封裝元件中，所述分隔件包括金屬、聚合物或其組合。
在上述疊層封裝元件中，所述第一封裝結構更包括位於所述重佈線層結構的頂面的多個UBM接墊，且所述多個接點連接至所述多個UBM接墊。
在上述疊層封裝元件中，從最外面UBM接墊至所述分隔件的內邊界的距離為“d”，所述分隔件的寬度為“W”，且d與W的比率為約1:1至1:10。
在上述疊層封裝元件中，從最外面UBM接墊至所述分隔件的內邊界的距離為“d”，所述分隔件的高度為“H”，且d與H的比率為約1:1至1:10。
在上述疊層封裝元件中，從最外面UBM接墊至所述分隔件的內邊界的距離為“d”，從所述第一封裝結構的邊緣至所述分隔件的外邊界的距離為“D”，且d與D的比率為約1:0.1至1:5。
在上述疊層封裝元件中，所述分隔件的外邊界對齊於所述第一封裝結構的邊緣。
在上述疊層封裝元件中，所述第一封裝結構的邊緣具有階梯狀輪廓。
根據本發明的另一些替代性實施例，一種封裝結構的形成方法包括以下步驟。於第一晶粒上方形成重佈線層結構，其中所述重佈線層結構電性連接至所述第一晶粒。形成多個UBM接墊以及第一分隔件，其中所述第一分隔件環繞所述UBM接墊，且所述多個UBM接墊電性連接至所述重佈線層結構。於所述多個UBM接墊上方形成多個接點。
在上述形成方法中，更包括於形成所述多個接點的步驟之後，於所述第一分隔件上形成第二分隔件。
在上述形成方法中，所述第一分隔件包括金屬，且所述第二分隔件包括聚合物。
在上述形成方法中，所述多個UBM接墊以及所述第一分隔件由相同光罩所定義。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更佳了解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
1~14‧‧‧疊層封裝元件
100、201‧‧‧晶粒
100a、203‧‧‧基底
100b‧‧‧接墊
100c‧‧‧鈍化層
100d‧‧‧接點
100e‧‧‧保護層
101‧‧‧介電層
102、209‧‧‧封裝體
104、108、112、116‧‧‧聚合物層
106、110、114‧‧‧重佈線層
117‧‧‧重佈線層結構
118‧‧‧凸點下金屬（UBM）接墊
119、400‧‧‧分隔件
120、214‧‧‧接點
205、211‧‧‧接合墊
207‧‧‧打線
300~308、500~510、600~610‧‧‧步驟
A‧‧‧區域
C‧‧‧載板
DB‧‧‧剝離層
EMI‧‧‧電磁干擾層
P1、P1-1~P1-13、P2‧‧‧封裝結構
T‧‧‧托盤
TIV‧‧‧積體扇出型穿孔
UF‧‧‧底膠層
圖1A至圖1F為根據一些實施例所繪示的疊層封裝元件的形成方法的剖面示意圖。 圖2為圖1B的簡化上視圖。 圖3為圖1E的區域A的放大圖。 圖4為根據一些實施例所繪示的疊層封裝元件的形成方法的流程圖。 圖5至圖7為根據一些實施例所繪示的疊層封裝元件的剖面示意圖。 圖8A至圖8F為根據其他實施例所繪示的疊層封裝元件的形成方法的剖面示意圖。 圖9為圖8B的簡化上視圖。 圖10為圖8E的區域A的放大圖。 圖11為根據其他實施例所繪示的疊層封裝元件的形成方法的流程圖。 圖12至圖15為根據其他實施例所繪示的疊層封裝元件的剖面示意圖。 圖16為根據又一些其他實施例所繪示的疊層封裝元件的形成方法的流程圖。 圖17至圖21為根據又一些其他實施例所繪示的疊層封裝元件的剖面示意圖。
1‧‧‧疊層封裝元件
100‧‧‧晶粒
100a‧‧‧基底
100b‧‧‧接墊
100c‧‧‧鈍化層
100d‧‧‧接點
100e‧‧‧保護層
101‧‧‧介電層
102‧‧‧封裝體
104、108、112、116‧‧‧聚合物層
106、110、114‧‧‧重佈線層
117‧‧‧重佈線層結構
118‧‧‧凸點下金屬(UBM)接墊
119‧‧‧分隔件
120、214‧‧‧接點
EMI‧‧‧電磁干擾層
P1、P2‧‧‧封裝結構
TIV‧‧‧積體扇出型穿孔
UF‧‧‧底膠層

Claims (1)

  1. 一種封裝結構，包括： 第一晶粒； 重佈線層結構，電性連接至所述第一晶粒； 多個凸點下金屬接墊，電性連接至所述重佈線層結構； 多個接點，電性連接至所述多個凸點下金屬接墊；以及 分隔件，位於所述重佈線層結構上方且環繞所述接點。
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