TWI710072B - 半導體裝置封裝體及其製造方法 - Google Patents

半導體裝置封裝體及其製造方法 Download PDF

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TWI710072B
TWI710072B TW108112074A TW108112074A TWI710072B TW I710072 B TWI710072 B TW I710072B TW 108112074 A TW108112074 A TW 108112074A TW 108112074 A TW108112074 A TW 108112074A TW I710072 B TWI710072 B TW I710072B
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primer layer
layer
package
primer
semiconductor device
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TW108112074A
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TW202002190A (zh
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陳又維
郭立中
施應慶
盧思維
林俊成
李隆華
黃冠育
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台灣積體電路製造股份有限公司
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Abstract

一種底膠結構及底膠結構的半導體裝置的製造方法。半導體裝置封裝體包括一封裝體，封裝體包括一積體電路晶片；一中介層，經由多個晶片連接器接合至積體電路晶片；以及一封膠層，圍繞積體電路晶片。半導體裝置封裝體更包括一封裝基板，經由多個導電連接器接合至中介層；一第一底膠層，位於封裝體與封裝基板之間，第一底膠層具有第一熱膨脹係數（CTE）；以及一第二底膠層，圍繞第一底膠層，第二底膠層具有小於第一熱膨脹係數的第二熱膨脹係數。

Description

半導體裝置封裝體及其製造方法
本發明實施例係關於一種半導體技術，且特別是關於一種半導體裝置封裝體及其製造方法。
半導體裝置係用於各種電子應用中，例如個人電腦、手機、數位相機及其他電子設備。半導體裝置的製造通常經由在半導體基底上依序沉積絕緣或介電層、導電層及半導體材料層，並使用微影製程圖案化各種材料層，以在其上形成電路部件及元件。
半導體工業透過不斷減小最小特徵部件尺寸繼續改善各種電子部件（例如，電晶體、二極體、電阻器、電容器等）的集積密度，這允許將更多元件集積於一給定區域。然而，隨著最小特徵部件尺寸的減小，也出現了應當解決的其他問題。
一種半導體裝置封裝體包括：一種半導體裝置封裝體包括：一封裝體，包括一積體電路晶片、經由多個晶片連接器接合至積體電路晶片的一中介層以及圍繞積體電路晶片的一封膠層；一封裝基底，經由多個導電連接器接合至中介層；一第一底膠層，位於封裝體與封裝基板之間，第一底膠層具有一第一熱膨脹係數；以及一第二底膠層，圍繞第一底膠層，第二底膠層具有小於第一熱膨脹係數的一第二熱膨脹係數。
一種半導體裝置封裝體之製造方法包括：將一晶片貼附至一中介層的一第一表面；以一封膠層封裝晶片；形成多個導電連接器於中介層的一第二表面，第二表面相對於第一表面；經由導電連接器將中介層接合至一封裝基底；沉積一第一底膠層於中介層與封裝基底之間，並圍繞導電連接器；以及沉積一第二底膠層以圍繞第一底膠層，第二底膠層具有比第一底膠層低的熱膨脹係數。
一種半導體裝置封裝體包括：一第一封裝體，包括：一第一積體電路晶片、圍繞第一積體電路晶片的一封膠層以及位於封膠層及第一積體電路晶片上的一重佈層；多個功能連接器；一第二封裝體，經由多個功能連接器接合至第一封裝體，其中功能連接器及重佈層電性連接第二封裝體的一第二積體電路晶片至第一積體電路晶片；一第一底膠層，位於第一封裝體與第二封裝體之間，第一底膠層圍繞功能連接器；以及一第二底膠層，圍繞第一底膠層，第二底膠層具有不同於第一底膠層的材料組成，第二底膠層的最頂部區域範圍位於第一底膠層的最上表面的上方。
以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵部件。而以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化本揭露內容。當然，這些僅為範例說明並非用以限定本發明。舉例來說，若是以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方，即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦包含了尚可將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。另外，本揭露內容在各個不同範例中會重複標號及/或文字。重複是為了達到簡化及明確目的，而非自行指定所探討的各個不同實施例及/或配置之間的關係。
再者，在空間上的相關用語，例如＂下方＂、＂之下＂、＂下＂、＂上方＂、＂上＂等等在此處係用以容易表達出本說明書中所繪示的圖式中元件或特徵部件與另外的元件或特徵部件的關係。這些空間上的相關用語除了涵蓋圖式所繪示的方位外，還涵蓋裝置於使用或操作中的不同方位。此裝置可具有不同方位（旋轉90度或其他方位）且此處所使用的空間上的相關符號同樣有相應的解釋。
本文討論的實施例係關於底膠結構及用於各種半導體封裝體的底膠結構的製造方法。在一些實施例中，底膠結構應用於裝置封裝體，裝置封裝體包括接合至中介層（interposer）的一個或多個半導體晶片以及接合至中介層中與一個或多個半導體晶片相對的一側的封裝基底。裝置封裝體可稱作基底上晶圓上晶片（chip-on-wafer-on-substrate, CoWoS）超薄夾層（ultra-thin sandwich, UTS）封裝體。在其他實施例中，底膠結構應用於封裝結構（例如，封裝體上封裝體（package on package, PoP）結構），其包括一第一封裝部件及一第二封裝部件。第二封裝部件可為記憶體封裝體（例如，具有一個或多個動態隨機存取記憶體（dynamic random access memory, DRAM）晶片），其使用功能連接器而物理性及電性耦接至第一封裝體（例如，整合型扇出（integrated fan-out, InFO）封裝，其具有邏輯晶片及重分佈結構）。
底膠結構可包括一第一底膠層及圍繞第一底膠層的一第二底膠層。第二底膠層可具有比第一底膠層更低的熱膨脹係數（oefficient of thermal expansion, CTE）。與其中底膠結構僅包括單一底膠材料層的實施例相比，包括第一底膠層和第二底膠層的實施例可改善可靠度。舉例來說，第一底膠層及第二底膠層可透過減少封裝晶片的邊角處的高應力來防止底膠破裂、底膠離層及凸塊破裂。所述封裝晶片可為超大型晶片（例如，其面積大於1000mm2 ）。包括第一底膠層及第二底膠層可減少晶片邊角處的應力，以增加可靠度。
第1至9B圖是根據一些實施例的在形成半導體裝置900的製程期間的中間步驟的各種剖面示意圖在第1至5圖中，透過將各種積體電路晶片接合至晶圓102來形成第一裝置封裝體100。在一實施例中，第一裝置封裝體100為晶圓上晶片（chip-on-wafer, CoW）封裝，然而應理解該實施例也可應用於其他3DIC封裝。第5繪示出了所得到的第一裝置封裝體100。在第6及7圖中，透過將第一裝置封裝體100組裝到一基底上來形成第二裝置封裝體700。在一實施例中，第二裝置封裝體700為基底上晶圓上晶片（CoWoS）封裝，然而應當理解該實施例可應用於其他3DIC封裝。第9、9A及9B圖繪示出了實現所得到裝置封裝體700的半導體裝置900。
晶圓102可具有形成於其中的各種裝置。具體來說，可於晶圓102內形成中介層，積體電路裝置等，其可包括多個裝置區域100A及100B（於後續步驟中單體化而形成第一裝置封裝體100）。
在一些實施例中，中介層形成於晶圓102內。中介層具有內連接結構，用於電連接積體電路晶片內的主動裝置（未繪示）以形成功能電路。在上述實施例中，晶圓102包括具有前表面（例如，第1圖中面朝上的表面）及背表面（例如，第1圖中面朝下的表面）的半導體基底。內連接結構形成於半導體基底的背表面上。通孔電極（未明確示出）形成於半導體基底內且從內連接結構延伸至半導體基底的前表面。可透過雙鑲嵌製程在半導體基底上的內連接結構中形成金屬線及通孔（via）。金屬線及通孔可以電性連接至通孔電極。中介層可具有（或不具有）諸如電晶體及二極體的主動裝置，且可具有（或不具有）諸如電阻器、電感器、電容器等裝置。
儘管是在具有中介層形成其中的晶圓102的背景下討論了本文所示的實施例，然而應可理解可於晶圓102內形成其他類型的裝置。舉例來說，積體電路裝置（例如，邏輯裝置）可形成於晶圓102內。在上述實施例中，晶圓102包括一半導體基底，其內形成有主動及/或被動裝置。半導體基底可為矽基底、摻雜或未摻雜的基底、或為絕緣層上覆矽（silicon-on-insulator, SOI）主動層的基底。半導體基底可包括其他半導體材料，例如鍺、化合物半導體（包括：碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦）、合金半導體（包括，SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP、或其組合。也可使用其他基底，例如多層型或漸變型基底。諸如電晶體、二極體、電容器、電阻器等的裝置可形成於半導體基底內及/或上方，且可以透過內連接結構（例如，可為形成於半導體基底上一個或多個介電層內的金屬化圖案）進行內連接，以形成積體電路。
如第1圖所示，晶片堆疊106A及106B利用晶片連接器104貼附於晶圓102。在一實施例中，第一晶片堆疊106A（例如，圖形處理單元（graphics processing unit, GPU））及第二晶片堆疊106B（例如，高帶寬記憶體（high bandwidth memory, HBM）可放置於晶圓102的每個裝置區域上。晶片堆疊106A及106B可使用拾取及放置（pick-and-place）工具而貼附至晶圓102。晶片連接器104可由導電材料形成，例如焊料、銅、鋁、金、鎳、銀、鈀、錫等、或其組合。在一些實施例中，晶片連接器104的製作一開始係經由諸如蒸鍍、電鍍、印刷、焊料轉移、球放置等方法而形成焊料層。一旦形成了一層焊料於結構上就可進行回流，以將晶片連接器104成形為所需的凸塊形狀。晶片連接器104於晶圓102上對應的連接器與晶片堆疊106A及106B之間形成接點，並將晶圓102電性連接至晶片堆疊106A及106B。
晶片堆疊106A及106B可各自具有單一功能（例如，邏輯裝置，記憶體晶片等），或可具有多重功能（例如，系統晶片（system on chip, SoC））。在特定實施例中，第一晶片堆疊106A是處理器而第二晶片堆疊106B是記憶體模組。更具體來說，第一晶片堆疊106A可為中央處理單元（central processing unit, CPU）、GPU、特殊應用積體電路（application-specific integrated circuit, ASIC）等處理器。在一些實施例中，第二晶片堆疊106B可為記憶體裝置，諸如動態隨機存取存儲器（DRAM）晶片、靜態隨機存取存儲器（SRAM）晶片，混合記憶體立方體（hybrid memory cube, HMC）模組等。
在第2圖中，底膠層202可形成於晶片堆疊106A及106B與晶圓102之間，且圍繞晶片連接器104。可在貼附晶片堆疊106A及106B之後透過毛細管流動製程形成底膠層202，或者可在貼附晶片堆疊106A及106B之前，透過合適的沉積方法形成底膠層202。底膠層202可透過後續所述兩段製程形成（參考第8、9、16及17圖），或者透過另一合適的製程形成。
在第3圖中，封膠層302形成於各個部件上。封膠層302可為模塑材料（molding compound）、環氧樹脂等，且可透過壓縮模塑成型、傳遞模塑成型等而形成。如第3圖所示，封膠層302可形成於晶圓102上方而掩埋或覆蓋晶片堆疊106A及106B，然後固化封膠層302。
在第4圖中，導電連接器402形成於晶圓102的背側上。在形成導電連接器402之前，可薄化晶圓102的背側。可透過化學機械研磨（chemical-mechanical polish, CMP）製程、研磨製程等來進行薄化，以實現晶圓102所需厚度及/或露出導電特徵部件（例如，通孔電極）。導電連接器402電性連接至晶圓102的特徵部件（例如，邏輯裝置、中介層等），且可為球柵陣列（ball grid array, BGA）連接器、焊球、金屬柱體，控制塌陷高度晶片連接（controlled collapse chip connection, C4）凸塊、微凸塊，化學鍍鎳鈀-浸金（electroless nickel-electroless palladium-immersion gold, ENEPIG）技術形成的凸塊等。在一些實施例中，導電連接器402一開始係經由諸如蒸鍍、電鍍、印刷、焊料轉移、球放置等方法而形成焊料層。一旦在結構上形成了一層焊料就可進行回流，以將材料成形為所需的凸塊形狀。在形成導電連接器402之後，可將晶圓102放置在膠帶404上，以進行後續製程步驟。
在第5圖中，薄化封膠層302以露出晶片堆疊106A及106B的上表面。可透過畫瘸機械研磨（CMP）製程、研磨製程等來進行薄化。在薄化之後，封膠層302及晶片堆疊106A及106B的上表面是切齊的。在薄化封膠層302之後，晶圓102及封膠層302經由單體分割（singulation）製程而單體化，因而形成第一裝置封裝體100，如第6圖所示。
第6圖繪示出了在進行單體分割製程之後得到的第一裝置封裝體100。如單體分割製程的結果所示，晶圓102單體化成為中介層602，其中每個第一裝置封裝體100具有中介層602。可在晶圓102位於膠帶404上的同時進行單體化製程。單體分割製程係沿相鄰裝置區域之間的切割道進行。舉例來說，如第5圖所示，第一裝置封裝體100可沿著裝置區域100A及100​​B之間的虛線而單體化。在一些實施例中，單體分割製程包括切割工藝、雷射製程或其組合。
如單體分割製程的結果所示，中介層602及封膠層302的邊緣是連續的。換句話說，中介層602的外側壁具有與封膠層302的外側壁相同的寬度。
在第7圖中，經由將第一裝置封裝體100組裝到封裝基底702來形成第二裝置封裝體700。封裝基底702可由諸如矽、鍺、鑽石等半導體材料形成。或者，也可使用諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦等化合物材料，或其組合等。另外，封裝基底702可為SOI基底。通常，SOI基底包括半導體材料層，例如磊晶矽、鍺、矽鍺、SOI，絕緣體上覆矽鍺（SiGe-on-insulator, SGOI）或其組合。在另一實施例中，封裝基底702為絕緣芯，例如玻璃纖維增強樹脂芯（fiberglass reinforced resin core）。一種示例性芯材料為玻璃纖維樹脂，例如FR4。芯材料的替代物包括雙馬來醯亞胺-三嗪（bismaleimide-triazine, BT）樹脂，或者為其他印刷電路板（PCB）材料或膜層。諸如Ajinomoto積層膜（Ajinomoto build-up film, ABF）或其他層壓板的積層膜可用於封裝基板702。
封裝基底702可包括主動及被動裝置（未繪示）。如所屬技術領域中具有通常知識者可理解可使用諸如電晶體、電容器、電阻器、其組合等的各種裝置來產生對於第二裝置封裝體700設計的結構與功能要求。可使用任何合適的方法形成裝置。
封裝基底702也可包括金屬化層及通孔（未繪示）以及位於金屬化層及通孔上方的接合墊704。金屬化層可形成於主動及被動裝置上，並設計成連接各種裝置，以形成功能電路。金屬化層可由交替的介電層（例如，低k值介電材料）與導電材料層（例如，銅）所形成，其中通孔內連接導電材料層，且金屬化層可透過任何合適的製程（例如沉積製程、鑲嵌製程、雙鑲嵌製程等）形成。在一些實施例中，封裝基底702實質上沒有主動及被動裝置。
在一些實施例中，回流導電連接器402，以將第一裝置封裝體100貼附至接合墊704，使中介層602接合至封裝基底702。導電連接器402電性及/或物理性耦接封裝基底 702（包括封裝基底702內的金屬化層）至第二裝置封裝體700。在一些實施例中，被動裝置（例如，表面黏著裝置（surface mount device, SMD），未繪示）在組裝於封裝基底702上之前，可貼附至第二裝置封裝體700（例如，接合至接合墊704）。在上述實施例中，被動裝置可與導電連接器402接合至第二裝置封裝體700的同一表面上。
在第8圖中，第一底膠層802形成於第一裝置封裝體100與第二裝置封裝體700之間，圍繞導電連接器402。第一底膠層802可在貼附第一裝置封裝體100之後透過毛細管流動製程形成，或者在貼附第一裝置封裝體100之前，透過合適的沉積方法形成。在透過毛細管流動製程形成第一底膠層802的實施例中，可在第一裝置封裝體100的邊角處沉積一定量的第一底膠材料。然後，加熱第一裝置封裝體100與第二裝置封裝體700，使第一底膠材料產生流動。第一底膠材料經由毛細管作用在第一裝置封裝體100與第二裝置封裝體700之間流動。在一些實施例中，可透過在沉積第一底膠材料之前，將表面暴露於電漿來活化第一裝置封裝體100及第二裝置封裝體700的表面，以增加表面的潤濕性並改善第一個底膠材料的毛細管作用。可沉積有限量的第一底膠材料以形成第一底膠層802，使第一底膠層802形成於限定的區域中。舉例來說，可沉積有限量的第一底膠材料，使第一底膠層的最頂部區域範圍設置於第一裝置封裝體100的最下表面下方。第一底膠層802的外圍與第一裝置封裝體100的外圍之間的距離D1可小於約2mm，小於約2.5mm，或小於約3mm。如第8圖所示，第一底膠層802的側壁可以是傾斜或漸細形的。如第8圖進一步所示，第一底膠層802的橫向外圍可延伸超出第一裝置封裝體100的橫向外圍。在一些實施例中，在剖面視圖中第一底膠層802的側壁可為彎曲的（未個別圖示說明）。
在其他實施例中，如第8A圖所示，第一底膠層802a的外圍的部分可設置於第一裝置封裝體100的外圍內。舉例來說，第一底膠層802a的最下表面的外圍與第一裝置封裝體100的外圍之間的距離D2可介於約100μm與200μm之間，例如約為150μm。在一些實施例中，第一底膠層802a的側壁可以是漸細的或傾斜形的。如第8A圖所示，在剖面視圖中第一底膠層802a的側壁可為彎曲的。在更進一步的實施例中，第一底膠層802可具有實質上垂直於封裝基底702的主表面的側壁（未個別圖示說明）。第一底膠層802的側壁可切齊於第一裝置封裝體100的側壁。
第一底膠層802可為任何可接受的材料，例如聚合物、環氧樹脂、模塑底膠材料等。根據至少一個實施例，第一底膠層802可由包括矽填料的環氧樹脂材料形成。更具體來說，第一底膠層802可由具有矽的重量百分比介於約50%與約60%之間的環氧樹脂材料形成，例如約60%。第一底膠層802可具有介於約20ppm/ºC與約30ppm/ºC之間的熱膨脹係數（CTE），例如約為22ppm/ºC。
在第9圖中，形成圍繞第一底膠層802的一第二底膠層902，以形成半導體裝置900。形成的第二底膠層902也可圍繞第一裝置封裝體100的至少一部分。儘管未個別圖示說明，形成的第二底膠層902可圍繞封膠層302的至少一部分。如第9圖所示，第二底膠層902可從封裝基底702的表面延伸至切齊中介層602的上表面的點。在一些實施例中，第二底膠層902的最頂部區域範圍可位於中介層602的上表面上方，或者位於中介層602的上表面下方。第二底膠層902可沿著中介層602的邊緣形成，以密封中介層602的邊緣並降減少中介層602發生破裂。第二底膠層902可完全包圍第一底膠層802的外圍。第二底膠層902的最頂部區域範圍可位於第一底膠層802的最頂部表面上方，第二底膠層902的製作可透過於第一底膠層802外圍沉積一定量的第二底膠材料並加熱第一裝置封裝體100及第二裝置封裝體700，以使包圍第一底膠層802的第二底膠材料產生流動。第一底膠層902外圍與第一裝置封裝體100外圍之間的距離D3可小於約2mm，小於約2.5mm，或小於約3mm。如第9圖所示，第二底膠層902的側壁可以是傾斜或漸細形的。
在一些實施例中，如第9A圖所示的實施例，第二底膠層902a可具有傾斜或漸細形側壁，其在剖面視圖中為彎曲的。儘管未個別圖示說明，然而形成的第二底膠層902a可圍繞封膠層302的至少一部分。第二底膠層902a的外圍與第一裝置封裝體100的外圍之間的距離D4可介於約2mm與3mm之間，例如約為2.5mm。
第二底膠層902可為任何可接受的材料，例如聚合物、環氧樹脂、模塑底膠材料等。第二底膠層902可由與第一底膠層802不同的材料形成，或者第二底膠層902可由具有與第一底膠層802相同的組成而不同的比例的材料形成。舉例來說，在一實施例中，第一底膠層802由包括矽填料的環氧樹脂材料形成。第二底膠層902可由包括矽填料的環氧樹脂材料形成，其矽填料的矽濃度高於第一底膠層802的矽填料。更具體來說，第二底膠層902可由矽的重量百分比介於約70%與約85%之間的環氧樹脂材料形成，例如約80%或85%。在一些實施例中，第一底膠層802的環氧樹脂材料內的矽填料可具有與第二底膠層902的環氧樹脂材料內的902不同的尺寸。
第二底膠層902可具有小於約25ppm/ºC的熱膨脹係數（CTE），小於約20ppm/ºC或小於約10ppm/ºC，例如約為8ppm/ºC、9ppm/ºC、11ppm/ºC、22ppm/ºC或24ppm/ºC。因此，第二底膠層902的熱膨脹係數（CTE）可小於第一底膠層802的熱膨脹係數（CTE）約18ppm/ºC、約17ppm/ºC或約11ppm/ºC。第二底膠層902的熱膨脹係數（CTE）也可與封裝基底702的熱膨脹係數（CTE）匹配。舉例來說，第二底膠層902的熱膨脹係數（CTE）可介於第一底膠層802的熱膨脹係數（CTE）與封裝基底702的熱膨脹係數（CTE）之間。第一底膠層802與第二底膠層902的熱膨脹係數（CTE）的比率可介於約2與4之間，例如約為3.7、2.6或2。第一底膠層802與第二底膠層902的熱膨脹係數（CTE）的比率大於及小於上述範圍可能由於第一底膠層802與第二底膠層902之間的熱膨脹係數（CTE）不匹配或者由於第二底膠層902與封裝基底702之間的熱膨脹係數（CTE）不匹配而導致底膠層的破裂。
第二底膠層902可具有介於約8與約15之間的彈性模數，例如約為11.0 GPa、9.7 GPa或11.5 GPa。第一底膠層802可具有與第二底部填充膠902的彈性模數類似或相同的彈性模數。
在形成第一底膠層802與第二底膠層902之後，固化第一底膠層802與第二底膠層902。第一底膠層802與第二底膠層902可以在室溫下或經由加熱或紫外線（ultra-violet, UV)）而固化。 在一些實施例中，第一底膠層802可在形成第二底膠層902之前固化，或者第一底膠層802與第二底膠層902可同時固化。
與第一底膠層802相比，第二底膠層902具有不良的流動性。舉例來說，第二底膠層902具有介於約55 Pa·s與70 Pa·s之間的黏度，例如約為65 Pa·s。而第一底膠層802具有介於約100 Pa·s與200 Pa·s之間的黏度，例如約為150 Pa·s。如此，第一底膠層802可於第一裝置封裝體100與第二裝置封裝體700之間流動，因而完全填充空間並包圍導電連接器402。
此外，半導體裝置900於半導體裝置900的邊角處受到高應力/應變。第二底膠層902可於半導體裝置900的邊角處具有比第一底膠層802更少的應變能量。例如，第二底膠層902可具有約1 μJ至約3 μJ之間的角應變能量，例如約為2.18 μJ或1.68 μJ。角應變能量值高於這些值會將底膠層破裂風險增加至不可接受的程度 。第一底膠層802可具有介於約4 μJ與約6 μJ之間的角應變能量，例如約為5.3 μJ或5.08 μJ。因此，第二底膠層902的角應變能量可小於第一底膠層802的角應變能量介於約1 μJ與約5 μJ之間，例如約為1 μJ、2 μJ或4 μJ。增加的角應變能量可能導致在底膠層中更早出現裂縫。因此，包括具有比第一底膠層802更低的角應變能量的第二底膠層902降低半導體裝置900的角應變能量並且降低底膠層中開裂的可能性。因此，具有第一底膠層802及第二底膠層902兩者的半導體裝置900可防止凸塊破裂、底膠層破裂及離層，同時仍然允許底膠層流動於且實質上填充於第一裝置封裝體100與第二裝置封裝體700之間的區域。如此一來，半導體裝置900的整體結構更加穩固。
在更進一步的實施例中，例如第9B圖所示的實施例，環形體910及/或蓋板912可接合至封裝基板702。蓋板912可經由熱界面材料（thermal interface material, TIM）918直接貼附至第一裝置封裝100，且蓋板912可經由第一黏著層916貼附至環形體910上。環形體910可經由第二黏著層914貼附至封裝基板702。環形體910可支撐蓋板912，且 將蓋板912與封裝基板702隔開以容納第一裝置封裝100。在一些實施例中，可以省略環形體910且可將蓋板912直接貼附至封裝基板702。
蓋板912可由金屬形成，諸如銅（Cu）、鎳（Ni）、鍍鎳銅、鋁（Al）、鋁合金等。環形體910可由金屬形成，諸如銅（Cu）、鎳（Ni）、鍍鎳銅、鋁（Al）、鋁合金等。第一黏著層916及第二黏著層914可由黏著材料形成，例如矽氧聚合物（silicon）等。熱界面材料（TIM）918可由矽氧聚合物（silicon）（包括矽、碳、氫、氧且有時為其他元素的聚合物）、氧化鋁（Al2 O3 ）或氧化鋅（ZnO2 ）與矽氧聚合物（[R2SiO]n）混合等形成。蓋板912、環形體910及熱界面材料（TIM）918可由具有高導熱率的材料形成。如此一來，蓋板912、環形體910及熱界面材料（TIM）918可用於消散第一裝置封裝體100內產生的熱至外部環境。此外，蓋板912及環形體910可為第一裝置封裝體100提供保護。
第10至17圖係繪示出根據一些實施例之半導體裝置1700中間製造階段的剖面示意圖。第10至14圖係繪示出了根據一些實施例之第一封裝體1400中間製造階段的剖面示意圖。第一封裝體1400也可稱為整合型扇出（InFO）封裝。在第15至17圖中，第二封裝體1500組裝至第一封裝體1400且底部進行填充，以形成半導體裝置1700。
第10圖繪示出一承載基底1002、形成於承載基底1002上的一釋放層1004、形成於釋放層1004上的一介電層1006以及形成於介電層1006上的一金屬化圖案1008（有時稱為重佈層或重佈線）。第10圖繪示出分別用於形成第一封裝體和第二封裝體第一封裝區域1000A及第二封裝區域1000B。
承載基底1002可為玻璃承載基底或陶瓷承載基底等。承載基底1002可為晶片，因而可同時於承載基底1002上形成多個封裝體。釋放層1004可由聚合物基材料形成，其可與承載基底1002一同自後續步驟中形成的上方結構移除。在一些實施例中，釋放層1004為環氧樹脂基熱釋放材料，其在加熱時失去其黏性，例如光 - 熱 - 轉換（light-to-heat-conversion, LTHC）釋放塗層。在其他實施例中，釋放層1004可為紫外線（UV）膠，當暴露於紫外線（UV）時其失去其黏性。釋放層1004可為液體並固化、可為層壓至承載基底1002上的層壓膜、或者可為類似物。釋放層1004的上表面可為水平的，且可具有高度的共平面性。
在一些實施例中，介電層1006由聚合物形成，例如聚苯並噁唑（polybenzoxazole, PBO）、聚醯亞胺（polyimide）、苯並環丁烯（benzocyclobutene, BCB）等。在其他實施例中，介電層1006由氮化物（例如，氮化矽）、氧化矽（例如，磷矽酸鹽玻璃（phosphosilicate glass, PSG）、硼矽酸鹽玻璃（borosilicate glass, BSG）、硼摻雜磷矽酸鹽玻璃（boron-doped phosphosilicate glass, BPSG）等等形成。介電層1006可透過任何可接受的沉積製程形成，例如旋塗、化學氣相沉積（CVD）、層壓等或其組合。
金屬化圖案1008形成於介電層1006上。形成金屬化圖案1008的一示例中，形成一種子層（未個別繪示出）於介電層1006上。在一些實施例中，種子層為金屬層，可為單層或複合層（包括由不同材料形成的多個次層（sub-layer））。在一些實施例中，種子層包括鈦層及鈦層上的銅層。可使用例如物理氣相沉積（PVD）製程等形成種子層。然後形成光阻於種子層上並圖案化種子層。可透過旋塗等製程形成光阻，且可對光阻進行曝光以進行圖案化。光阻的圖案對應於金屬化圖案1008。圖案化後形成穿過光阻的開口以露出種子層。形成導電材料於光阻的開口內及種子層的露出部分上。導電材料可透過電鍍形成，例如電鍍或無電鍍等。導電材料可包括金屬，例如銅、鈦、鎢、鋁等。然後，去除光阻及上方未形成導電材料的種子層部分。可透過可接受的灰化或剝離製程去除光阻，例如使用氧電漿等。一旦去除光阻，去除種子層的露出部分，例如透過使用可接受的蝕刻製程（例如透過濕法或乾法蝕刻製程）。種子層及導電材料的餘留部分形成了金屬化圖案1008。
在第11圖中，形成介電層1102於金屬化圖案1008上、形成通孔電極1104、經由黏著層1106將積體電路晶片1108貼附至介電層1102以及形成封膠層1110圍繞各個部件。在一些實施例中，介電層1102由聚合物形成，聚合物可為光敏材料，例如聚苯並噁唑（PBO）、聚醯亞胺、苯並環丁烯（BCB），其可使用微影光罩進行圖案化。在其他實施例中，介電層1102由由氮化物（例如，氮化矽）、氧化矽（例如，磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、硼摻雜磷矽酸鹽玻璃（BPSG）等等形成。介電層1102可透過旋塗、層壓、化學氣相沉積（CVD）等製程或其組合形成。然後圖案化介電層1102以形成開口而露出金屬化圖案1008的部分。圖案化可透過可接受的製程來進行，例如在介電層為光敏材料時透過對介電層1102進行曝光，或透過使用異向性蝕刻來進行蝕刻。
介電層1006及1102以及金屬化圖案1008可稱為背側重佈結構1112。如圖所示，背側重佈結構1112包括兩個介電層1006及1102以及一個金屬化圖案1008。在其他實施例中，背側重佈結構1112可包括任何數量的介電層、金屬化圖案及通孔電極。透過重複形成金屬化圖案1008及介電層1102的製程，可在背側重佈結構1112內形成一或多個額外的金屬化圖案及介電層。可於形成金屬化圖案期間，透過形成種子層及金屬化圖案的導電材料於下方的介電層的開口內而形成通孔電極。 因此，通孔電極可內連接並電性耦接各個金屬化圖案。
如圖所示，可透過形成種子層（未個別繪示出）於背側重佈結構1112（例如，介電層1102及金屬化圖案1008的露出部分）上來形成通孔電極1104。在一些實施例中，種子層為金屬層，其可為單層或複合層（包括由不同材料形成的多個次層）。在一些實施例中，種子層包括鈦層及鈦層上的銅層。可使用例如物理氣相沉積（PVD）製程等形成種子層。形成並圖案化光阻於種子層上。可透過旋塗製程等形成光阻，且可對光阻進行曝光以進行圖案化。光阻的圖案對應於通孔電極。圖案化形成穿過光阻的開口以露出種子層。形成導電材料於光阻的開口內及種子層的露出部分上。導電材料可透過電鍍形成，例如電鍍或無電鍍等。導電材料可包括金屬，例如銅、鈦、鎢、鋁等。然後，去除光阻及上方未形成導電材料的種子層部分。可透過可接受的灰化或剝離製程去除光阻，例如使用氧電漿等。一旦去除光阻，去除種子層的露出部分，例如透過使用可接受的蝕刻製程（例如透過濕法或乾法蝕刻製程）。種子層及導電材料的餘留部分形成了通孔電極1104。
然後可透過黏著層1106將積體電路晶片1108貼附至介電層1102。如第11圖所示，將單個積體電路晶片1108貼附至第一封裝區域1000A及第二封裝區域1000B中的每一者。然而，在其他實施例中，可在每個區域中貼附更多或更少的積體電路晶片1108。舉例來說，在一實施例中，可在每個區域中貼附兩個或更多個積體電路晶片1108。積體電路晶片1108可為邏輯晶片（例如，中央處理單元，微控制器等）、記憶體晶片（例如，動態隨機存取記憶體（DRAM）晶片、靜態隨機存取記憶體（SRAM）晶片等）、電源管理晶片（例如，電源管理集成電路（power management integrated circuit, PMIC）晶片）、射頻（radio frequency RF）晶片、感測晶片、微機電系統（micro-electro-mechanical-system, MEMS）晶片、信號處理晶片（例如，數位信號處理（digital signal processing, DSP）晶片）、前端晶片（例如，類比前端（analog front-end, AFE）晶片）等或其組合。而且，在一些實施例中，積體電路晶片1108可具有不同的尺寸（例如，不同的高度及/或表面區域），且在其他實施例中，積體電路晶片1108可具有相同的尺寸（例如，相同的高度及/或表面區域）。
黏著層1106位於積體電路晶片1108的背側上，且將積體電路晶片1108貼附至背側重佈結構1112，例如圖中的介電層1102。黏著層1106可為任何合適的黏著劑、環氧樹脂，晶片貼附膜（die attach film, DAF）等。黏著層1106可提供於積體電路晶片1108的背側，例如提供於相應半導體晶片的背側，或者可提供於積體電路晶片1108的承載基底的表面上。積體電路晶片1108可透過黏著層1106使用拾取與放置工具貼附至介電層1102。
然後可形成封膠層1110於各個部件上。封膠層1110可為模塑材料、環氧樹脂等，且可以透過壓縮模塑、傳遞模塑等來進行。在固化之後，封膠層1110可進行研磨製程以露出通孔電極1104及積體電路晶片1108的上表面。在進行研磨製程之後，通孔電極1104、積體電路晶片1108及封膠層1110的上表面為共平面。 在一些實施例中，可省略研磨製程，舉例來說，若通孔電極1104及積體電路晶片1108的上表面已經露出。
在第12圖中，形成前側重佈結構1202。前側重佈結構1202包括各種介電層及金屬化圖案（未個別標記），其有時稱作重佈層或重佈線。介電層可以由聚合物形成，聚合物可為光敏材料，例如聚苯並噁唑（PBO）、聚醯亞胺、苯並環丁烯（BCB），其可使用微影光罩進行圖案化。在其他實施例中，介電層1102由由氮化物（例如，氮化矽）、氧化矽（例如，磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG），硼摻雜磷矽酸鹽玻璃（BPSG））等等形成。介電層1102可透過旋塗、層壓、化學氣相沉積（CVD）等製程或其組合形成。然後圖案化介電層。圖案化在每個介電層內形成開口，以露出部分通孔電極1104及積體電路晶片1108的上表面或下方的金屬化圖案。圖案化可透過可接受的製程（例如在介電層為光敏材料時透過對介電層進行曝光，或透過使用異向性蝕刻來進行蝕刻）。若介電層為光敏材料，則可在曝光後對介電層進行顯影。
在形成每個介電層之後，可形成金屬化圖案於對應的介電層上。在形成金屬化圖案的一示例中，形成一種子層（未個別繪示出）於介電層上且穿過介電層的開口。在一些實施例中，種子層為金屬層，其可為單層或複合層（包括由不同材料形成的多個次層）。在一些實施例中，種子層包括鈦層及鈦層上的銅層。可使用例如物理氣相沉積（PVD）製程等形成種子層。然後形成光阻於種子層上並圖案化種子層。可透過旋塗等製程形成光阻，且可對光阻進行曝光以進行圖案化。光阻圖案對應於金屬化圖案。圖案化形成穿過光阻的開口以露出種子層。在光阻的開口內及種子層的露出部分上形成導電材料。導電材料可透過電鍍形成，例如電鍍或無電鍍等。導電材料可包括金屬，例如銅、鈦、鎢、鋁等。然後，去除光阻及上方未形成導電材料的種子層部分。可透過可接受的灰化或剝離製程去除光阻，例如使用氧電漿等。一旦去除光阻，去除種子層的露出部分，例如透過使用可接受的蝕刻製程（例如透過濕法或乾法蝕刻製程）。種子層及導電材料的餘留部分形成了金屬化圖案及通孔電極。通孔電極形成於穿過介電層的開口內，例如通孔電極1104、積體電路晶片1108的上表面及/或下方的金屬化圖案。
所示的前側重佈結構1202為一示例。可以在前側重佈結構1202內形成更多或更少的介電層及金屬化圖案。若要形成更少的介電層及金屬化圖案，則可省略上述所討論的步驟及製程。若要形成更多的介電層及金屬化圖案，則可重複上述所討論的步驟及製程。所屬技術領域中具有通常知識者將容易理解需省略或重複哪些步驟及製程。
在第13圖中，形成接墊1304於前側重佈結構1202的外側上、形成導電連接器1302於接墊1304上、剝除（de-bonded）承載基底1002，然後翻轉結構並放置於膠帶層1306上。
接墊1304用於耦接至導電連接器1302，且可稱為凸塊下金屬層（under bump metallurgy, UBM）1304。在所示實施例中，接墊1304穿過開口（其穿過第12圖的最頂部介電層）至第12圖的最頂部金屬化圖案。在形成接墊1304的一示例中，形成種子層（未個別繪示出）於最頂部的介電層上。在一些實施例中，種子層為金屬層，其可為單層或複合層（包括由不同材料形成的多個次層）。在一些實施例中，種子層包括鈦層及鈦層上的銅層。可使用例如物理氣相沉積（PVD）製程等形成種子層。然後形成光阻於種子層上並圖案化種子層。可透過旋塗等製程形成光阻，且可對光阻進行曝光以進行圖案化。光阻圖案對應於接墊1304。圖案化形成穿過光阻的開口以露出種子層。在光阻的開口內及種子層的露出部分上形成導電材料。導電材料可透過電鍍形成，例如電鍍或無電鍍等。導電材料可包括金屬，例如銅、鈦、鎢、鋁等。然後，去除光阻及上方未形成導電材料的種子層部分。可透過可接受的灰化或剝離製程去除光阻，例如使用氧電漿等。一旦去除光阻，去除種子層的露出部分，例如透過使用可接受的蝕刻製程（例如透過濕法或乾法蝕刻製程）。種子層及導電材料的餘留部分形成了接墊1304。在一實施例中，接墊1304以不同方式形成，可使用更多的光阻及圖案化步驟。
導電連接器1302形成於凸塊下金屬層（UBM）1304上。導電連接器1302可為球柵陣列（BGA）連接器、焊球、金屬柱體，控制塌陷高度晶片連接（C4）凸塊、微凸塊，化學鍍鎳鈀-浸金（ENEPIG）技術形成的凸塊等。導電連接器1302可包括導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合。在一些實施例中，導電連接器1302一開始係經由諸如蒸鍍、電鍍、印刷、焊料轉移、球放置等方法而形成焊料層。一旦在結構上形成了一層焊料就可進行回流，以將材料成形為所需的凸塊形狀。在另一實施例中，導電連接器1302為透過濺射、印刷、電鍍、無電鍍、化學氣相沉積（CVD）等製程形成的金屬柱（例如銅柱）。金屬柱可為無焊料的，且具有實質上垂直的側壁。在一些實施例中，形成金屬蓋層（未繪示）於導電連接器1302的頂部上。金屬蓋層可包括鎳、錫、錫鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合，且可透過電鍍製程形成。
然後，剝除承載基底，以使承載基底1002與背側重佈結構1112（例如，介電層1006）分離（剝除）。根據一些實施例，剝除製程包括投射光線（雷射光或紫外線（UV））於釋放層1004上，使得釋放層1004在光的熱量下分解，且可移除承載基底1002。 然後將上述結構翻轉並放置在膠帶層1306上。
如第13圖中進一步所示，形成開口穿過介電層1006，以露出金屬化圖案1008的部分。可使用雷射鑽孔或蝕刻等形成開口。
在第14圖中，第二封裝體1400貼附至第一封裝區域1000A及第二封裝區域1000B內的金屬化圖案1008。第二封裝體1400各自包括一基底1402及耦接基底1402的一或多個堆疊晶片1410（1410A和1410B）。儘管繪示出了單個堆疊晶片1410（1410A和1410B），然而在其他實施例中，多個堆疊晶片1410（每個具有一或多個堆疊的晶片）可並排設置而耦接於基底1402的同一表面上。基底1402可由矽、鍺、鑽石等半導體材料形成。在一些實施例中，也可使用矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦等化合物材料以及其組合等。另外，基底1402可為絕緣體上覆矽（SOI）基底。通常，絕緣體上覆矽（SOI）基底包括半導體材料層，例如磊晶矽、鍺、矽鍺、絕緣體上覆矽（SOI），絕緣體上覆矽鍺（SGOI）或其組合。在另一實施例中，基底1402為絕緣芯，例如玻璃纖維增強樹脂芯。一種示例性芯材料為玻璃纖維樹脂，例如FR4。芯材料的替代物包括雙馬來醯亞胺-三嗪（BT）樹脂，或者為其他印刷電路板（PCB）材料或膜層。諸如Ajinomoto積層膜（ABF）或其他層壓板的積層膜可用於基底1402。
基底1402可以包括主動及被動裝置（未繪示）。所屬技術領域中具有通常知識者將可理解可以使用諸如電晶體、電容器、電阻器及其組合等的各種裝置來產生設計第二封裝體1400的結構與功能要求。可以使用任何合適的方法形成上述裝置。
基底1402也可以包括金屬化層（未繪示）及通孔電極1406。金屬化層可形成在主動及被動裝置上，且設計為連接各種裝置以形成功能電路。金屬化層可由交替的介電層（例如，低k值介電材料）及導電材料（例如，銅）形成，其中通孔電極內連接導電材料層，且可透過任何合適的製程（例如沉積製程、鑲嵌製程、雙鑲嵌製程）形成。在一些實施例中，基底1402實質上沒有主動及被動裝置。
基底1402可於基底1402的一第一側上具有接合墊1408以耦接至堆疊晶片1410，且在基底1402的一第二側上具有接合墊1404，第二側與基底1402的第一側相對。在一些實施例中，透過形成介電層內的凹槽（未繪示）於基板1402的第一側及第二側上來形成接合墊1408和1404。形成凹槽以允許接合墊1408及1404嵌入介電層內。在其他實施例中，省略凹槽，因為接合墊1408及1404可形成於介電層上。在一些實施例中，接合墊1408及1404包括由銅、鈦、鎳、金、鈀等或其組合形成的薄種子層（未繪示）。接合墊1408及1404的導電材料可沉積於薄種子層上。導電材料可透過電化學鍍製程、無電電鍍製程、化學氣相沉積（CVD）製程、原子層沉積（ALD）製程、物理氣相沉積（PVD）製程等或其組合形成。在一實施例中，接合墊1408及1404的導電材料為銅、鎢、鋁、銀、金等或其組合。
在一實施例中，接合墊1408及1404為凸塊下金屬層（UBM），其包括三層導電材料，例如鈦層、銅層及鎳層。然而，所屬技術領域中具有通常知識者將可理解存在許多合適的材料與膜層排置，例如鉻/鉻銅合金/銅/金的排置、鈦/鈦鎢/銅的排置或者適合於形成接合墊1408及1404的銅/鎳/金的排置。可用於接合墊1408及1404的任何合適的材料或材料層完全涵蓋於目前實施例中。在一些實施例中，通孔電極1406延伸穿過基底1402，且將至少一個接合墊1408耦接至少一個接合墊1404。
在所示實施例中，堆疊晶片1410透過接合線1414耦接至基底1402，然而可使用其他連接方式，例如導電凸塊。在一實施例中，堆疊晶片1410是堆疊的記憶體晶片。舉例來說，堆疊晶片1410可為記憶體晶片，諸如低功率（LP）雙重資料速率（double data rate, DDR）記憶體模組（例如，LPDDR1、LPDDR2、LPDDR3、LPDDR4等記憶體模組）。
堆疊晶片1410及接合線1414可由模塑材料1412進行封裝。模塑材料1412可模塑於堆疊晶片1410及接合線1414上。舉例來說，使用壓縮模塑。在一些實施例中，模塑材料1412是模塑化合物（molding compound）、聚合物、環氧樹脂、氧化矽填充材料等或其組合。可進行固化步驟以固化模塑材料1412，其中固化可為熱固化、紫外線（UV）固化等或其組合。
在一些實施例中，堆疊晶片1410及接合線1414埋入於模塑材料1412中，且在模塑材料1412固化之後，進行平坦化步驟，例如研磨，以去除模塑材料的多餘部分，使第二封裝體1400具有實質上平坦的表面。
在形成第二封裝體1400之後，第二封裝體1400透過功能連接器1416及接合墊1404機械性地和電性地接合至第一封裝區域1000A及第二封裝區域1000B內的金屬化圖案1008。在一些實施例中，堆疊晶片1410可透過接合線1414、接合墊1408及1404、通孔電極1406、功能連接器1416以及通孔電極1104耦接至積體電路晶片1108。
功能連接器1416可類似於上述導電連接器1302，且此處不再重複描述，然而功能連接器1416與導電連接器1302並不需要相同。功能連接器1416可設置於基底1402上背對於堆疊晶片1410的一側。
在第15圖中，透過沿著切割道區域1418（繪示於第14圖中）（例如在相鄰封裝區域1000A與1000B之間）切割來進行單體化製程。上述切割將第一封裝區域1000A及第二封裝區域1000B單體化。第15圖繪示出單體化的第一封裝體1500，其可來自第一封裝區域1000A及第二封裝區域1000B的其中一個。第一封裝體1500也可以稱作整合型扇出（InFO）封裝體1500。
在第16圖中，第一底膠層1602形成於第一封裝體1500與第二封裝體1400之間，且圍繞功能性連接器1416。第一底膠層1602可在第二封裝體1400貼附至第一封裝體1500之後，透過毛細管流動製程形成，或者可在第二封裝體1400貼附至第一封裝體1500之前，透過合適的沉積方法形成。在透過毛細管流動製程形成第一底膠層1602的實施例中，一定量的第一底膠材料可沉積於第二封裝體1400的邊角處。然後加熱第一封裝體1500及第二封裝體1400，以使第一底膠材料產生流動。第一底膠材料透過毛細管作用而流動於第一封裝體1500與第二封裝體1400之間。在一些實施例中，可透過在沉積第一底膠材料之前，將第二封裝體1400及第一封裝體1500的表面暴露於電漿來活化其表面，此乃為了增加上述表面的潤濕性並改善第一底膠材料的毛細管作用。
可沉積有限量的第一底膠材料以形成第一底膠層1602，以使第一底膠層1602形成於限定的區域中。第一底膠層1602的外圍部分可設置於第二封裝1400的外圍內。舉例來說，第一底膠層1602的最下表面的外圍與第二封裝體1400的外圍之間的距離D5可介於約100μm與200μm之間，例如約為150μm。在一些實施例中，第一底膠層1602的側壁可為漸細或傾斜形的。如第16圖所示，第一底膠層1602的側壁可在剖面視圖中為彎曲的。在又一些實施例中，第一底膠層1602可具有實質上垂直於第一封裝體1500的主表面的側壁的（未個別圖示說明），或者第一底膠層1602可具有漸細或傾斜的側壁並延伸超過第二封裝體1400的外圍。
第一底膠層1602可為任何可接受的材料，例如聚合物、環氧樹脂、模塑底膠層等。根據至少一個實施例，第一底膠層1602可由包括矽填料的環氧樹脂材料形成。更具體來說，第一底膠層1602可由具有約60%至70%的矽的重量百分比的環氧樹脂材料形成，例如約為75%。第一底膠層1602可具有介於約20ppm/ºC與30ppm/ºC之間的熱膨脹係數（CTE），例如約為20ppm/ºC。
在第17圖中，形成第二底膠層1702圍繞第一底膠層1602以形成半導體裝置1700。也可形成第二底膠層1702圍繞第二封裝體1400的至少一部分，例如圍繞基底1402及/或模塑材料1412。如第17圖所示，第二底膠層1702可自介電層1006的表面延伸至切齊基底1402的上表面的點。在一些實施例中，第二底膠層1702的最頂部區域範圍可位於基底1402的上表面上方，或者位於基底1402的上表面下方。第二底膠層1702可沿著基底1402的邊緣形成，以密封基底1402的邊緣並降減少基底1402發生破裂。第二底膠層1702可完全包圍第一底膠層1602的外圍。第二底膠層1702的最頂部區域範圍可延伸於第一底膠層1602的最頂部表面上方。第二底膠層1702的製作可透過在第一底膠層1602外圍沉積一定量的第二底膠材料並使第二底膠材料回流。第二底膠層1702的外圍與第二封裝體1400的外圍之間的距離D6可小於約2mm，小於約2.5mm，或小於約3mm。如第17圖所示，第二底膠層1702的側壁可為傾斜或漸細形的，且可在剖面視圖中為彎曲的。
第二底膠層1702可為任何可接受的材料，例如聚合物、環氧樹脂、模塑底膠層等。第二底膠層1702可由與第一底膠層1602不同的材料形成，或者第二底膠層1702可由具有與第一底膠層1602相同的組成而不同的比例的材料形成。舉例來說，在一實施例中，第一底膠層1602由包括矽填料的環氧樹脂材料形成。第二底膠層1702可由包括矽填料的環氧樹脂材料形成，其矽填料的矽濃度高於第一底膠層1602的矽填料。更具體來說，第二底膠層1702可由矽的重量百分比介於約70%與約85%之間的環氧樹脂材料形成，例如約75%或85%。在一些實施例中，第一底膠層1602的環氧樹脂材料內的矽填料可具有與第二底膠層1702的環氧樹脂材料內的902不同的尺寸。
第二底膠層1702可具有小於約25ppm/ºC的熱膨脹係數（CTE），小於約20ppm/ºC或小於約10ppm/ºC，例如約為8ppm/ºC、9ppm/ºC、11ppm/ºC、22ppm/ºC或24ppm/ºC。因此，第二底膠層1702的熱膨脹係數（CTE）可小於第一底膠層1602的熱膨脹係數（CTE）約18ppm/ºC、約17ppm/ºC或約11ppm/ºC。第二底膠層1602的熱膨脹係數（CTE）也可與第一封裝體1500的熱膨脹係數（CTE）匹配。舉例來說，第二底膠層1702的熱膨脹係數（CTE）可介於第一底膠層1602的熱膨脹係數（CTE）與第一封裝體1500的熱膨脹係數（CTE）之間。第一底膠層1602與第二底膠層1702的熱膨脹係數（CTE）的比率可介於約2與4之間，例如約為3.7、2.6或2。第一底膠層1602與第二底膠層1702的熱膨脹係數（CTE）的比率大於及小於上述範圍可能由於第一底膠層1602與第二底膠層1702之間的熱膨脹係數（CTE）不匹配或者由於第二底膠層1702與第一封裝體1500之間的熱膨脹係數（CTE）不匹配而導致底膠層的破裂。
在形成第一底膠層1602與第二底膠層1702之後，固化第一底膠層1602與第二底膠層1702。第一底膠層1602與第二底膠層1702可以在室溫下或經由加熱或紫外線（UV）而固化。 在一些實施例中，第一底膠層1602可在形成第二底膠層1702之前固化，或者第一底膠層1602與第二底膠層1702可同時固化。
與第一底膠層1602相比，第二底膠層1702具有不良的流動性。舉例來說，第二底膠層1702具有介於約55 Pa·s與70 Pa·s之間的黏度，例如約為65 Pa·s。而第一底膠層1602具有介於約100 Pa·s與200 Pa·s之間的黏度，例如約為150 Pa·s。如此，第一底膠層1602可於第一裝置封裝體1500與第二裝置封裝體1400之間流動，因而完全填充空間並包圍功能連接器1416。
此外，半導體裝置1700於半導體裝置1700的邊角處受到高應力/應變。第二底膠層1702可於半導體裝置1700的邊角處具有比第一底膠層1602更少的應變能量。例如，第二底膠層1702可具有約1μJ至約3μJ之間的角應變能量，例如約為2.18μJ或1.68μJ。角應變能量值高於這些值會將底膠層破裂風險增加至不可接受的程度 。第一底膠層1602可具有介於約4μJ與約6μJ之間的角應變能量，例如約為5.08μJ或5.3μJ。因此，第二底膠層1702的角應變能量可小於第一底膠層1602的角應變能量介於約1μJ與約5μJ之間，例如約為1μJ、2μJ或4μJ。增加的角應變能量可能導致在底膠層中更早出現裂縫。因此，包括具有比第一底膠層1602更低的角應變能量的第二底膠層1702降低半導體裝置1700的角應變能量並且降低底膠層中開裂的可能性。因此，具有第一底膠層1602及第二底膠層1702兩者的半導體裝置1700可防止凸塊破裂、底膠層破裂及離層，同時仍然允許底膠層流動於且實質上填充於第一裝置封裝體1500與第二裝置封裝體1400之間的區域。如此一來，半導體裝置1700的整體結構更加穩固。
儘管未個別圖示說明，然而根據一些實施例，半導體裝置1700可包括與前述第9B圖所示的實施例的環形體910及蓋板912類似的一或多個蓋板及環形體。更具體來說，可提供一第一蓋板及一第一環形體以消散第一封裝體1500中產生的熱量並保護第一封裝體1500，且可提供一第二蓋板及一第二環形體以消散第二封裝體1400中產生的熱量並保護第二封裝體1400。在一些實施例中，可以提供單一環形體及單一蓋板以消散在第一封裝體1500與第二封裝體1400中產生的熱量並保護第一封裝體1500與第二封裝體1400兩者。如此，熱量可自第一封裝體1500與第二封裝體1400消散至外部環境並可保護第一封裝體1500與第二封裝體1400。
根據一實施例中，一種半導體裝置封裝體包括：一封裝體，包括一積體電路晶片、經由多個晶片連接器接合至積體電路晶片的一中介層以及圍繞積體電路晶片的一封膠層；一封裝基底，經由多個導電連接器接合至中介層；一第一底膠層，位於封裝體與封裝基板之間，第一底膠層具有一第一熱膨脹係數；以及一第二底膠層，圍繞第一底膠層，第二底膠層具有小於第一熱膨脹係數的一第二熱膨脹係數。在一實施例中，第一底膠層自封裝體朝向封裝基底逐漸變細。在一實施例中，第二底膠層自封裝基底朝向封裝體逐漸變細。在一實施例中，第一底膠層及第二底膠層自封裝基底朝向封裝體逐漸變細。在一實施例中，第一底膠層與中介層接觸，且與封膠層隔開。在一實施例中，第二底膠層與封裝體接觸，且與導電連接器隔開。在一實施例中，第一底膠層具有大於第二底膠層的一流動性。
根據另一實施例，一種半導體裝置封裝體之製造方法包括：將一晶片貼附至一中介層的一第一表面；以一封膠層封裝晶片；形成多個導電連接器於中介層的一第二表面，第二表面相對於第一表面；經由導電連接器將中介層接合至一封裝基底；沉積一第一底膠層於中介層與封裝基底之間，並圍繞導電連接器；以及沉積一第二底膠層以圍繞第一底膠層，第二底膠層具有比第一底膠層低的熱膨脹係數。在一實施例中，形成第一底膠層包括使一第一底膠材料流動於中介層與封裝基底之間。在一實施例中，在形成第二底膠層之前固化第一底膠層。在一實施例中，第一底膠層與第二底膠層為同時固化。在一實施例中，上述方法更包括在形成第一底膠層之前，將中介層與封裝基底的表面暴露於一電漿。在一實施例中，第二底膠層具有高於第一底膠層的矽重量濃度。在一實施例中，第二底膠層具有一熱膨脹係數低於該第一底膠層的一熱膨脹係數。
又根據另一實施例，一種半導體裝置封裝體包括：一第一封裝體，包括：一第一積體電路晶片、圍繞第一積體電路晶片的一封膠層以及位於封膠層及第一積體電路晶片上的一重佈層；多個功能連接器；一第二封裝體，經由多個功能連接器接合至第一封裝體，其中功能連接器及重佈層電性連接第二封裝體的一第二積體電路晶片至第一積體電路晶片；一第一底膠層，位於第一封裝體與第二封裝體之間，第一底膠層圍繞功能連接器；以及一第二底膠層，圍繞第一底膠層，第二底膠層具有不同於第一底膠層的材料組成，第二底膠層的最頂部區域範圍位於第一底膠層的最上表面的上方。在一實施例中，第二底膠層具有低於第一底膠層的一熱膨脹係數。在一實施例中，第二底膠層延伸於第二封裝體正下方位於第一底膠層與重佈層之間。在一實施例中，第二底膠層接觸第二封裝體的一第一側表面及相對於第二封裝體的第一側表面的一第二側表面。在一實施例中，第一底膠層的一橫向外圍延伸超出第一封裝體的一橫向外圍。在一實施例中，第二底膠層自重佈層的一上表面延伸至第二封裝體的一側壁。
以上概略說明了本發明數個實施例的特徵，使所屬技術領域中具有通常知識者對於本揭露的型態可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到可輕易利用本揭露作為其它製程或結構的變更或設計基礎，以進行相同於此處所述實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構並未脫離本揭露之精神和保護範圍內，且可在不脫離本揭露之精神和範圍內，當可作更動、替代與潤飾。
100‧‧‧第一裝置封裝體100A、100B‧‧‧裝置區域102‧‧‧晶圓104‧‧‧晶片連接器106A‧‧‧第一晶片堆疊106B‧‧‧第二晶片堆疊202‧‧‧底膠層302、1110‧‧‧封膠層402‧‧‧導電連接器404、1306‧‧‧膠帶602‧‧‧中介層700‧‧‧第二裝置封裝體702‧‧‧封裝基底704、1404、1408‧‧‧接合墊802、802a、1602‧‧‧第一底膠層900、1700‧‧‧半導體裝置902、1702‧‧‧第二底膠層910‧‧‧環形體912‧‧‧蓋板914‧‧‧第二黏著層916‧‧‧第一黏著層918‧‧‧熱界面材料1000A‧‧‧第一封裝區域1000B‧‧‧第二封裝區域1002‧‧‧承載基底1004‧‧‧釋放層1006、1102‧‧‧介電層1008‧‧‧金屬化圖案1104、1406‧‧‧通孔電極1106‧‧‧黏著層1108‧‧‧積體電路晶片1112‧‧‧背側重佈結構1202‧‧‧前側重佈結構1302‧‧‧導電連接器1304‧‧‧接墊/凸塊下金屬層1400‧‧‧第二封裝體1402‧‧‧基底1410、1410A、1410B‧‧‧堆疊晶片1412‧‧‧模塑材料1414‧‧‧接合線1416‧‧‧功能連接器1500‧‧‧第一封裝體D1、D2、D3、D4、D5、D6‧‧‧距離
第1-8、8A、9、9A-9B圖係繪示出根據一些實施例之半導體裝置封裝體中間製造階段的剖面示意圖。 第10至17圖係繪示出根據一些實施例之半導體裝置封裝體中間製造階段的剖面示意圖。
100‧‧‧第一裝置封裝體
104‧‧‧晶片連接器
106A‧‧‧第一晶片堆疊
106B‧‧‧第二晶片堆疊
202‧‧‧底膠層
302‧‧‧封膠層
402‧‧‧導電連接器
602‧‧‧中介層
702‧‧‧封裝基底
704‧‧‧接合墊
802‧‧‧第一底膠層
900‧‧‧半導體裝置
902‧‧‧第二底膠層
D3‧‧‧距離

Claims (10)

  1. 一種半導體裝置封裝體，包括：一封裝體，包括：一積體電路晶片；一中介層，經由多個晶片連接器接合至該積體電路晶片；以及一封膠層，圍繞該積體電路晶片；一封裝基底，經由多個導電連接器接合至該中介層；一第一底膠層，位於該封裝體與該封裝基板之間，該第一底膠層具有一第一熱膨脹係數；以及一第二底膠層，圍繞及接觸該第一底膠層且與該等導電連接器隔開，該第二底膠層具有小於該第一熱膨脹係數的一第二熱膨脹係數。
  2. 如申請專利範圍第1項所述之半導體裝置封裝體，其中該第一底膠層自該封裝體朝向該封裝基底逐漸變細，該第二底膠層自該封裝基底朝向該封裝體逐漸變細。
  3. 如申請專利範圍第1項所述之半導體裝置封裝體，其中該第一底膠層與該中介層接觸，且與該封膠層隔開，該第二底膠層與該封裝體接觸。
  4. 如申請專利範圍第1項所述之半導體裝置封裝體，其中該第一底膠層具有大於該第二底膠層的一流動性。
  5. 一種半導體裝置封裝體之製造方法，包括：將一晶片貼附至一中介層的一第一表面；以一封膠層封裝該晶片；形成多個導電連接器於該中介層的一第二表面，該第二表面相對該於第一表面；經由該等導電連接器將該中介層接合至一封裝基底； 沉積一第一底膠層於該中介層與該封裝基底之間，並圍繞該等導電連接器；以及沉積一第二底膠層以圍繞及接觸該第一底膠層且與該等導電連接器隔開，該第二底膠層具有比該第一底膠層低的熱膨脹係數。
  6. 如申請專利範圍第5項所述之半導體裝置封裝體之製造方法，更包括在形成第一底膠層之前，將該中介層與該封裝基底的表面暴露於一電漿。
  7. 如申請專利範圍第5項所述之半導體裝置封裝體之製造方法，其中該第二底膠層具有高於第一底膠層的矽重量濃度。
  8. 一種半導體裝置封裝體，包括：一第一封裝體，包括：一第一積體電路晶片；一封膠層，圍繞該第一積體電路晶片；以及一重佈層，位於該封膠層及該第一積體電路晶片上；多個功能連接器；一第二封裝體，經由該等功能連接器接合至該第一封裝體，其中該等功能連接器及該重佈層電性連接該第二封裝體的一第二積體電路晶片至該第一積體電路晶片；一第一底膠層，位於該第一封裝體與該第二封裝體之間，該第一底膠層圍繞該等功能連接器；以及一第二底膠層，圍繞及接觸該第一底膠層且與該等功能連接器隔開，該第二底膠層具有不同於該第一底膠層的材料組成，該第二底膠層的最頂部區域範圍位於該第一底膠層的最上表面的上方。
  9. 如申請專利範圍第8項所述之半導體裝置封裝體，其中該第二底膠層延伸於該第二封裝體正下方位於該第一底膠層與該重佈層之間。
  10. 如申請專利範圍第8項所述之半導體裝置封裝體，其中該第二底膠層自該重佈層的一上表面延伸至該第二封裝體的一側壁。
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