TWI722411B - 半導體封裝、半導體封裝堆疊及其製造方法 - Google Patents

半導體封裝、半導體封裝堆疊及其製造方法 Download PDF

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TWI722411B
TWI722411B TW108112197A TW108112197A TWI722411B TW I722411 B TWI722411 B TW I722411B TW 108112197 A TW108112197 A TW 108112197A TW 108112197 A TW108112197 A TW 108112197A TW I722411 B TWI722411 B TW I722411B
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semiconductor
encapsulation body
semiconductor package
electrically connected
semiconductor die
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TW108112197A
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TW202030848A (zh
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施信益
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南亞科技股份有限公司
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Abstract

本發明提供一種半導體封裝、半導體封裝堆疊及其製造方法。半導體封裝包括半導體晶粒、包封體以及包封體穿孔。半導體晶粒包括半導體基底、內連線層與半導體貫孔。半導體基底具有彼此相對的主動面與背側表面。內連線層設置於半導體基底的主動面上。半導體貫孔由半導體基底的背側表面至半導體基底的主動面而貫穿半導體基底。包封體側向包封半導體晶粒。包封體穿孔貫穿包封體。

Description

半導體封裝、半導體封裝堆疊及其製造方法
本發明是有關於一種半導體封裝及其製造方法，且特別是有關於一種三維半導體封裝及其製造方法。
隨著對於電子元件之微縮的要求不斷提高，逐漸產生了對於更小且更新穎的半導體晶粒之封裝技術的需求。舉例而言，層疊式封裝（package-on-package，POP）屬於上述封裝技術的其中一種。層疊式封裝包括多個彼此堆疊的半導體封裝，且可視為一種三維半導體封裝。在典型的疊層式封裝中，中間半導體封裝設置於頂部半導體封裝與底部半導體封裝之間。目前來說，需透過中間半導體封裝的前側重佈線層（front-side redistribution layer，RDL）來實現中間半導體封裝與頂部半導體封裝之間的訊號傳輸以及中間半導體封裝與底部半導體封裝之間的訊號傳輸。因此，前側重佈線層的佈線密度非常高，且封裝結構的可靠度可能會受到影響。
本發明提供一種層疊式半導體封裝，具有較佳的可靠度。此外，本發明亦提供此層疊式半導體封裝的製造方法。
本發明實施例的半導體封裝包括半導體晶粒、包封體與包封體穿孔。半導體晶粒包括半導體基底、內連線層以及半導體貫孔。半導體基底具有彼此相對的主動面與背側表面。內連線層設置於半導體基底的主動面上。半導體貫孔由半導體基底的背側表面至半導體基底的主動面貫穿半導體基底。包封體側向包封半導體晶粒。包封體穿孔貫穿包封體。
在一些實施例中，半導體封裝更包括前側重佈線結構以及背側重佈線結構。前側重佈線結構設置於內連線層與包封體的前側表面上。前側重佈線結構電性連接於內連線層與包封體穿孔。背側重佈線結構設置於半導體基底的背側表面與包封體的背側表面上。包封體的背側表面相對於包封體的前側表面，且背側重佈線結構電性連接於半導體貫孔與包封體穿孔。
在一些實施例中，半導體封裝更包括前側導電連接件以及背側導電連接件。前側導電連接件設置於前側重佈線結構上，且電性連接於前側重佈線結構。背側導電連接件設置於背側重佈線結構上，且電性連接於背側重佈線結構。
在一些實施例中，包封體的背側表面實質上共面於半導體基底的背側表面。
在一些實施例中，包封體的前側表面實質上共面於半導體晶粒的前側表面。半導體基底的主動面面向半導體晶粒的前側表面，且半導體基底的背側表面背向半導體晶粒的前側表面。
在一些實施例中，半導體晶粒包括記憶體晶粒。
本發明實施例的半導體封裝堆疊包括如上所述的半導體封裝、底部半導體封裝以及頂部半導體封裝。底部半導體封裝附接至半導體封裝的底面，且電性連接於內連線層與包封體穿孔。頂部半導體封裝附皆至半導體封裝的頂面，且電性連接於半導體貫孔與包封體穿孔。
在一些實施例中，底部半導體封裝包括底部半導體晶粒、底部包封體與底部包封體穿孔。底部包封體包封底部半導體晶粒。底部包封體穿孔貫穿底部包封體，且電性連接於半導體封裝的包封體穿孔。
在一些實施例中，底部半導體晶粒的頂面埋入於底部包封體中，底部半導體晶粒的底面實質上共面於底部包封體的底面。
在一些實施例中，半導體封裝堆疊更包括封裝基底。封裝基底附接至底部半導體封裝的底面。
本發明實施例的半導體封裝的製造方法包括：提供半導體晶粒，其中半導體晶粒包括半導體基底、內連線層以及半導體貫孔，內連線層設置於半導體基底的主動面上，半導體貫孔由半導體基底的背側表面至半導體基底的主動面而貫穿半導體基底；以包封體側向包封半導體晶粒；以及形成貫穿包封體的包封體穿孔。
在一些實施例中，半導體封裝的製造方法更包括：在形成包封體之前將半導體晶粒附接至第一載體上，其中半導體基底的背側表面面向第一載體，且半導體基底的主動面背向第一載體；以及在形成包封體與包封體穿孔之後分離第一載體。
在一些實施例中，形成包封體穿孔的步驟在形成包封體的步驟之前。
在一些實施例中，形成包封體、將半導體晶粒附接至第一載體以及形成包封體穿孔的步驟包括：在第一載體的表面上形成包封體穿孔；將半導體晶粒附接至第一載體的表面上；以及以包封體側向包封半導體晶粒與包封體穿孔。
在一些實施例中，形成包封體穿孔的步驟在形成包封體的步驟之後。
在一些實施例中，將半導體晶粒附接至第一載體、形成包封體、以及形成包封體穿孔的步驟包括：將半導體晶粒附接至第一載體的表面上；以包封體側向包封半導體晶粒；移除包封體的一部分，以在包封體中形成穿孔；以及在穿孔中填入導體材料，以形成包封體穿孔。
在一些實施例中，半導體封裝的製造方法更包括：在內連線層與包封體的前側表面上形成前側重佈線結構，其中前側重佈線結構電性連接於內連線層與包封體穿孔；以及在前側重佈線結構上形成前側導電連接件，其中前側導電連接件電性連接於前側重佈線結構。
在一些實施例中，在形成包封體與包封體穿孔之後，更包括：將第二載體附接至包封體、半導體晶粒與包封體穿孔的背向第一載體的表面。
在一些實施例中，半導體封裝的製造方法更包括：在半導體基底的背側表面與包封體的背側表面上形成背側重佈線結構，其中背側重佈線結構電性連接於半導體貫孔以及包封體穿孔；在背側重佈線結構上形成背側導電連接件，其中背側導電連接件電性連接於背側重佈線結構；以及分離第二載體。
本發明實施例的半導體封裝堆疊的製造方法包括：如上所述的半導體封裝的製造方法；將頂部半導體封裝附接至半導體封裝的頂面，其中頂部半導體封裝電性連接於半導體貫孔與包封體穿孔；以及將底部半導體封裝附接至半導體封裝的底面，其中底部半導體封裝電性連接於內連線層與包封體穿孔。
基於上述，本發明實施例的半導體封裝包括包封體穿孔與半導體貫孔兩者。包封體穿孔貫穿側向環繞半導體晶粒的包封體，而半導體貫孔由半導體晶粒的背側至半導體晶粒的主動側而貫穿半導體晶粒。半導體封裝堆疊於頂部半導體封裝與底部半導體封裝之間時，可藉由包封體穿孔來實現頂部半導體封裝與底部半導體封裝之間的通訊。另一方面，訊號可從半導體晶粒的背側（例如是由頂部半導體封裝）經由半導體貫孔而傳輸到半導體晶粒的主動側，而並未行經包封體穿孔以及設置於半導體晶粒的主動側的前側重佈線結構，且反之亦然。如此一來，可縮短在半導體晶粒的背側與主動側之間的訊號傳輸路徑。此外，可降低半導體封裝的前側重佈線結構的配線密度，且可提高半導體封裝的可靠度。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1是依照本發明一些實施例的半導體封裝的製造方法的流程圖。圖2A至圖2K是依照本發明一些實施例的半導體封裝的製造方法中各階段的結構的剖視示意圖。
請參照圖1與圖2A，進行步驟S100，以提供半導體晶粒100。在一些實施例中，半導體晶粒100可為記憶體晶粒，例如是動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒。半導體晶粒100包括半導體基底102以及設置於半導體基底102上的元件層104。半導體基底102可為半導體晶圓或絕緣體上覆半導體（semiconductor-on-insulator，SOI）晶圓。半導體晶圓或SOI晶圓的半導體材料可包括元素半導體、合金半導體或化合物半導體。舉例而言，元素半導體可包括Si或Ge。合金半導體可包括SiGe、SiGeC或其類似者，而化合物半導體可包括SiC、III-V族半導體或II-VI族半導體。半導體基底102具有主動面AS與相對於主動面AS的背側表面BS。元件層104形成於半導體基底102的主動面AS上。一部分的半導體元件106形成於元件層104，而半導體元件106的其他部分（未繪示）可埋入於半導體基底102中。在一些實施例中，半導體元件106可包括記憶體元件。舉例而言，半導體元件106可包括電晶體、電容、其類似者或其組合。
內連線層108設置於元件層104上。多個內連線單元110形成於內連線層108中，且電性連接於下伏的半導體元件106。舉例而言，內連線單元110可包括導電通孔、導電跡線或其組合。此外，可於內連線層108上形成導電接墊112。導電接墊112電性連接於內連線單元110。在一些實施例中，於導電接墊112上形成至少一保護層116，且上述至少一保護層116具有至少局部地暴露出導電接墊112的前側表面（亦即圖2A所示的導電接墊112的上表面）的開口。可於保護層116上形成導電柱114，且導電柱114延伸至保護層116的上述開口中，以電性連接於導電接墊112。在一些實施例中，絕緣材料118可側向地環繞導電柱114的突出於保護層116之一些部分。在此些實施例中，絕緣材料118的前側表面（亦即圖2A所示的絕緣材料118的上表面）可實質上共面於導電柱114的前側表面（亦即圖2A所示的導電柱114的上表面）。在替代實施例中，導電柱114的前側表面此時被絕緣材料118覆蓋，且將在後續步驟（例如是步驟S108）中對半導體晶粒100以及側向環繞半導體晶粒100的包封體（例如是圖2D所示的包封體124）進行平坦化製程時被暴露出來。
此外，半導體晶粒100亦包括半導體貫孔（through semiconductor via，TSV）120。半導體貫孔120由半導體基底102的背側表面BS至半導體基底102的主動面AS而貫穿半導體基底102，且電性連接於形成在內連線層108中的內連線單元110。如圖2A所示，在一些實施例中，半導體貫孔120更貫穿元件層104，且接觸於內連線層108。在此些實施例中，是以中段穿孔製程（TSV-middle process）形成半導體晶粒100。換言之，形成半導體貫孔120的步驟是在形成元件層104之後，而在形成內連線層108之前。藉由設置半導體貫孔120，訊號可從半導體基底102的背側表面BS經由半導體貫孔120與內連線單元110而傳輸到設置於半導體基底102的主動面AS上的半導體元件106。在一些實施例中，半導體元件106位於半導體晶粒100的中心區域，而半導體貫孔120設置於半導體晶粒100的邊緣區域中。
在替代實施例中，半導體貫孔120的前側表面（亦即圖2A所示的半導體貫孔120的上表面）實質上共面於半導體基底102的主動面AS，且半導體貫孔120可藉由導電插塞（未繪示）而電性連接於內連線單元110。導電插塞（未繪示）由半導體貫孔120的前側表面延伸至元件層104的前側表面（亦即圖2A所示的元件層104的上表面）。在此些替代實施例中，是以先穿孔製程（TSV-first process）形成半導體晶粒100。換言之，形成半導體貫孔120的步驟是在形成元件層104與內連線層108的步驟之前。在其他實施例中，半導體貫孔120可實質上貫穿整個半導體晶粒100。在此些實施例中，是以後穿孔製程（TSV-last process）形成半導體晶粒100，且形成半導體貫孔120的步驟是在形成元件層104與內連線層108的步驟之後。
請參照圖1與圖2B，進行步驟S102，以提供第一載體CA1。在一些實施例中，第一載體CA1為玻璃載板。此外，可在第一載體CA1的將在後續步驟中附接半導體晶粒100的表面上形成黏著層（未繪示）。在一些實施例中，黏著層可為光熱轉換（light-to-heat-conversion，LTHC）層、熱離形層（thermal release layer）或其類似者。
在一些實施例中，進行步驟S104，以在第一載體CA1上形成包封體穿孔122（也可稱為中介體穿孔（through interposer via，TIV）。在第一載體CA1上預先形成有黏著層的實施例中，此黏著層位於包封體穿孔122與第一載體CA1之間。包封體穿孔122可為導電柱。在一些實施例中，包封體穿孔122的形成方法包括在第一載體CA1上形成全面性披覆的晶種層（未繪示）。隨後，在晶種層上形成具有定義出包封體穿孔122的位置與尺寸的開口的光阻圖案（未繪示）。接著，藉由例如是鍍覆製程而在光阻圖案的開口中填入導體材料，以形成包封體穿孔122。最後，藉由例如是剝除製程（stripping process）或灰化製程（ashing process）移除光阻圖案。
請參照圖1與圖2C，進行步驟S106，以將多個半導體晶粒100附接至第一載體CA1上。附接至第一載體CA1上的半導體晶粒100面向上方。也就是說，半導體基底102的背側表面BS面向第一載體CA1，而半導體基底102的主動面AS背向第一載體CA1。在一些實施例中，包封體穿孔122是預先形成於第一載體CA1上，且一些相鄰的包封體穿孔122之間具有適當的間距，以使此些相鄰包封體穿孔122之間的空間可容納至少一半導體晶粒100。舉例而言，如圖2C所示，4個半導體晶粒100附接至第一載體CA1上，且兩兩分別位於相鄰的包封體穿孔122之間。然而，所屬領域中具有通常知識者可改變附接至第一載體CA1的半導體晶粒100的數量以及包封體穿孔122與半導體晶粒100的配置，本發明並不以此為限。在一些實施例中，藉由取放製程（pick-and-place process）而將半導體晶粒100附接至第一載體CA1上。在此些實施例中，預先形成的包封體穿孔122可在取放製程期間作為對位標記。
請參照圖1與圖2D，進行步驟S108，以包封體124包封半導體晶粒100。如此一來，形成包括半導體晶粒100與包封體124的重構晶圓（reconstructed wafer）。在包封體穿孔122預先形成於第一載體CA1上的實施例中，包封體穿孔122與半導體晶粒100兩者均被包封體124包封。包封體穿孔122可視為貫穿包封體124。在一些實施例中，可以包封材料包覆（over mold）包封體穿孔122與半導體晶粒100，使包封體穿孔122與半導體晶粒100埋入於此包封材料中。隨後，可對此包封材料進行平坦化製程，以暴露出包封體穿孔122與半導體晶粒100的導電柱114的前側表面（亦即圖2D所示的包封體穿孔122與導電柱114的上表面）。包封材料的殘留部分形成包封體124。在一些實施例中，包封體124的前側表面124a實質上共面於包封體穿孔122與導電柱114的前側表面。另一方面，包封體124的背側表面124b實質上共面於包封體穿孔122的底面以及半導體基底102的背側表面BS。舉例而言，平坦化製程包括化學機械研磨（chemical mechanical polishing，CMP）製程或蝕刻製程。
在替代實施例中，形成包封體124的步驟（亦即步驟S108）在形成包封體穿孔122的步驟（亦即步驟S104）之前。在此些替代實施例中，於步驟S108中以包封體124包封半導體晶粒100。隨後，於步驟S104中移除包封體124的一些部分以在包封體124中形成穿孔，且在包封體124的穿孔中填入導體材料，而形成包封體穿孔122。在一些實施例中，包封體124的材料為光敏材料（photosensitive material），且可藉由微影製程以在包封體124中形成穿孔。在其他實施例中，包封體124並非由光敏材料構成，且藉由微影製程與蝕刻製程以在包封體124中形成穿孔。
請參照圖1與圖2E，進行步驟S110，以在如圖2D所示的重構晶圓上形成前側重佈線結構126。如此一來，前側重佈線結構126覆蓋此重構晶圓的背向第一載體CA1的前側表面（亦即圖2D所示的重構晶圓的上表面）。換言之，前側重佈線結構126覆蓋包封體124的前側表面124a以及導電柱114與包封體穿孔122的前側表面。在一些實施例中，前側重佈線結構126包括彼此堆疊的多層介電層128（例如是4層介電層128）以及重佈線單元130。然而，所屬領域中具有通常知識者可改變前側重佈線結構126的介電層128之數量，本發明並不以此為限。重佈線單元130形成於介電層128之堆疊結構中。此外，重佈線單元130的一些部分經由導電柱114而電性連接於半導體晶粒100的內連線層108，而重佈線單元130的另一些部分電性連接於包封體穿孔122。在一些實施例中，重佈線單元130包括導電通孔、導電跡線或其組合。藉由設置前側重佈線結構126，半導體晶粒100的輸入/輸出端（例如是導電柱114）可被擴展地配線（out rout）至含有被包封體124側向包封的半導體晶粒100的重構晶圓之範圍。
進行步驟S112，以在前側重佈線結構126上形成前側導電連接件132。前側導電連接件132電性連接於位在前側重佈線結構126中的重佈線單元130。在一些實施例中，前側導電連接件132包括受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、焊料凸塊（solder bump）、球柵陣列（ball grid array，BGA）、導電柱、其類似者或其組合。前側導電連接件132的形成方法可包括圖案化前側重佈線結構126的最外側介電層128，以在最外側介電層128中形成多個開口。隨後，分別於此些開口中形成前側導電連接件132。在一些實施例中，可在形成前側導電連接件132之前形成分別覆蓋最外側介電層128的多個開口的多個凸塊下金屬（under bump metallization，UBM）層134。在此些實施例中，在形成前側導電連接件132之後，多個凸塊下金屬層134分別位於前側導電連接件132與最外側的重佈線單元130之間，且位於前側導電連接件132與最外側介電層128之間。
請參照圖1、圖2E與圖2F，進行步驟S114，以將第二載體CA2附接至目前封裝結構（如圖2E所示）的背向第一載體CA1的前側表面。此外，翻轉目前的結構，且將第一載體CA1自目前的封裝結構分離。在一些實施例中，第二載體CA2附接至封裝結構的前側導電連接件132。再者，在一些實施例中，黏著層136預先形成於第二載體CA2的附接於前側導電連接件132之表面上。如此一來，在第二載體CA2附接於前側導電連接件132之後，黏著層136位於前側導電連接件132與第二載體CA2之間。在一些實施例中，藉由層壓製程（lamination process）將第二載體CA2附接至封裝結構上，且前側導電連接件132可能埋入於黏著層136中。據此，黏著層136可填於前側重佈線結構126與第二載體CA2之間的空間中。舉例而言，第二載體CA2為玻璃載體。在分離第一載體CA1之後，暴露出半導體基底102的背側表面BS、包封體124的背側表面124b以及包封體穿孔122與半導體貫孔120的背向第二載體CA之背側表面（亦即圖2F所示的包封體穿孔122與半導體貫孔120的上表面）。在一些實施例中，第一載體CA1上預先形成有黏著層（未繪示，且例如是光熱轉換層或熱離形層），且藉由對黏著層照射光或熱而使黏著層失去黏性，而使得形成有黏著層的第一載體CA1自封裝結構分離。
請參照圖1、圖2F與圖2G，進行步驟S116，以在圖2F所示的封裝結構的暴露表面上形成背側重佈線結構138。如此一來，背側重佈線結構138覆蓋半導體基底102的背側表面BS、包封體124的背側表面124b以及包封體穿孔122與半導體貫孔120的背向第二載體CA2之背側表面。在一些實施例中，背側重佈線結構138包括彼此堆疊的多層介電層140（例如是4層介電層140）以及重佈線單元142。然而，所屬領域中具有通常知識者可改變背側重佈線結構138的介電層140之數量，本發明並不以此為限。重佈線單元142形成於介電層140之堆疊結構中。此外，重佈線單元142的一些部分電性連接於半導體晶粒100的半導體貫孔120，而重佈線單元142的另一些部分電性連接於包封體穿孔122。如此一來，半導體貫孔120電性連接於內連線層108與背側重佈線結構138之間，而包封體穿孔122電性連接於前側重佈線結構126與背側重佈線結構138之間。在一些實施例中，重佈線單元142包括導電通孔、導電跡線或其組合。
進行步驟S118，以在背側重佈線結構138上形成背側導電連接件144。背側導電連接件144電性連接於位在背側導重佈線結構138中的重佈線單元142。在一些實施例中，背側導電連接件144包括受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、焊料凸塊（solder bump）、球柵陣列（ball grid array，BGA）、導電柱、其類似者或其組合。背側導電連接件144的形成方法可包括圖案化背側重佈線結構138的最外側介電層140，以在最外側介電層140中形成多個開口。隨後，分別於此些開口中形成背側導電連接件144。在一些實施例中，可在形成背側導電連接件144之前形成分別覆蓋最外側介電層140的多個開口的多個凸塊下金屬（under bump metallization，UBM）層146。在此些實施例中，在形成背側導電連接件144之後，多個凸塊下金屬層146分別位於背側導電連接件144與最外側的重佈線單元142之間，且位於背側導電連接件144與最外側介電層140之間。
請參照圖1、圖2G與圖2H，進行步驟S120，以分離第二載體CA2。如此一來，暴露出目前封裝結構的前側表面與背側表面。在一些實施例中，目前封裝結構的前側表面包括前側導電連接件132與前側重佈線結構126的表面，而目前封裝結構的背側表面包括背側導電連接件144與背側重佈線結構138的表面。在一些實施例中，預先形成於第二載體CA2上的黏著層136為光熱轉換層或熱離形層，且藉由對黏著層照射光或熱而使黏著層136失去黏性，而使得形成有黏著層136的第二載體CA2自封裝結構分離。在一些實施例中，在分離第二載體CA2之後，可將目前的封裝結構附接於膠帶TP。舉例而言，翻轉目前的封裝結構，且使前側導電連接件132附接至膠帶TP。在一些實施例中，膠帶TP連接於框架（未繪示）。
請參照圖1、圖2H與圖2I，進行步驟S122，以對目前的封裝結構進行單體化製程。多個經單體化的封裝結構分別稱作半導體封裝10。各半導體封裝10包括至少一半導體晶粒100以及位於半導體晶粒100周圍的包封體穿孔122。在一些實施例中，單體化製程包括鋸切製程（sawing process）、雷射剝蝕製程（laser ablation process）、蝕刻製程、其類似者或其組合。
請參照圖1、圖2I與圖2J，進行步驟S124，以將半導體封裝10附接至底部半導體封裝150上。在一些實施例中，底部半導體封裝150包括半導體晶粒152、包封體穿孔154以及包封體156。包封體穿孔154圍繞半導體晶粒152。此外，包封體156包封半導體晶粒152與包封體穿孔154。在一些實施例中，半導體晶粒152為邏輯晶粒，例如是控制器晶粒（controller die）。半導體晶粒152可面向下方。如此一來，半導體晶粒152的主動面（或稱為前側表面）AS1背向上覆的半導體封裝10，而半導體晶粒152的背側表面BS1面向半導體封裝10。此外，半導體晶粒152的主動面AS1被包封體156暴露出來，而半導體晶粒152的背側表面BS1則埋入於包封體156中。在一些實施例中，半導體晶粒152具有導電柱153，其暴露於半導體晶粒152的主動面AS1，並可作為半導體晶粒152的輸入/輸出端。
在一些實施例中，可在半導體晶粒152的主動面AS1、包封體156的前側表面156a以及包封體穿孔154的背向上覆的半導體封裝10的前側表面上形成前側重佈線結構158。前側重佈線結構158包括重佈線單元160以及至少一介電層162。重佈線單元160埋入於介電層162中，且電性連接於半導體晶粒152的輸入/輸出端（例如是導電柱153）與包封體穿孔154。需注意的是，圖2J僅示意性地繪示重佈線單元160。實際上重佈線單元160可包括導電跡線、導電通孔或其組合。藉由設置前側重佈線結構158，半導體晶粒152的輸入/輸出端（例如是導電柱153）可被擴展地配線（out rout）至包括半導體晶粒152與包封體156的重構晶圓之範圍。在一些實施例中，可在前側重佈線結構158的表面（亦即圖2J所示的前側重佈線結構158的底面）上形成前側導電連接件164。前側導電連接件164電性連接於形成在前側重佈線結構158中的重佈線單元160。在一些實施例中，前側導電連接件164可包括受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、焊料凸塊（solder bump）、球柵陣列（ball grid array，BGA）、其類似者或其組合。再者，在一些實施例中，前側導電連接件164附接於封裝基板166。如此一來，前側導電連接件164連接於前側重佈線結構158與封裝基板166之間。在一些實施例中，封裝基板166可為印刷電路板（printed circuit board，PCB），例如是具有核心層的印刷電路板（core PCB）或不具有核心層的印刷電路板（coreless PCB）。
在一些實施例中，可在包封體156的背側表面156b以及包封體穿孔154的面向半導體封裝10的背側表面上形成背側重佈線結構168。背側重佈線結構168包括重佈線單元170以及至少一介電層172。重佈線單元170埋入於介電層172中，且電性連接於包封體穿孔154。在半導體晶粒152的背側背側表面BS1埋入於包封體156的實施例中，背側重佈線結構168的重佈線單元170並非直接電性連接於半導體晶粒152，而可經由包封體穿孔154與前側重佈線結構158而電性連接於半導體晶粒152。需注意的是，圖2J僅示意性地繪示重佈線單元170。實際上重佈線單元170可包括導電跡線、導電通孔或其組合。在一些實施例中，可在背側重佈線結構168的表面（亦即圖2J所示的背側重佈線結構168的上表面）上形成背側導電連接件174。背側導電連接件174電性連接於形成在背側重佈線結構168中的重佈線單元170。在一些實施例中，藉由接合半導體封裝10的前側導電連接件132與底部半導體封裝150的背側導電連接件174來實現半導體封裝10與底部半導體封裝150的電性連接。在一些實施例中，背側導電連接件174可包括受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、焊料凸塊（solder bump）、球柵陣列（ball grid array，BGA）、其類似者或其組合。
請參照圖1與圖2K，進行步驟S126，以將頂部半導體封裝180附接至半導體封裝10上。在一些實施例中，頂部半導體封裝180包括彼此堆疊的多個半導體晶粒182、基底184以及包封體186。彼此堆疊的多個半導體晶粒182設置於基底184上，且包封體186包封此些半導體晶粒182。在一些實施例中，半導體晶粒182包括邏輯晶粒、記憶體晶粒（例如是低功率記憶體晶粒）、其類似者或其組合。可在基底184中形成內連線單元188，且半導體晶粒182中的半導體元件（未繪示）可經由焊線（bonding wire）190電性連接於內連線單元188。在一些實施例中，在基底184的面向半導體封裝10的表面上形成導電連接件192，且導電連接件192電性連接於基底184中的內連線單元188。在一些實施例中，可藉由接合頂部半導體封裝180的導電連接件192與半導體封裝10的背側導電連接件144來實現頂部半導體封裝180與半導體封裝10之間的電性連接。舉例而言，導電連接件192可包括受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、焊料凸塊（solder bump）、球柵陣列（ball grid array，BGA）、其類似者或其組合。
至此，已形成包括中間半導體封裝（亦即半導體封裝10）、底部半導體封裝150與頂部半導體封裝180的半導體封裝堆疊20，且半導體封裝堆疊20可視為層疊式封裝（package-on-package，POP）結構。半導體封裝10堆疊於頂部半導體封裝180與底部半導體封裝150之間，且包括包封體穿孔122與半導體貫孔120兩者。在半導體封裝10中，包封體穿孔122貫穿側向環繞半導體晶粒100的包封體124，而半導體貫孔120由半導體晶粒100的背側至半導體晶粒100的主動側而貫穿半導體晶粒100。如此一來，可藉由包封體穿孔122來實現頂部半導體封裝180與底部半導體封裝150之間的通訊。在一些實施例中，包封體穿孔122經由半導體封裝10的背側重佈線結構138與背側導電連接件133而電性連接至頂部半導體封裝180，且經由半導體封裝10的前側重佈線結構126與前側導電連接件132而電性連接至底部半導體封裝150。另一方面，訊號可從半導體晶粒100的背側經由背側重佈線結構138與半導體貫孔120而傳輸到半導體晶粒100的主動側，而並未行經包封體穿孔122以及設置於半導體晶粒100的主動側的前側重佈線結構126，且反之亦然。如此一來，可縮短在半導體晶粒100的背側與主動側之間的訊號傳輸路徑。此外，可降低半導體封裝10的前側重佈線結構126的配線密度，且可提高半導體封裝10的可靠度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、150、180:半導體封裝 20:半導體封裝堆疊 100、152、182:半導體晶粒 102:半導體基底 104:元件層 106:半導體元件 108:內連線層 110、188:內連線單元 112:導電接墊 114、153:導電柱 116:保護層 118:絕緣材料 120:半導體貫孔 122、154:包封體穿孔 124、156、186:包封體 124a、156a:前側表面 124b、156b:背側表面 126、158:前側重佈線結構 128、140、162、172:介電層 130、142、160、170:重佈線單元 132、164:前側導電連接件 134、146:凸塊下金屬層 136:黏著層 138、168、174:背側重佈線結構 144:背側導電連接件 184:基底 190:焊線 192:導電連接件 AS、AS1:主動面 BS、BS1:背側表面 CA1:第一載體 CA2:第二載體 S100、S102、S104、S106、S108、S110、S112、S114、S116、S118、S120、S122、S124、S126:步驟 TP:膠帶
圖1是依照本發明一些實施例的半導體封裝的製造方法的流程圖。 圖2A至圖2K是依照本發明一些實施例的半導體封裝的製造方法中各階段的結構的剖視示意圖。
10:半導體封裝
100:半導體晶粒
102:半導體基底
108:內連線層
120:半導體貫孔
122:包封體穿孔
124:包封體
124a:前側表面
124b:背側表面
126:前側重佈線結構
128、140:介電層
130、142:重佈線單元
132:前側導電連接件
134、146:凸塊下金屬層
138:背側重佈線結構
144:背側導電連接件
AS:主動面
BS:背側表面

Claims (20)

  1. 一種半導體封裝，包括：半導體晶粒，包括：半導體基底，具有彼此相對的主動面與背側表面；內連線層，設置於所述半導體基底的所述主動面上；以及半導體貫孔，由所述半導體基底的所述背側表面至所述半導體基底的所述主動面貫穿所述半導體基底；包封體，側向包封所述半導體晶粒；包封體穿孔，貫穿所述包封體；以及前側重佈線結構，設置於所述內連線層與所述包封體的前側表面上，其中所述前側重佈線結構包括重佈線單元，所述重佈線單元的一部分電性連接於所述內連線層，所述重佈線單元的另一部分電性連接於所述包封體穿孔，且其中所述包封體穿孔並未經由所述前側重佈線結構而直接電性連接於所述半導晶粒。
  2. 如申請專利範圍第1項所述的半導體封裝，更包括：背側重佈線結構，設置於所述半導體基底的所述背側表面與所述包封體的背側表面上，其中所述包封體的所述背側表面相對於所述包封體的所述前側表面，且所述背側重佈線結構電性連接於所述半導體貫孔以及所述包封體穿孔。
  3. 如申請專利範圍第2項所述的半導體封裝，更包括：前側導電連接件，設置於所述前側重佈線結構上，且電性連 接於所述前側重佈線結構；以及背側導電連接件，設置於所述背側重佈線結構上，且電性連接於所述背側重佈線結構。
  4. 如申請專利範圍第1項所述的半導體封裝，其中所述包封體的背側表面實質上共面於所述半導體基底的所述背側表面。
  5. 如申請專利範圍第1項所述的半導體封裝，其中所述包封體的所述前側表面實質上共面於所述半導體晶粒的前側表面，所述半導體基底的所述主動面面向所述半導體晶粒的所述前側表面，且所述半導體基底的所述背側表面背向所述半導體晶粒的所述前側表面。
  6. 如申請專利範圍第1項所述的半導體封裝，其中所述半導體晶粒包括記憶體晶粒。
  7. 一種半導體封裝堆疊，包括：如申請專利範圍第1項至第6項中的任一項所述的半導體封裝；底部半導體封裝，附接至所述半導體封裝的底面，且電性連接於所述內連線層與所述包封體穿孔；以及頂部半導體封裝，附接至所述半導體封裝的頂面，且電性連接於所述半導體貫孔以及所述包封體穿孔。
  8. 如申請專利範圍第7項所述的半導體封裝堆疊，其中所述底部半導體封裝包括：底部半導體晶粒； 底部包封體，包封所述底部半導體晶粒；以及底部包封體穿孔，貫穿所述底部包封體，且電性連接於所述半導體封裝的所述包封體穿孔。
  9. 如申請專利範圍第8項所述的半導體封裝堆疊，其中所述底部半導體晶粒的頂面埋入於所述底部包封體中，所述底部半導體晶粒的底面實質上共面於所述底部包封體的底面。
  10. 如申請專利範圍第7項所述的半導體封裝堆疊，更包括：封裝基底，附接至所述底部半導體封裝的底面。
  11. 一種半導體封裝的製造方法，包括：提供半導體晶粒，其中所述半導體晶粒包括半導體基底、內連線層以及半導體貫孔，所述內連線層設置於所述半導體基底的主動面上，所述半導體貫孔由所述半導體基底的背側表面至所述半導體基底的主動面而貫穿所述半導體基底；以包封體側向包封所述半導體晶粒；形成貫穿所述包封體的包封體穿孔；以及在所述內連線層與所述包封體的前側表面上形成前側重佈線結構，其中所述前側重佈線結構包括重佈線單元，所述重佈線單元的一部分電性連接於所述內連線層，所述重佈線單元的另一部分電性連接於所述包封體穿孔，且其中所述包封體穿孔並未經由所述前側重佈線結構而直接電性連接於所述半導體晶粒。
  12. 如申請專利範圍第11項所述的半導體封裝的製造方法，更包括：在形成所述包封體之前將所述半導體晶粒附接至第一載體上，其中所述半導體基底的所述背側表面面向所述第一載體，且所述半導體基底的所述主動面背向所述第一載體；以及在形成所述包封體與所述包封體穿孔之後分離所述第一載體。
  13. 如申請專利範圍第12項所述的半導體封裝的製造方法，其中形成所述包封體穿孔的步驟在形成所述包封體的步驟之前。
  14. 如申請專利範圍第13項所述的半導體封裝的製造方法，其中形成所述包封體、將所述半導體晶粒附接至所述第一載體以及形成所述包封體穿孔的步驟包括：在所述第一載體的表面上形成包封體穿孔；將所述半導體晶粒附接至所述第一載體的所述表面上；以及以所述包封體側向包封所述半導體晶粒與所述包封體穿孔。
  15. 如申請專利範圍第12項所述的半導體封裝的製造方法，其中形成所述包封體穿孔的步驟在形成所述包封體的步驟之後。
  16. 如申請專利範圍第15項所述的半導體封裝的製造方法，其中將所述半導體晶粒附接至所述第一載體、形成所述包封體、以及形成所述包封體穿孔的步驟包括： 將所述半導體晶粒附接至所述第一載體的表面上；以所述包封體側向包封所述半導體晶粒；移除所述包封體的一部分，以在所述包封體中形成穿孔；以及在所述穿孔中填入導體材料，以形成所述包封體穿孔。
  17. 如申請專利範圍第11項所述的半導體封裝的製造方法，更包括：在所述前側重佈線結構上形成前側導電連接件，其中所述前側導電連接件電性連接於所述前側重佈線結構。
  18. 如申請專利範圍第12項所述的半導體封裝的製造方法，在形成所述包封體與所述包封體穿孔之後，更包括：將第二載體附接至所述包封體、所述半導體晶粒與所述包封體穿孔的背向所述第一載體的表面。
  19. 如申請專利範圍第18項所述的半導體封裝的製造方法，更包括：在所述半導體基底的所述背側表面與所述包封體的背側表面上形成背側重佈線結構，其中所述背側重佈線結構電性連接於所述半導體貫孔以及所述包封體穿孔；在所述背側重佈線結構上形成背側導電連接件，其中所述背側導電連接件電性連接於所述背側重佈線結構；以及分離所述第二載體。
  20. 一種半導體封裝堆疊的製造方法，包括： 如申請專利範圍第11項至第19項中的任一項所述的半導體封裝的製造方法；將頂部半導體封裝附接至所述半導體封裝的頂面，其中所述頂部半導體封裝電性連接於所述半導體貫孔與所述包封體穿孔；以及將底部半導體封裝附接至所述半導體封裝的底面，其中所述底部半導體封裝電性連接於所述內連線層與所述包封體穿孔。
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