CN111524878A - 半导体封装、半导体封装堆叠及其制造方法 - Google Patents

半导体封装、半导体封装堆叠及其制造方法 Download PDF

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Publication number
CN111524878A
CN111524878A CN201910404765.4A CN201910404765A CN111524878A CN 111524878 A CN111524878 A CN 111524878A CN 201910404765 A CN201910404765 A CN 201910404765A CN 111524878 A CN111524878 A CN 111524878A
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semiconductor
encapsulant
semiconductor package
hole
backside
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施信益
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本发明提供一种半导体封装、半导体封装堆叠及其制造方法。半导体封装包括半导体晶粒、包封体以及包封体穿孔。半导体晶粒包括半导体基底、内连线层与半导体贯孔。半导体基底具有彼此相对的主动面与背侧表面。内连线层设置于半导体基底的主动面上。半导体贯孔由半导体基底的背侧表面至半导体基底的主动面而贯穿半导体基底。包封体侧向包封半导体晶粒。包封体穿孔贯穿包封体。

Description

半导体封装、半导体封装堆叠及其制造方法
技术领域
本发明涉及一种半导体封装及其制造方法，尤其涉及一种三维半导体封装及其制造方法。
背景技术
随着对于电子元件的微缩的要求不断提高，逐渐产生了对于更小且更新颖的半导体晶粒的封装技术的需求。举例而言，层叠式封装(package-on-package，POP)属于上述封装技术的其中一种。层叠式封装包括多个彼此堆叠的半导体封装，且可视为一种三维半导体封装。在典型的叠层式封装中，中间半导体封装设置于顶部半导体封装与底部半导体封装之间。目前来说，需通过中间半导体封装的前侧重布线层(front-side redistributionlayer，RDL)来实现中间半导体封装与顶部半导体封装之间的信号传输以及中间半导体封装与底部半导体封装之间的信号传输。因此，前侧重布线层的布线密度非常高，且封装结构的可靠度可能会受到影响。
发明内容
本发明提供一种层叠式半导体封装，具有较佳的可靠度。此外，本发明亦提供此层叠式半导体封装的制造方法。
本发明实施例的半导体封装包括半导体晶粒、包封体与包封体穿孔。半导体晶粒包括半导体基底、内连线层以及半导体贯孔。半导体基底具有彼此相对的主动面与背侧表面。内连线层设置于半导体基底的主动面上。半导体贯孔由半导体基底的背侧表面至半导体基底的主动面贯穿半导体基底。包封体侧向包封半导体晶粒。包封体穿孔贯穿包封体。
在一些实施例中，半导体封装还包括前侧重布线结构以及背侧重布线结构。前侧重布线结构设置于内连线层与包封体的前侧表面上。前侧重布线结构电性连接于内连线层与包封体穿孔。背侧重布线结构设置于半导体基底的背侧表面与包封体的背侧表面上。包封体的背侧表面相对于包封体的前侧表面，且背侧重布线结构电性连接于半导体贯孔与包封体穿孔。
在一些实施例中，半导体封装还包括前侧导电连接件以及背侧导电连接件。前侧导电连接件设置于前侧重布线结构上，且电性连接于前侧重布线结构。背侧导电连接件设置于背侧重布线结构上，且电性连接于背侧重布线结构。
在一些实施例中，包封体的背侧表面实质上共面于半导体基底的背侧表面。
在一些实施例中，包封体的前侧表面实质上共面于半导体晶粒的前侧表面。半导体基底的主动面面向半导体晶粒的前侧表面，且半导体基底的背侧表面背向半导体晶粒的前侧表面。
在一些实施例中，半导体晶粒包括存储器晶粒。
本发明实施例的半导体封装堆叠包括如上所述的半导体封装、底部半导体封装以及顶部半导体封装。底部半导体封装附接至半导体封装的底面，且电性连接于内连线层与包封体穿孔。顶部半导体封装附皆至半导体封装的顶面，且电性连接于半导体贯孔与包封体穿孔。
在一些实施例中，底部半导体封装包括底部半导体晶粒、底部包封体与底部包封体穿孔。底部包封体包封底部半导体晶粒。底部包封体穿孔贯穿底部包封体，且电性连接于半导体封装的包封体穿孔。
在一些实施例中，底部半导体晶粒的顶面埋入于底部包封体中，底部半导体晶粒的底面实质上共面于底部包封体的底面。
在一些实施例中，半导体封装堆叠还包括封装基底。封装基底附接至底部半导体封装的底面。
本发明实施例的半导体封装的制造方法包括：提供半导体晶粒，其中半导体晶粒包括半导体基底、内连线层以及半导体贯孔，内连线层设置于半导体基底的主动面上，半导体贯孔由半导体基底的背侧表面至半导体基底的主动面而贯穿半导体基底；以包封体侧向包封半导体晶粒；以及形成贯穿包封体的包封体穿孔。
在一些实施例中，半导体封装的制造方法还包括：在形成包封体之前将半导体晶粒附接至第一载体上，其中半导体基底的背侧表面面向第一载体，且半导体基底的主动面背向第一载体；以及在形成包封体与包封体穿孔之后分离第一载体。
在一些实施例中，形成包封体穿孔的步骤在形成包封体的步骤之前。
在一些实施例中，形成包封体、将半导体晶粒附接至第一载体以及形成包封体穿孔的步骤包括：在第一载体的表面上形成包封体穿孔；将半导体晶粒附接至第一载体的表面上；以及以包封体侧向包封半导体晶粒与包封体穿孔。
在一些实施例中，形成包封体穿孔的步骤在形成包封体的步骤之后。
在一些实施例中，将半导体晶粒附接至第一载体、形成包封体、以及形成包封体穿孔的步骤包括：将半导体晶粒附接至第一载体的表面上；以包封体侧向包封半导体晶粒；移除包封体的一部分，以在包封体中形成穿孔；以及在穿孔中填入导体材料，以形成包封体穿孔。
在一些实施例中，半导体封装的制造方法还包括：在内连线层与包封体的前侧表面上形成前侧重布线结构，其中前侧重布线结构电性连接于内连线层与包封体穿孔；以及在前侧重布线结构上形成前侧导电连接件，其中前侧导电连接件电性连接于前侧重布线结构。
在一些实施例中，在形成包封体与包封体穿孔之后，还包括：将第二载体附接至包封体、半导体晶粒与包封体穿孔的背向第一载体的表面。
在一些实施例中，半导体封装的制造方法还包括：在半导体基底的背侧表面与包封体的背侧表面上形成背侧重布线结构，其中背侧重布线结构电性连接于半导体贯孔以及包封体穿孔；在背侧重布线结构上形成背侧导电连接件，其中背侧导电连接件电性连接于背侧重布线结构；以及分离第二载体。
本发明实施例的半导体封装堆叠的制造方法包括：如上所述的半导体封装的制造方法；将顶部半导体封装附接至半导体封装的顶面，其中顶部半导体封装电性连接于半导体贯孔与包封体穿孔；以及将底部半导体封装附接至半导体封装的底面，其中底部半导体封装电性连接于内连线层与包封体穿孔。
基于上述，本发明实施例的半导体封装包括包封体穿孔与半导体贯孔两者。包封体穿孔贯穿侧向环绕半导体晶粒的包封体，而半导体贯孔由半导体晶粒的背侧至半导体晶粒的主动侧而贯穿半导体晶粒。半导体封装堆叠于顶部半导体封装与底部半导体封装之间时，可通过包封体穿孔来实现顶部半导体封装与底部半导体封装之间的通讯。另一方面，信号可从半导体晶粒的背侧(例如是由顶部半导体封装)经由半导体贯孔而传输到半导体晶粒的主动侧，而并未行经包封体穿孔以及设置于半导体晶粒的主动侧的前侧重布线结构，且反之亦然。如此一来，可缩短在半导体晶粒的背侧与主动侧之间的信号传输路径。此外，可降低半导体封装的前侧重布线结构的配线密度，且可提高半导体封装的可靠度。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1是依照本发明一些实施例的半导体封装的制造方法的流程图。
图2A至图2K是依照本发明一些实施例的半导体封装的制造方法中各阶段的结构的剖视示意图。
具体实施方式
图1是依照本发明一些实施例的半导体封装的制造方法的流程图。图2A至图2K是依照本发明一些实施例的半导体封装的制造方法中各阶段的结构的剖视示意图。
请参照图1与图2A，进行步骤S100，以提供半导体晶粒100。在一些实施例中，半导体晶粒100可为存储器晶粒，例如是动态随机存取存储器(dynamic random accessmemory，DRAM)晶粒。半导体晶粒100包括半导体基底102以及设置于半导体基底102上的元件层104。半导体基底102可为半导体晶圆或绝缘体上覆半导体(semiconductor-on-insulator，SOI)晶圆。半导体晶圆或SOI晶圆的半导体材料可包括元素半导体、合金半导体或化合物半导体。举例而言，元素半导体可包括Si或Ge。合金半导体可包括SiGe、SiGeC或其类似者，而化合物半导体可包括SiC、III-V族半导体或II-VI族半导体。半导体基底102具有主动面AS与相对于主动面AS的背侧表面BS。元件层104形成于半导体基底102的主动面AS上。一部分的半导体元件106形成于元件层104，而半导体元件106的其他部分(未示出)可埋入于半导体基底102中。在一些实施例中，半导体元件106可包括存储器元件。举例而言，半导体元件106可包括晶体管、电容、其类似者或其组合。
内连线层108设置于元件层104上。多个内连线单元110形成于内连线层108中，且电性连接于下伏的半导体元件106。举例而言，内连线单元110可包括导电通孔、导电迹线或其组合。此外，可于内连线层108上形成导电接垫112。导电接垫112电性连接于内连线单元110。在一些实施例中，于导电接垫112上形成至少一保护层116，且上述至少一保护层116具有至少局部地暴露出导电接垫112的前侧表面(亦即图2A所示的导电接垫112的上表面)的开口。可于保护层116上形成导电柱114，且导电柱114延伸至保护层116的上述开口中，以电性连接于导电接垫112。在一些实施例中，绝缘材料118可侧向地环绕导电柱114的突出于保护层116的一些部分。在此些实施例中，绝缘材料118的前侧表面(亦即图2A所示的绝缘材料118的上表面)可实质上共面于导电柱114的前侧表面(亦即图2A所示的导电柱114的上表面)。在替代实施例中，导电柱114的前侧表面此时被绝缘材料118覆盖，且将在后续步骤(例如是步骤S108)中对半导体晶粒100以及侧向环绕半导体晶粒100的包封体(例如是图2D所示的包封体124)进行平坦化制程时被暴露出来。
此外，半导体晶粒100亦包括半导体贯孔(through semiconductor via，TSV)120。半导体贯孔120由半导体基底102的背侧表面BS至半导体基底102的主动面AS而贯穿半导体基底102，且电性连接于形成在内连线层108中的内连线单元110。如图2A所示，在一些实施例中，半导体贯孔120还贯穿元件层104，且接触于内连线层108。在此些实施例中，是以中段穿孔制程(TSV-middle process)形成半导体晶粒100。换言之，形成半导体贯孔120的步骤是在形成元件层104之后，而在形成内连线层108之前。通过设置半导体贯孔120，信号可从半导体基底102的背侧表面BS经由半导体贯孔120与内连线单元110而传输到设置于半导体基底102的主动面AS上的半导体元件106。在一些实施例中，半导体元件106位于半导体晶粒100的中心区域，而半导体贯孔120设置于半导体晶粒100的边缘区域中。
在替代实施例中，半导体贯孔120的前侧表面(亦即图2A所示的半导体贯孔120的上表面)实质上共面于半导体基底102的主动面AS，且半导体贯孔120可通过导电插塞(未示出)而电性连接于内连线单元110。导电插塞(未示出)由半导体贯孔120的前侧表面延伸至元件层104的前侧表面(亦即图2A所示的元件层104的上表面)。在此些替代实施例中，是以先穿孔制程(TSV-first process)形成半导体晶粒100。换言之，形成半导体贯孔120的步骤是在形成元件层104与内连线层108的步骤之前。在其他实施例中，半导体贯孔120可实质上贯穿整个半导体晶粒100。在此些实施例中，是以后穿孔制程(TSV-last process)形成半导体晶粒100，且形成半导体贯孔120的步骤是在形成元件层104与内连线层108的步骤之后。
请参照图1与图2B，进行步骤S102，以提供第一载体CA1。在一些实施例中，第一载体CA1为玻璃载板。此外，可在第一载体CA1的将在后续步骤中附接半导体晶粒100的表面上形成粘着层(未示出)。在一些实施例中，粘着层可为光热转换(light-to-heat-conversion，LTHC)层、热离形层(thermal release layer)或其类似者。
在一些实施例中，进行步骤S104，以在第一载体CA1上形成包封体穿孔122(也可称为中介体穿孔(through interposer via，TIV))。在第一载体CA1上预先形成有粘着层的实施例中，此粘着层位于包封体穿孔122与第一载体CA1之间。包封体穿孔122可为导电柱。在一些实施例中，包封体穿孔122的形成方法包括在第一载体CA1上形成全面性披覆的晶种层(未示出)。随后，在晶种层上形成具有定义出包封体穿孔122的位置与尺寸的开口的光阻图案(未示出)。接着，通过例如是镀覆制程而在光阻图案的开口中填入导体材料，以形成包封体穿孔122。最后，通过例如是剥除制程(stripping process)或灰化制程(ashingprocess)移除光阻图案。
请参照图1与图2C，进行步骤S106，以将多个半导体晶粒100附接至第一载体CA1上。附接至第一载体CA1上的半导体晶粒100面向上方。也就是说，半导体基底102的背侧表面BS面向第一载体CA1，而半导体基底102的主动面AS背向第一载体CA1。在一些实施例中，包封体穿孔122是预先形成于第一载体CA1上，且一些相邻的包封体穿孔122之间具有适当的间距，以使此些相邻包封体穿孔122之间的空间可容纳至少一半导体晶粒100。举例而言，如图2C所示，4个半导体晶粒100附接至第一载体CA1上，且两两分别位于相邻的包封体穿孔122之间。然而，所属领域中技术人员可改变附接至第一载体CA1的半导体晶粒100的数量以及包封体穿孔122与半导体晶粒100的配置，本发明并不以此为限。在一些实施例中，通过取放制程(pick-and-place process)而将半导体晶粒100附接至第一载体CA1上。在此些实施例中，预先形成的包封体穿孔122可在取放制程期间作为对位标记。
请参照图1与图2D，进行步骤S108，以包封体124包封半导体晶粒100。如此一来，形成包括半导体晶粒100与包封体124的重构晶圆(reconstructed wafer)。在包封体穿孔122预先形成于第一载体CA1上的实施例中，包封体穿孔122与半导体晶粒100两者均被包封体124包封。包封体穿孔122可视为贯穿包封体124。在一些实施例中，可以包封材料包覆(overmold)包封体穿孔122与半导体晶粒100，使包封体穿孔122与半导体晶粒100埋入于此包封材料中。随后，可对此包封材料进行平坦化制程，以暴露出包封体穿孔122与半导体晶粒100的导电柱114的前侧表面(亦即图2D所示的包封体穿孔122与导电柱114的上表面)。包封材料的残留部分形成包封体124。在一些实施例中，包封体124的前侧表面124a实质上共面于包封体穿孔122与导电柱114的前侧表面。另一方面，包封体124的背侧表面124b实质上共面于包封体穿孔122的底面以及半导体基底102的背侧表面BS。举例而言，平坦化制程包括化学机械研磨(chemical mechanical polishing，CMP)制程或蚀刻制程。
在替代实施例中，形成包封体124的步骤(亦即步骤S108)在形成包封体穿孔122的步骤(亦即步骤S104)之前。在此些替代实施例中，于步骤S108中以包封体124包封半导体晶粒100。随后，于步骤S104中移除包封体124的一些部分以在包封体124中形成穿孔，且在包封体124的穿孔中填入导体材料，而形成包封体穿孔122。在一些实施例中，包封体124的材料为光敏材料(photosensitive material)，且可通过微影制程以在包封体124中形成穿孔。在其他实施例中，包封体124并非由光敏材料构成，且通过微影制程与蚀刻制程以在包封体124中形成穿孔。
请参照图1与图2E，进行步骤S110，以在如图2D所示的重构晶圆上形成前侧重布线结构126。如此一来，前侧重布线结构126覆盖此重构晶圆的背向第一载体CA1的前侧表面(亦即图2D所示的重构晶圆的上表面)。换言之，前侧重布线结构126覆盖包封体124的前侧表面124a以及导电柱114与包封体穿孔122的前侧表面。在一些实施例中，前侧重布线结构126包括彼此堆叠的多层介电层128(例如是4层介电层128)以及重布线单元130。然而，所属领域中技术人员可改变前侧重布线结构126的介电层128的数量，本发明并不以此为限。重布线单元130形成于介电层128的堆叠结构中。此外，重布线单元130的一些部分经由导电柱114而电性连接于半导体晶粒100的内连线层108，而重布线单元130的另一些部分电性连接于包封体穿孔122。在一些实施例中，重布线单元130包括导电通孔、导电迹线或其组合。通过设置前侧重布线结构126，半导体晶粒100的输入/输出端(例如是导电柱114)可被扩展地配线(out rout)至含有被包封体124侧向包封的半导体晶粒100的重构晶圆的范围。
进行步骤S112，以在前侧重布线结构126上形成前侧导电连接件132。前侧导电连接件132电性连接于位在前侧重布线结构126中的重布线单元130。在一些实施例中，前侧导电连接件132包括受控塌陷芯片连接(controlled collapse chip connection，C4)凸块、焊料凸块(solder bump)、球栅阵列(ball grid array，BGA)、导电柱、其类似者或其组合。前侧导电连接件132的形成方法可包括图案化前侧重布线结构126的最外侧介电层128，以在最外侧介电层128中形成多个开口。随后，分别于此些开口中形成前侧导电连接件132。在一些实施例中，可在形成前侧导电连接件132之前形成分别覆盖最外侧介电层128的多个开口的多个凸块下金属(under bump metallization，UBM)层134。在此些实施例中，在形成前侧导电连接件132之后，多个凸块下金属层134分别位于前侧导电连接件132与最外侧的重布线单元130之间，且位于前侧导电连接件132与最外侧介电层128之间。
请参照图1、图2E与图2F，进行步骤S114，以将第二载体CA2附接至目前封装结构(如图2E所示)的背向第一载体CA1的前侧表面。此外，翻转目前的结构，且将第一载体CA1自目前的封装结构分离。在一些实施例中，第二载体CA2附接至封装结构的前侧导电连接件132。再者，在一些实施例中，粘着层136预先形成于第二载体CA2的附接于前侧导电连接件132的表面上。如此一来，在第二载体CA2附接于前侧导电连接件132之后，粘着层136位于前侧导电连接件132与第二载体CA2之间。在一些实施例中，通过层压制程(laminationprocess)将第二载体CA2附接至封装结构上，且前侧导电连接件132可能埋入于粘着层136中。据此，粘着层136可填于前侧重布线结构126与第二载体CA2之间的空间中。举例而言，第二载体CA2为玻璃载体。在分离第一载体CA1之后，暴露出半导体基底102的背侧表面BS、包封体124的背侧表面124b以及包封体穿孔122与半导体贯孔120的背向第二载体CA2的背侧表面(亦即图2F所示的包封体穿孔122与半导体贯孔120的上表面)。在一些实施例中，第一载体CA1上预先形成有粘着层(未示出，且例如是光热转换层或热离形层)，且通过对粘着层照射光或热而使粘着层失去黏性，而使得形成有粘着层的第一载体CA1自封装结构分离。
请参照图1、图2F与图2G，进行步骤S116，以在图2F所示的封装结构的暴露表面上形成背侧重布线结构138。如此一来，背侧重布线结构138覆盖半导体基底102的背侧表面BS、包封体124的背侧表面124b以及包封体穿孔122与半导体贯孔120的背向第二载体CA2的背侧表面。在一些实施例中，背侧重布线结构138包括彼此堆叠的多层介电层140(例如是4层介电层140)以及重布线单元142。然而，所属领域中技术人员可改变背侧重布线结构138的介电层140的数量，本发明并不以此为限。重布线单元142形成于介电层140的堆叠结构中。此外，重布线单元142的一些部分电性连接于半导体晶粒100的半导体贯孔120，而重布线单元142的另一些部分电性连接于包封体穿孔122。如此一来，半导体贯孔120电性连接于内连线层108与背侧重布线结构138之间，而包封体穿孔122电性连接于前侧重布线结构126与背侧重布线结构138之间。在一些实施例中，重布线单元142包括导电通孔、导电迹线或其组合。
进行步骤S118，以在背侧重布线结构138上形成背侧导电连接件144。背侧导电连接件144电性连接于位在背侧导重布线结构138中的重布线单元142。在一些实施例中，背侧导电连接件144包括受控塌陷芯片连接(controlled collapse chip connection，C4)凸块、焊料凸块(solder bump)、球栅阵列(ball grid array，BGA)、导电柱、其类似者或其组合。背侧导电连接件144的形成方法可包括图案化背侧重布线结构138的最外侧介电层140，以在最外侧介电层140中形成多个开口。随后，分别于此些开口中形成背侧导电连接件144。在一些实施例中，可在形成背侧导电连接件144之前形成分别覆盖最外侧介电层140的多个开口的多个凸块下金属(under bump metallization，UBM)层146。在此些实施例中，在形成背侧导电连接件144之后，多个凸块下金属层146分别位于背侧导电连接件144与最外侧的重布线单元142之间，且位于背侧导电连接件144与最外侧介电层140之间。
请参照图1、图2G与图2H，进行步骤S120，以分离第二载体CA2。如此一来，暴露出目前封装结构的前侧表面与背侧表面。在一些实施例中，目前封装结构的前侧表面包括前侧导电连接件132与前侧重布线结构126的表面，而目前封装结构的背侧表面包括背侧导电连接件144与背侧重布线结构138的表面。在一些实施例中，预先形成于第二载体CA2上的粘着层136为光热转换层或热离形层，且通过对粘着层照射光或热而使粘着层136失去黏性，而使得形成有粘着层136的第二载体CA2自封装结构分离。在一些实施例中，在分离第二载体CA2之后，可将目前的封装结构附接于胶带TP。举例而言，翻转目前的封装结构，且使前侧导电连接件132附接至胶带TP。在一些实施例中，胶带TP连接于框架(未示出)。
请参照图1、图2H与图2I，进行步骤S122，以对目前的封装结构进行单体化制程。多个经单体化的封装结构分别称作半导体封装10。各半导体封装10包括至少一半导体晶粒100以及位于半导体晶粒100周围的包封体穿孔122。在一些实施例中，单体化制程包括锯切制程(sawing process)、激光剥蚀制程(laser ablation process)、蚀刻制程、其类似者或其组合。
请参照图1、图2I与图2J，进行步骤S124，以将半导体封装10附接至底部半导体封装150上。在一些实施例中，底部半导体封装150包括半导体晶粒152、包封体穿孔154以及包封体156。包封体穿孔154围绕半导体晶粒152。此外，包封体156包封半导体晶粒152与包封体穿孔154。在一些实施例中，半导体晶粒152为逻辑晶粒，例如是控制器晶粒(controllerdie)。半导体晶粒152可面向下方。如此一来，半导体晶粒152的主动面(或称为前侧表面)AS1背向上覆的半导体封装10，而半导体晶粒152的背侧表面BS1面向半导体封装10。此外，半导体晶粒152的主动面AS1被包封体156暴露出来，而半导体晶粒152的背侧表面BS1则埋入于包封体156中。在一些实施例中，半导体晶粒152具有导电柱153，其暴露于半导体晶粒152的主动面AS1，并可作为半导体晶粒152的输入/输出端。
在一些实施例中，可在半导体晶粒152的主动面AS1、包封体156的前侧表面156a以及包封体穿孔154的背向上覆的半导体封装10的前侧表面上形成前侧重布线结构158。前侧重布线结构158包括重布线单元160以及至少一介电层162。重布线单元160埋入于介电层162中，且电性连接于半导体晶粒152的输入/输出端(例如是导电柱153)与包封体穿孔154。需注意的是，图2J仅示意性地示出重布线单元160。实际上重布线单元160可包括导电迹线、导电通孔或其组合。通过设置前侧重布线结构158，半导体晶粒152的输入/输出端(例如是导电柱153)可被扩展地配线(out rout)至包括半导体晶粒152与包封体156的重构晶圆的范围。在一些实施例中，可在前侧重布线结构158的表面(亦即图2J所示的前侧重布线结构158的底面)上形成前侧导电连接件164。前侧导电连接件164电性连接于形成在前侧重布线结构158中的重布线单元160。在一些实施例中，前侧导电连接件164可包括受控塌陷芯片连接(controlled collapse chip connection，C4)凸块、焊料凸块(solder bump)、球栅阵列(ball grid array，BGA)、其类似者或其组合。再者，在一些实施例中，前侧导电连接件164附接于封装基板166。如此一来，前侧导电连接件164连接于前侧重布线结构158与封装基板166之间。在一些实施例中，封装基板166可为印刷电路板(printed circuit board，PCB)，例如是具有核心层的印刷电路板(core PCB)或不具有核心层的印刷电路板(corelessPCB)。
在一些实施例中，可在包封体156的背侧表面156b以及包封体穿孔154的面向半导体封装10的背侧表面上形成背侧重布线结构168。背侧重布线结构168包括重布线单元170以及至少一介电层172。重布线单元170埋入于介电层172中，且电性连接于包封体穿孔154。在半导体晶粒152的背侧背侧表面BS1埋入于包封体156的实施例中，背侧重布线结构168的重布线单元170并非直接电性连接于半导体晶粒152，而可经由包封体穿孔154与前侧重布线结构158而电性连接于半导体晶粒152。需注意的是，图2J仅示意性地示出重布线单元170。实际上重布线单元170可包括导电迹线、导电通孔或其组合。在一些实施例中，可在背侧重布线结构168的表面(亦即图2J所示的背侧重布线结构168的上表面)上形成背侧导电连接件174。背侧导电连接件174电性连接于形成在背侧重布线结构168中的重布线单元170。在一些实施例中，通过接合半导体封装10的前侧导电连接件132与底部半导体封装150的背侧导电连接件174来实现半导体封装10与底部半导体封装150的电性连接。在一些实施例中，背侧导电连接件174可包括受控塌陷芯片连接(controlled collapse chipconnection，C4)凸块、焊料凸块(solder bump)、球栅阵列(ball grid array，BGA)、其类似者或其组合。
请参照图1与图2K，进行步骤S126，以将顶部半导体封装180附接至半导体封装10上。在一些实施例中，顶部半导体封装180包括彼此堆叠的多个半导体晶粒182、基底184以及包封体186。彼此堆叠的多个半导体晶粒182设置于基底184上，且包封体186包封此些半导体晶粒182。在一些实施例中，半导体晶粒182包括逻辑晶粒、存储器晶粒(例如是低功率存储器晶粒)、其类似者或其组合。可在基底184中形成内连线单元188，且半导体晶粒182中的半导体元件(未示出)可经由焊线(bonding wire)190电性连接于内连线单元188。在一些实施例中，在基底184的面向半导体封装10的表面上形成导电连接件192，且导电连接件192电性连接于基底184中的内连线单元188。在一些实施例中，可通过接合顶部半导体封装180的导电连接件192与半导体封装10的背侧导电连接件144来实现顶部半导体封装180与半导体封装10之间的电性连接。举例而言，导电连接件192可包括受控塌陷芯片连接(controlled collapse chip connection，C4)凸块、焊料凸块(solder bump)、球栅阵列(ball grid array，BGA)、其类似者或其组合。
至此，已形成包括中间半导体封装(亦即半导体封装10)、底部半导体封装150与顶部半导体封装180的半导体封装堆叠20，且半导体封装堆叠20可视为层叠式封装(package-on-package，POP)结构。半导体封装10堆叠于顶部半导体封装180与底部半导体封装150之间，且包括包封体穿孔122与半导体贯孔120两者。在半导体封装10中，包封体穿孔122贯穿侧向环绕半导体晶粒100的包封体124，而半导体贯孔120由半导体晶粒100的背侧至半导体晶粒100的主动侧而贯穿半导体晶粒100。如此一来，可通过包封体穿孔122来实现顶部半导体封装180与底部半导体封装150之间的通讯。在一些实施例中，包封体穿孔122经由半导体封装10的背侧重布线结构138与背侧导电连接件144而电性连接至顶部半导体封装180，且经由半导体封装10的前侧重布线结构126与前侧导电连接件132而电性连接至底部半导体封装150。另一方面，信号可从半导体晶粒100的背侧经由背侧重布线结构138与半导体贯孔120而传输到半导体晶粒100的主动侧，而并未行经包封体穿孔122以及设置于半导体晶粒100的主动侧的前侧重布线结构126，且反之亦然。如此一来，可缩短在半导体晶粒100的背侧与主动侧之间的信号传输路径。此外，可降低半导体封装10的前侧重布线结构126的配线密度，且可提高半导体封装10的可靠度。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视权利要求所界定的为准。

Claims (20)

1.一种半导体封装，其特征在于，包括：
半导体晶粒，包括：
半导体基底，具有彼此相对的主动面与背侧表面；
内连线层，设置于所述半导体基底的所述主动面上；以及
半导体贯孔，由所述半导体基底的所述背侧表面至所述半导体基底的所述主动面贯穿所述半导体基底；
包封体，侧向包封所述半导体晶粒；以及
包封体穿孔，贯穿所述包封体。
2.根据权利要求1所述的半导体封装，其特征在于，还包括：
前侧重布线结构，设置于所述内连线层与所述包封体的前侧表面上，其中所述前侧重布线结构电性连接于所述内连线层与所述包封体穿孔；以及
背侧重布线结构，设置于所述半导体基底的所述背侧表面与所述包封体的背侧表面上，其中所述包封体的所述背侧表面相对于所述包封体的所述前侧表面，且所述背侧重布线结构电性连接于所述半导体贯孔以及所述包封体穿孔。
3.根据权利要求2所述的半导体封装，其特征在于，还包括：
前侧导电连接件，设置于所述前侧重布线结构上，且电性连接于所述前侧重布线结构；以及
背侧导电连接件，设置于所述背侧重布线结构上，且电性连接于所述背侧重布线结构。
4.根据权利要求1所述的半导体封装，其特征在于，所述包封体的背侧表面实质上共面于所述半导体基底的所述背侧表面。
5.根据权利要求1所述的半导体封装，其特征在于，所述包封体的前侧表面实质上共面于所述半导体晶粒的前侧表面，所述半导体基底的所述主动面面向所述半导体晶粒的所述前侧表面，且所述半导体基底的所述背侧表面背向所述半导体晶粒的所述前侧表面。
6.根据权利要求1所述的半导体封装，其特征在于，所述半导体晶粒包括存储器晶粒。
7.一种半导体封装堆叠，其特征在于，包括：
如权利要求1至6任一项所述的半导体封装；
底部半导体封装，附接至所述半导体封装的底面，且电性连接于所述内连线层与所述包封体穿孔；以及
顶部半导体封装，附接至所述半导体封装的顶面，且电性连接于所述半导体贯孔以及所述包封体穿孔。
8.根据权利要求7所述的半导体封装堆叠，其特征在于，所述底部半导体封装包括：
底部半导体晶粒；
底部包封体，包封所述底部半导体晶粒；以及
底部包封体穿孔，贯穿所述底部包封体，且电性连接于所述半导体封装的所述包封体穿孔。
9.根据权利要求8所述的半导体封装堆叠，其特征在于，所述底部半导体晶粒的顶面埋入于所述底部包封体中，所述底部半导体晶粒的底面实质上共面于所述底部包封体的底面。
10.根据权利要求7所述的半导体封装堆叠，其特征在于，还包括：
封装基底，附接至所述底部半导体封装的底面。
11.一种半导体封装的制造方法，其特征在于，包括：
提供半导体晶粒，其中所述半导体晶粒包括半导体基底、内连线层以及半导体贯孔，所述内连线层设置于所述半导体基底的主动面上，所述半导体贯孔由所述半导体基底的背侧表面至所述半导体基底的主动面而贯穿所述半导体基底；
以包封体侧向包封所述半导体晶粒；以及
形成贯穿所述包封体的包封体穿孔。
12.根据权利要求11所述的半导体封装的制造方法，其特征在于，还包括：
在形成所述包封体之前将所述半导体晶粒附接至第一载体上，其中所述半导体基底的所述背侧表面面向所述第一载体，且所述半导体基底的所述主动面背向所述第一载体；以及
在形成所述包封体与所述包封体穿孔之后分离所述第一载体。
13.根据权利要求12所述的半导体封装的制造方法，其特征在于，形成所述包封体穿孔的步骤在形成所述包封体的步骤之前。
14.根据权利要求13所述的半导体封装的制造方法，其特征在于，形成所述包封体、将所述半导体晶粒附接至所述第一载体以及形成所述包封体穿孔的步骤包括：
在所述第一载体的表面上形成包封体穿孔；
将所述半导体晶粒附接至所述第一载体的所述表面上；以及
以所述包封体侧向包封所述半导体晶粒与所述包封体穿孔。
15.根据权利要求12所述的半导体封装的制造方法，其特征在于，形成所述包封体穿孔的步骤在形成所述包封体的步骤之后。
16.根据权利要求15所述的半导体封装的制造方法，其特征在于，将所述半导体晶粒附接至所述第一载体、形成所述包封体、以及形成所述包封体穿孔的步骤包括：
将所述半导体晶粒附接至所述第一载体的表面上；
以所述包封体侧向包封所述半导体晶粒；
移除所述包封体的一部分，以在所述包封体中形成穿孔；以及
在所述穿孔中填入导体材料，以形成所述包封体穿孔。
17.根据权利要求11所述的半导体封装的制造方法，其特征在于，还包括：
在所述内连线层与所述包封体的前侧表面上形成前侧重布线结构，其中所述前侧重布线结构电性连接于所述内连线层与所述包封体穿孔；以及
在所述前侧重布线结构上形成前侧导电连接件，其中所述前侧导电连接件电性连接于所述前侧重布线结构。
18.根据权利要求12所述的半导体封装的制造方法，其特征在于，在形成所述包封体与所述包封体穿孔之后，还包括：将第二载体附接至所述包封体、所述半导体晶粒与所述包封体穿孔的背向所述第一载体的表面。
19.根据权利要求18所述的半导体封装的制造方法，其特征在于，还包括：
在所述半导体基底的所述背侧表面与所述包封体的背侧表面上形成背侧重布线结构，其中所述背侧重布线结构电性连接于所述半导体贯孔以及所述包封体穿孔；
在所述背侧重布线结构上形成背侧导电连接件，其中所述背侧导电连接件电性连接于所述背侧重布线结构；以及
分离所述第二载体。
20.一种半导体封装堆叠的制造方法，其特征在于，包括：
如权利要求11至19任一项所述的半导体封装的制造方法；
将顶部半导体封装附接至所述半导体封装的顶面，其中所述顶部半导体封装电性连接于所述半导体贯孔与所述包封体穿孔；以及
将底部半导体封装附接至所述半导体封装的底面，其中所述底部半导体封装电性连接于所述内连线层与所述包封体穿孔。
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