CN115497929A - 半导体封装及其制造方法 - Google Patents
半导体封装及其制造方法 Download PDFInfo
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- CN115497929A CN115497929A CN202210137523.5A CN202210137523A CN115497929A CN 115497929 A CN115497929 A CN 115497929A CN 202210137523 A CN202210137523 A CN 202210137523A CN 115497929 A CN115497929 A CN 115497929A
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Abstract
本发明提供一种包括第一半导体晶粒、第二半导体晶粒、第一绝缘包封体、介电层结构、导体结构和第二绝缘包封体的半导体封装。第一半导体晶粒包括从半导体基底的第一侧延伸到第二侧的第一半导体基底和硅穿孔(TSV)。第二半导体晶粒设置在半导体基底的第一侧。第二半导体晶粒上的第一绝缘包封体封装了第一半导体晶粒。TSV的末端与第一绝缘包封体的表面共面。介电层结构覆盖了第一半导体晶粒和第一绝缘包封体。导体结构延伸穿过介电层结构并与硅穿孔接触。第二绝缘包封体与第二半导体晶粒、第一绝缘封装和介电层结构接触。
Description
技术领域
本发明涉及一种半导体封装及其制造方法。
背景技术
因为各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度不断提高,半导体行业经历了快速增长。在大多数情况下,集成密度的这种改进来自最小特征尺寸的反复减小,这允许将更多组件集成到给定的面积中。随着近来对小型化、更高速度和更大带宽以及更低功耗和延迟的需求不断增长,对更小、更具创意的半导体晶粒封装技术的需求也在增长。目前,系统整合集成电路(SoIC)组件因其多功能和紧凑性而变得越来越流行。然而,存在与SoIC组件的封装制程相关的挑战。
发明内容
根据揭露的一些实施例,提供包括第一半导体晶粒、第二半导体晶粒、第一绝缘包封体、介电层结构、导体结构和第二绝缘包封体的半导体封装。第一半导体晶粒包括第一半导体基底和硅穿孔。硅穿孔从半导体基底的第一侧延伸到半导体基底的第二侧,第一侧与第二侧相对。第二半导体晶粒设置在半导体基底的第一侧。第一绝缘包封体设置在第二半导体晶粒上并封装第一半导体晶粒。硅穿孔的末端与第一个绝缘包封体的表面共面。介电层结构覆盖了第一半导体晶粒和第一绝缘包封体。导体结构延伸穿过介电层结构并与硅穿孔接触。第二绝缘包封体侧向封装并与第二半导体晶粒、第一绝缘封装和介电层结构接触。在一些实施例中,第二绝缘包封体的表面与导体结构的表面共面。
根据揭露的一些其他实施例,提供了一种制造半导体封装的方法,包括以下步骤。具有硅穿孔的第一半导体基底连接到第二半导体基底。第一半导体基底使用第一绝缘包封体封装在第二半导体基底上。执行蚀刻制程以去除第一半导体基底的一部分直到露出硅穿孔的一部分而第一绝缘包封体被覆盖。在第一半导体基底和第一绝缘包封体上形成介电层结构。形成延伸穿过介电层结构并电连接到硅穿孔的导体结构。形成与第二半导体基底的侧壁边缘、第一绝缘包封体的侧壁边缘和介电层结构的侧壁边缘接触的第二绝缘包封体。
根据揭露的一些其他实施例,提供了一种制造半导体封装的方法,包括以下步骤。硅穿孔延伸穿过第一半导体基底形成半导体晶粒。第一半导体晶粒上形成介电层结构和导体结构,其中介电层结构覆盖第一半导体晶粒的第一侧,导体结构延伸穿过介电层结构与硅穿孔电连接。第一半导体晶粒在第一半导体晶粒的第二侧连接到第二半导体晶粒。第二侧与第一侧相对。第一半导体和介电层结构使用第二半导体晶粒上的第一绝缘包封体封装。第二半导体晶粒和第一绝缘包封体使用第二绝缘包封体封装。
附图说明
图1A至图1G是示意性地示出根据本揭露的一些实施例的用以制造半导体封装的制程流程的截面图。
图2A至图2I示意性地示出了根据本公开的一些实施例的图1C中所示的步骤的制程流程。
图3A至图3G示意性地示出了根据本公开的一些实施例的图1C中所示的步骤的制程流程。
图4A至图4E示意性地示出了根据本公开的一些实施例的图1C中所示的步骤的制程流程。
图5示意性地示出了根据本公开的一些实施例的图1G中的半导体封装的放大部分V。
图6A至图6L示意性地示出了根据本公开的一些实施例的制造半导体封装的方法。
图7示意性地示出了根据本公开的一些实施例的半导体封装。
具体实施方式
现将详细地参考本发明的示范性实施例,示范性实施例的实例说明在附图中。只要有可能,相同组件符号在图式和描述中用来表示相同或相似部分。
下面的揭露提供了许多不同的实施例或示例,用以实现所提供主题的不同特征。下面描述了组件和布置的具体示例以简化本揭露。当然,这些仅仅是示例而不是限制性的。例如,在下面的描述中在第二特征之上或之上形成第一特征可以包括其中第一和第二特征直接接触形成的实施例,并且还可以包括其中附加特征可以形成在第一和第二特征,因此第一和第二特征可能不会直接接触。此外,在各种示例中,本揭露可以重复参考数字和/或字母。这种重复是为了简单和清楚的目的,其本身并不规定所讨论的各种实施例和/或配置之间的关系。
此外,为了方便描述,本文中可以使用空间相对术语,例如“底下”、“之下”、“下方”、“之上”、“上方”等来描述一个组件或特征与另一组件的关系,或功能如图所示。除了图中所描绘的取向之外,空间相对术语旨在涵盖设备在使用或操作中的不同取向。设备可以以其他方式定向(旋转90度或以其他方向)并且这里使用的空间相对描述词同样可以相应地解释。
还可以包括其他特征和过程。例如,可以包括测试结构以帮助对3D封装或3DIC组件进行验证测试。测试结构可以包括例如在重分布层中或在允许测试3D封装或3DIC、使用探针和/或探针卡等的基板上形成的测试焊盘。验证测试可以在中间结构以及最终结构上执行。此外,本文公开的结构和方法可以与结合已知良好晶粒的中间验证的测试方法结合使用,以提高产量并降低成本。
图1A至图1G是示意性地示出根据本揭露的一些实施例的用以制造半导体封装的制程流程的截面图。
在图1A中,其中具有硅穿孔120的第一半导体基底110从第一半导体晶圆(未示出)切单而得并附接到第二半导体晶圆WF的第二半导体基底210。第一半导体基底110可以是半导体基底,例如硅基底,包括形成在其中的主动组件(例如,晶体管等)和形成在其中的被动组件(例如,电阻器、电容器、电感器等),例如,形成在第一半导体基底110的前侧110F。主动组件和被动组件通过半导体晶圆的前段制程(FEOL)制造制程在第一半导体基底110中形成。另外,在第一半导体基底110的前侧110F处形成互联机电路结构130。互联机电路结构130可以电连接到硅穿孔120,但揭露不以此限。互联机电路结构130可以包括交替堆栈的互连布线(例如,铜互连布线)和介电层,其中互联机电路结构130的互连布线电连接到第一半导体基底110中的主动组件和/或被动组件。互联机电路结构130通过半导体晶圆的后段制程(BEOL)制造制程形成。互联机电路结构130中最外面的互连布线可以包括导电衬垫132,而导电衬垫132可以是铝垫、铜垫或其他合适的金属垫。
第二半导体基底210可以是半导体基底,例如硅基底,包括形成在其中的主动组件(例如,晶体管等)和被动组件(例如,电阻器、电容器、电感器等)。主动组件和被动组件通过半导体晶圆的前段制程(FEOL)制造制程在第二半导体基底210中形成并构建逻辑电路、内存或其组合。在第二半导体基底210的前侧210F处形成互联机电路结构220。互联机电路结构220可以包括交替堆栈的互连布线(例如,铜互连布线)和介电层,其中互联机电路结构220的互连布线电连接到第二半导体基底210中的主动组件和/或被动组件。互联机电路结构220通过半导体晶圆的后段制程(BEOL)制造制程形成。互联机电路结构220中最外面的互连布线可以包括导电衬垫222,而导电衬垫222可以是铝垫、铜垫或其他合适的金属垫。
第一半导体基底110可以通过电接点BM连接到第二半导体基底210。接点BM可以是焊球、金属柱、受控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯-浸金技术(ENEPIG)形成的凸块、它们的组合(例如,附有焊球的金属柱),或类似。接点BM可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或其组合的导电材料。在一些实施例中,作为示例,接点BM包括共晶材料并且可以包括焊料凸块或焊球。在一些实施例中,接点BM包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(例如铜柱),其上具有或不具有焊料材料。金属柱可以是无焊料的并且具有基本上垂直的侧壁或锥形侧壁。
在一些实施例中,可以预先在互联机电路结构130和互联机电路结构220上分别形成微凸块。例如,在互联机电路结构130上具有微凸块的第一半导体基底110可以从第一半导体晶圆中切单而成,然后被拾取并放置在第二半导体晶圆WF上,使得互联机电路结构130上的微凸块接触互联机电路结构220上的微凸块。第一半导体基底110可以通过晶圆上芯片制程连接到第二半导体基底210上。在一些实施例中,接点BM的间距可以是10μm或更小。在一些实施例中,第一半导体基底110和第二半导体基底210可以通过混合接合制程彼此结合,使得第一半导体基底110上的互联机电路结构130和第二半导体基底210上的互联机电路结构220之间没有间隙。
在图1B中,在将单片化的第一半导体基底110连接到第二半导体晶圆WF中的第二半导体基底210之后,在第二半导体晶圆WF上方形成第一绝缘包封体230以至少侧向封装第一半导体基底110,以及形成在第一半导体基底110中的互联机电路结构130。在一些实施例中,第一绝缘包封体230可以填充第一半导体基底110上的互联机电路结构130和第二半导体基底210上的互联机电路结构220之间的间隙,并且第一绝缘包封体230可以密封接点BM。在一些替代实施例中,可进一步形成底部填充剂材料以填充第一半导体基底110上的互联机电路结构130与第二半导体基底210上的互联机电路结构220之间的间隙以密封接点BM。第一绝缘包封体230可以封装和/或接触底部填充剂材料、互联机电路结构130和第一半导体基底110。在其他一些实施例中,第一半导体基底110和第二半导体基底210可以通过混合接合制程彼此结合并且互联机电路结构130和互联机电路结构220之间没有间隙。在一些实施例中,第一绝缘包封体230和底部填充剂的材料(未示出)包括环氧聚合物或其他合适的介电材料。
随后,在图1C中,执行显露制程以显露硅穿孔120,并在第一半导体基底110上的背侧110B处形成隔离层140以形成第一半导体晶粒100。在一些实施例中,隔离层140可具有厚度,例如约2μm或更大,足以将第一半导体基底110与可从上覆层扩散的材料隔离。为了露出硅穿孔120,可以在图1B的结构上执行研磨过程以部分去除第一绝缘包封体230,直到第一半导体基底110与第一绝缘包封体230齐平。部分去除第一绝缘包封体230的研磨制程包括机械研磨制程、CMP制程或其组合。显露制程可以包括使用蚀刻技术(例如湿式蚀刻、干式蚀刻等)去除第一半导体基底110的一部分,直到硅穿孔120的一部分被暴露并且在背侧110B处远离第一半导体基底110的蚀刻表面而突出。
通过蚀刻已经被第一绝缘包封体230封装的第一半导体基底110形成凹部结构,并且在由第一绝缘包封体230和蚀刻的第一半导体基底110所定义的凹部结构中形成隔离层140。在一些实施例中,第一绝缘包封体230可以在蚀刻第一半导体基底110期间被保护材料覆盖,或者替代地,用以蚀刻第一半导体基底110的蚀刻剂可以在第一半导体基底110的材料和第一绝缘包封体的材料之间具有良好的选择,因此第一半导体基底110的材料不容易在蚀刻室中扩散,这有利保持蚀刻室的真空状态。在一些实施例中,可以稍后去除在蚀刻第一半导体基底110期间覆盖第一绝缘包封体230的保护材料以暴露第一绝缘包封体230。
在一些实施例中,隔离层140由可在250℃以下的温度下固化但不以此限的低温聚酰亚胺制成。隔离层140可以在去除蚀刻制程中使用的保护材料之前或去除保护材料之后形成。保护材料的材料可以与隔离层140的材料相同,例如低温聚酰亚胺,但不以此限。可以执行研磨制程以去除第一绝缘包封体230上的隔离层140的部分材料以形成第一半导体晶粒100。在图1C中,硅穿孔120的末端120B、第一绝缘包封体230的顶表面230B和隔离层140的顶表面140B共面且彼此齐平。
第一半导体晶粒100可以包括第一半导体基底110、从前侧110F延伸穿过第一半导体基底110到与前侧110F相对的背侧110B的硅穿孔120、形成在前侧110F处的互联机电路结构130以及在背侧110B处覆盖第一半导体基底110的隔离层140。第一半导体晶粒100与作为第二半导体晶圆WF的一部分的第二半导体基底210接合。第一半导体晶粒100被第一绝缘包封体230侧向封装并与第一绝缘包封体230共面。第一半导体基底110的侧壁边缘、互联机电路结构130的侧壁边缘和隔离层140的侧壁边缘可以彼此对齐并与第一绝缘包封体230直接接触。
在图1D中,介电层242形成在第一绝缘包封体230和第一半导体晶粒100上。介电层242覆盖了第一绝缘包封体230的顶表面230B和隔离层140的顶表面140B并具有开口242A,因此硅穿孔120的末端120B没有被介电层242覆盖。形成导体结构250并填充介电层242的开口242A以接触硅穿孔120的末端120B,使得硅穿孔120电连接至导体结构250和互联机电路结构130的导线。导体结构250可以是铜通孔、衬垫铜通孔等。此外,还可以在介电层242上形成另一个介电层244,介电层244包围导体结构250,从而使介电层242和介电层244形成介电层结构240。介电层结构240覆盖了第一半导体晶粒100和第一绝缘包封体230。导体结构250延伸穿过介电层结构240并与硅穿孔120电连接。一些导体结构250可用作晶圆级测试的测试垫,以便可以识别经过测试且可靠的已知良好晶粒(KGD)。
如图1D的放大部分所示,硅穿孔120可以包括金属柱120P和衬垫120L,衬垫120L包围金属柱120P,而衬垫120L在其他图中被省略以进行说明。衬垫120L可以将金属柱120P和第一半导体基底110隔离开来,禁止金属柱120P的金属材料扩散到第一半导体基底110。在一些实施例中,硅穿孔120的形成包括在第一半导体基底110中形成TSV开口,在TSV开口中形成衬垫120L,以及将金属材料填充到TSV开口的剩余部分中以形成被衬垫120L包围的金属柱120P。硅穿孔120通常具有较高的深宽比,例如大于约7,但不以此限。
在导体结构250形成之后,第二半导体晶圆WF被减薄和锯切。图1E显示从第二半导体晶圆WF切单而成的第二半导体晶粒200包括第二半导体基底210和互联机电路结构220并且与具有硅穿孔120的第一半导体晶粒100堆栈。第一半导体晶粒100和第二半导体晶粒200的堆栈结构260被拾取并放置在载具270上,其中导体结构250和介电层结构240形成在第一半导体晶粒100上具体来说,预先在载具270上形成背侧扇出重布线路结构280和绝缘层穿孔290,绝缘层穿孔290与背侧扇出重布线路结构280电连接,第一半导体晶粒100和第二半导体晶粒200的堆栈结构260附着在背侧扇出重布线路结构280上,其中导体结构250朝上。
在一些实施例中,第一半导体晶粒100和第二半导体晶粒200的堆栈通过使用晶粒贴合膜DAF附接到背侧扇出重布线路结构280。在第一半导体晶粒100和第二半导体晶粒200的堆栈结构260中,第一半导体晶粒100的横向尺寸小于第二半导体晶粒200的横向尺寸,第一半导体晶粒100被第一绝缘包封体230封装在第二半导体晶粒200之上。第一绝缘包封体230的侧壁边缘可以与第二半导体晶粒200的侧壁边缘以及介电层结构240的侧壁边缘对齐。
在图1F中,在载具270上形成第二绝缘包封体300以侧向封装第一半导体晶粒100和第二半导体晶粒200的堆栈结构260。第二绝缘包封体300可以与第二半导体晶粒200的侧壁边缘、第一绝缘包封体230的侧壁边缘和介电层结构240的侧壁边缘接触。在堆栈结构260和第二绝缘包封体300上进一步形成前侧扇出重布线路结构310。前侧扇出重布线路结构310可以电连接到导体结构250和绝缘层穿孔290。此外,还可以在前侧扇出重布线路结构310上形成接合结构320以接合到外部组件,例如电路板等。接合结构320可以包括凸块下金属(under bump metal,UBM)和凸块下金属上的焊球等。
在形成前侧扇出重布线路结构310之前,可以进行诸如化学研磨、机械研磨、CMP等的平坦化制程,使得第二绝缘包封体300的表面、介电层结构240的表面、绝缘层穿孔290的末端和导体结构250的表面可以彼此齐平并共面。前侧扇出重布线路结构310可以电连接到导体结构250和绝缘层穿孔290,使得第一半导体晶粒100、第二半导体晶粒200、背侧扇出重布线路结构280和前侧扇出重布线路结构310可以相互电连接以实现所需的电路功能。
在图1F中,在载具270上形成半导体封装330。半导体封装330包括第一半导体晶粒100、第二半导体晶粒200、第一绝缘包封体230、介电层结构240、导体结构250、绝缘层穿孔290、第二绝缘包封体300、背侧扇出重布线路结构280、前侧扇出重布线路结构310和接合结构320。第一半导体晶粒100以第一半导体晶粒100的前(主动)侧面向第二半导体晶粒200的前(主动)侧通过接点BM的方式结合到第二半导体晶粒200。第一绝缘包封体230设置在第二半导体晶粒200上,侧向地封装第一半导体晶粒100。介电层结构240的介电层242和介电层244位在第一半导体晶粒100和第一绝缘包封体230上,连续覆盖第一半导体晶粒100和第一绝缘包封体230。介电层242可以与第一半导体晶粒100和第一绝缘包封体230直接接触。背侧扇出重布线路结构280位在第二半导体晶粒200的背侧之上,超过第二半导体晶粒200。第二绝缘包封体300侧向地封装了第一绝缘包封体230和第二半导体晶粒200,背侧扇出重布线路结构280与第二绝缘包封体300直接接触。前侧扇出重布线路结构310设置在第二绝缘包封体300和介电层结构240上并与第二绝缘包封体300和介电层结构240接触。绝缘层穿孔290延伸穿过第二绝缘包封体300并连接在背侧扇出重布线路结构280和前侧扇出重布线路结构310之间。接合结构320设置在前侧扇出重布线路结构310上。
第一半导体晶粒100有第一半导体基底110、硅穿孔120贯穿第一半导体基底110、互联机电路结构130位在第一半导体基底110的前侧处、隔离层140位在第一半导体基底110的背侧处。隔离层140介在第一半导体基底110和介电层结构240之间。硅穿孔120的末端与第一绝缘包封体230的表面共面,也与隔离层140的表面共面。隔离层140由低温聚亚酰胺制成,可以防止前侧扇出重布线路结构310中的Cu等金属材料扩散到第一半导体晶粒100中的第一半导体基底110。隔离层140、硅穿孔120和第一绝缘包封体230共面。
在图1G中,载具270被移除,并且可以执行切单制程来将半导体封装330切单。半导体封装330定向为倒置的。另一个半导体封装340通过接合结构350连接到半导体封装330以形成层迭封装(PoP)结构360。在一些实施例中,半导体封装340可以是内存,例如DRAM封装,而接合结构350可以包括焊球。接合结构350可以设置在半导体封装330的背侧扇出重布线路结构280和半导体封装340上的接合垫之间。半导体封装340还可以通过绝缘层穿孔290电连接到前侧扇出重布线路结构310。
图2A在顶视图方向示意性地示出了第一半导体基底110,第一半导体基底110被第一绝缘包封体230侧向封装并且图2B示意性地示出了沿图2A中的线AA截取的横截面。在图2A和2B中,互联机电路结构130设置在第一半导体基底110的前侧110F处。第一绝缘包封体230与第一半导体基底110的侧壁边缘和互联机电路结构130的侧壁边缘接触。硅穿孔120的末端暴露在第一半导体基底110的背侧110B处。在一些实施例中,图2A和图2B所示的结构可以通过对图1B所示的结构进行平坦化制程,例如化学研磨、机械研磨等直到露出硅穿孔120的末端来形成。第一绝缘包封体230的表面、第一半导体基底110的表面和硅穿孔120的末端在研磨处理后共面。在顶视图中,第一绝缘包封体230形成环绕第一半导体基底110的环形。
图2C显示了在图2B的结构上形成的保护层PLA,保护层PLA覆盖了第一绝缘包封体230的至少一部分。保护层PLA可能会暴露硅穿孔120的末端。保护层PLA的形成可以包括在第一绝缘包封体230和第一半导体基底110上涂覆保护材料例如低温聚亚酰胺,然后通过光刻制程对保护材料进行图案化以暴露第一半导体基底110和硅穿孔120。图案化保护材料可以进一步固化以形成保护层PL。
在图2C中,保护层PLA可能会完全暴露第一半导体基底110。保护层PLA覆盖了第一绝缘包封体230的大部分表面。第一绝缘包封体230靠近第一半导体基底110的部分可能不会被保护层PLA覆盖,并且可能具有小于100nm的小宽度。在替代实施例中,保护层PLA可以完全覆盖第一绝缘包封体230,使得保护层PLA的侧壁边缘可以与第一绝缘包封体230和第一半导体基底110之间的边界对齐。
在图2D中,执行蚀刻制程以去除第一半导体基底110的一部分,从而形成由第一绝缘包封体230和蚀刻的第一半导体基底110限定的凹谷结构CV。蚀刻制程可包括湿式蚀刻技术、干式蚀刻技术或其组合。在一些实施例中,蚀刻制程可以在蚀刻室中进行。保护层PLA覆盖第一绝缘包封体230,因此第一绝缘包封体230不容易与蚀刻剂反应,蚀刻剂用以去除第一半导体基底110的材料。由此,可以防止蚀刻室中第一绝缘包封体230的材料的污染。在一些实施例中,受蚀刻的第一半导体基底110可以具有例如大约5μm~25μm的厚度T110。硅穿孔120在凹谷结构CV中可能会从第一半导体基底110的表面突出,并且在第一半导体基底110的表面上方具有大约0.2μm~2μm的突出高度P120。
在图2E中,例如通过沉积制程在图2D的结构上形成第一隔离层142。第一隔离层142的材料可以包括氮化物、氧化物等。在一些实施例中,第一隔离层142可以由低温氮化硅制成并且可以具有的厚度,但是揭露不以此限。第一隔离层142共形地覆盖了保护层PL、第一半导体基底110和硅穿孔120的突出部分以及第一绝缘包封体230未被保护层PL覆盖的部分。
在图2F中,通过在第一隔离层142上涂覆隔离材料,在第一隔离层142上进一步形成第二隔离层144。例如,第二隔离层144的材料可以与第一隔离层142的材料不同。在一些实施例中,第二隔离层144的材料可以与保护层PL的材料相同。例如,第二隔离层144的材料可以是低温聚亚酰胺。第二隔离层144可能有足够的厚度来补偿底层交错的结构并提供平坦的顶表面144T。第二隔离层144填充了通过图2D的蚀刻制程形成的凹谷结构CV,并覆盖了第一绝缘包封体230上的保护层PLA。
在图2F的结构上执行诸如化学研磨、机械研磨或其组合的研磨过程,直到完全去除保护层PLA。如图2G所示,经过研磨处理后,第一绝缘包封体230的表面、第一隔离层142的一部分、第二隔离层144的表面和硅穿孔120的末端显露出来。第一隔离层142具有U形横截面。第一隔离层142包括平面部分142P和垂直部分142V。平面部分142P介在第二隔离层144和第一半导体基底110之间。竖直部分142V从平面部分142P的外围向硅穿孔120的末端的水平高度竖直延伸以环绕第二隔离层144的侧壁边缘144S。第一隔离层142的垂直部分142V的一部分在第一绝缘包封体230和第二隔离层144之间并与第一绝缘包封体230接触。第一隔离层142和第二隔离层144可以在图1C所示的结构中构造隔离层140。换言之,图2G的结构可以用作图1C的结构的实施例。在一些实施例中,包括第一隔离层142和第二隔离层144的隔离层140可以具有1μm~3μm的厚度。在一些实施例中,可以省略第一隔离层142,使得隔离层140是填充由第一绝缘包封体230和第一半导体基底110限定的凹谷结构CV并且与硅穿孔120和第一绝缘包封体230的侧壁边缘直接接触的单层。
图2H示意性地示出了图2G的步骤之后的半导体封装的顶表面。参考图2G和图2H,第一绝缘包封体230围绕着第一半导体基底110,也围绕着第一隔离层142。垂直部分142V可以包括在顶视图中围绕第二隔离层144的第一子部分142V1和在顶视图中围绕硅穿孔120的第二子部分142V2。第一子部分142V1有一个环状的结构,介在第二隔离层144和第一绝缘包封体230之间。第二子部分142V2有一个环状的结构,介在第二隔离层144和硅穿孔120之间。
在图2I中,介电层242形成在图2G的结构上。介电层242的材料可以与隔离层140的第二隔离层144的材料相同。例如,介电层242可以由低温聚亚酰胺制成。介电层242有开口242A,所以介电层242不覆盖硅穿孔120的末端。介电层242形成在由第一绝缘包封体230、隔离层140和硅穿孔120的共面配置构成的平面表面上。
在图2I中,导体结构250进一步形成在介电层242上并填充介电层242的开口242A,另一个介电层244形成在介电层242上以包围导体结构250从而形成如图1D所示的介电层结构240。导体结构250可以由诸如铜的金属形成以用作导通孔。在一些实施例中,导体结构250可以是线性通孔。
图3A示意性地示出了图2C的替代结构。在图3A中,在图2B的结构上形成保护层PLB以完全覆盖第一绝缘包封体230并进一步覆盖第一半导体基底110的接口设备部分112。第一半导体基底110的周边部分112靠近第一绝缘包封体230并与第一绝缘包封体230接触。保护层PLB不覆盖硅穿孔120。保护层PLB的材料可以包括低温聚亚酰胺。在一些实施例中,保护层PLB的材料可以是其他在后续制程中可以作为掩膜的材料。例如,保护层PLB的材料可以是光阻。
在图3B中,执行使用保护层PLB作为掩模的蚀刻制程以去除未被保护层PLB覆盖的第一半导体基底110部分。受蚀刻的半导体基底110包括周边部分112和被周边部分112包围的变薄部分114。周边部分112与绝缘包封体230直接接触并且位在第一绝缘包封体230和变薄部分114之间。周边部分112的厚度大于变薄部分114以形成凹谷结构CV。硅穿孔120设置在变薄部分114中,硅穿孔120的一部分从变薄部分114的表面突出。在蚀刻过程中,第一绝缘包封体230被完全覆盖,因此第一绝缘包封体230不受蚀刻过程中使用的蚀刻剂的影响。可以防止第一绝缘包封体230的材料污染蚀刻室。
在图3C中,第一隔离层142形成在图3B的结构上以覆盖第一半导体基底110、硅穿孔120和保护层PLB的变薄部分114。第一隔离层142可以共形地覆盖保护层PLB的顶表面和侧壁边缘、变薄部分114的顶表面114B、硅穿孔120的暴露部分的侧壁边缘120S和硅穿孔120的末端120B。另外,第一半导体基底110的周边部分112的侧壁边缘112S也被第一隔离层142覆盖,而周边部分112的顶表面112B被保护层PLB覆盖。第一隔离层142可以由氧化物、氮化物或其组合制成并且可以通过沉积制程形成在第一半导体基底110上。在一些实施例中,第一隔离层142的材料可以是低温氮化硅。
在图3D中,第二隔离层144形成在第一隔离层142上。在一些实施例中,第二隔离层144通过涂覆制程形成,而第二隔离层144具有足够的厚度来补偿由保护层PLB、受蚀刻的第一半导体基底110和露出的硅穿孔120引起的不均匀结构。第二隔离层144可由低温聚亚酰胺制成。在一些实施例中,可以省略第一隔离层142,使得第二隔离层144可以与第一半导体基底110和硅穿孔120接触。
在图3E中,执行研磨制程以减少第二隔离层144的厚度,直到完全去除保护层PLB并露出硅穿孔120和第一绝缘包封体230,从而形成隔离层140。硅穿孔120的末端120B、周边部分112的顶表面112B、隔离层140的顶表面140B及第一绝缘包封体230的顶表面230B共面。图3E所示的结构可以作为图1C的结构的另一个实施例。
本实施例中的隔离层140可以包括具有U形截面的第一隔离层142和填充第一隔离层142的U形截面的第二隔离层144。第一隔离层142包括平面部分142P和垂直部分142V。平面部分142P设置在第一半导体基底110和第二隔离层144的底部之间,垂直部分142V从平面部分142P的外围垂直延伸并插入硅穿孔120和第二隔离层144之间以及第一半导体基底110的第二隔离层144和周边部分112之间。
图3F示意性地示出了在图3E的步骤之后封装的顶视图。在图3E和图3F中,第一绝缘包封体230围绕着第一半导体基底110的周边部分112,而第一隔离层142与第一绝缘包封体230被第一半导体基底110的周边部分112隔开。垂直部分142V可以包括在顶视图中围绕第二隔离层144的第一子部分142V1和在顶视图中围绕硅穿孔120的第二子部分142V2。第一子部分142V1有一个环状的结构,介在第一半导体基底110和第二隔离层144的周边部分112之间。第二子部分142V2有一个环状的结构,介在第二隔离层144和硅穿孔120之间。
在图3G中,介电层242形成在图3E的结构上。介电层242可以由与第二隔离层144相同的材料制成。例如,介电层242的材料可以是低温聚亚酰胺。介电层242可能有开口242A暴露硅穿孔120。介电层242可以与隔离层140、第一半导体基底110的周边部分112和第一绝缘包封体230的一部分直接接触。
在图3G中,可以在介电层242上依次形成一个导体结构250和另一个介电层244。导体结构250填充了介电层242的开口242A以接触硅穿孔120。导体结构250可以是铜通孔、铜线性通孔等。介电层244环绕导体结构250。在一些实施例中,导体结构250可以与介电层244共面。具有与介电层242接触的较厚周边部分112的图3G的结构可用作图1D的结构的实施例。
图4A示意性地说明了蚀刻第一半导体基底的步骤。在图4A中,保护层PLC形成在第一绝缘包封体230上并且基本上完全覆盖第一绝缘包封体230。执行蚀刻制程以去除第一半导体基底110的一部分以露出硅穿孔120的一部分。图4A的步骤类似图2D的步骤和图3B的步骤,从而形成凹谷结构CV并且凹谷结构CV由第一绝缘包封体230和第一半导体基底110定义。第一绝缘包封体230在蚀刻过程中被保护层PLC覆盖,从而防止了第一绝缘包封体230材料对蚀刻室的污染。保护层PLC在本实施例中由光阻材料制成,可以在刻蚀制程后去除。
图4B示意性地显示了保护层PLC被移除并形成了第一隔离层142。第一隔离层142可以共形地覆盖第一半导体基底110、硅穿孔120和第一绝缘包封体230。第一隔离层142可能与第一绝缘包封体230直接接触,因为图4A中所示的保护层PLC在第一隔离层142形成之前被移除。与前述实施例类似,第一隔离层142可由氧化物、氮化物或其组合制成。例如,第一隔离层142可以由低温氮化硅通过沉积制程制成。
在图4C中,第二隔离层144可以形成在第一隔离层142上。第二隔离层144的材料可以是低温聚亚酰胺。第二隔离层144可以通过涂覆制程形成在第一隔离层142上。第二隔离层144的厚度可以厚一些,这样可以补偿第一半导体基底110、硅穿孔120、第一绝缘包封体230造成的结构不均匀,方便后续的磨削加工。
图4C的结构被研磨以减少第二隔离层144的厚度,直到硅穿孔120和第一绝缘包封体230被暴露,并形成介电层242,如图4D所示。在研磨过程之后,形成包括第一隔离层142和第二隔离层144的隔离层140。第一隔离层142具有U形横截面,第二隔离层144填充U形横截面。介电层242设置在第一绝缘包封体230和隔离层140上。介电层242的材质可以与第二隔离层144相同,例如低温聚亚酰胺。在一些实施例中,可以省略第一隔离层142,使得隔离层140是由低温聚亚酰胺的材料形成的单层结构。
在图4E中,可以在介电层242上依次形成导体结构250和另一个介电层244。导体结构250在介电层242的开口处接触硅穿孔120。导体结构250可以是铜通孔、铜线性通孔等。介电层244环绕导体结构250,介电层242和介电层244一起构成介电层结构240。在形成导体结构250和介电层244之后,可以执行研磨和/或平坦化制程,并且导体结构250可以与介电层结构240共面而导体结构250延伸穿过介电层结构240。图4E的结构可用作图1D的结构的实施例。
图5示意性地示出了根据揭露的一些实施例的图1G中的半导体封装的放大部分V。在一些实施例中,半导体封装330’可以类似图1G中的半导体封装330,并且还包括设置在第一半导体基底110和导通孔254上的热增强层252。另外,介电层结构240’包括前面实施例中描述的介电层242和介电层244,还包括介电层246。
在半导体封装330’中,介电层242形成在第一半导体基底110上的隔离层140上,没有覆盖通过第一半导体基底110的硅穿孔120的末端。热增强层252形成在介电层242上并且由具有良好散热特性的材料制成。热增强层252可以具有3μm~15μm的厚度。在一些实施例中,热增强层252的材料包括铜等。热增强层252可以包括延伸穿过介电层242以接触硅穿孔120的垫部分252P和与垫部分252P分离并分布在第一半导体基底110上的导热部分252T。介电层244形成在介电层242上,没有覆盖垫部分252P。导通孔254形成在介电层244上并与热增强层252的垫部分252P接触。介电层246设置在介电层244上,没有覆盖导通孔254。介电层242、242和246形成介电层结构240’,垫部分252P和导通孔254形成导体结构250,导体结构250延伸穿过介电层结构240’,并与第一半导体基底110中的硅穿孔120电连接。导通孔254的表面可以与介电层246的表面共面。热增强层252可以提供热传导特性,从而可以有效地散发半导体封装330’中产生的热量,从而提高半导体封装330’的性能和可靠性。
图6A至图6L示意性地示出了根据揭露的一些实施例制造半导体封装的方法。在图6A中,提供了第一半导体晶圆WF1。金属柱MP形成在第一半导体晶圆WF1中,并从第一半导体晶圆WF1的表面延伸到第一半导体晶圆WF1的一定深度。此外,互联机电路结构ICC1形成在第一半导体晶圆WF1的表面上,互联机电路结构ICC1形成在金属柱MP上并与金属柱MP电连接。
金属柱MP的形成可以包括在第一半导体晶圆WF1中形成深开口,在深开口中形成衬垫,以及将金属材料填充到深开口的剩余部分中。深开口往往具有高深宽比,从第一半导体晶圆WF1的表面延伸到第一半导体晶圆WF1的一定深度。主动组件AC和/或被动组件可以通过半导体晶圆的前段制程(FEOL)制造制程形成在第一半导体晶圆WF1上。深开口延伸到第一半导体晶圆WF1中至至少比主动组件AC更深的深度,并且可以延伸至大于第一半导体晶圆WF1的最终期望高度的深度。深开口的深度可以在大约20μm和大约200μm之间。在一些实施例中,深开口可具有距第一半导体晶圆WF1上的主动组件AC约100μm的深度。衬垫可以与深开口的形状共形并且沿着深开口的垂直壁和深开口的底部连续延伸。衬垫可以是例如由原硅酸四乙酯(TEOS)或氮化硅形成的氧化物,但可替代地使用任何合适的介电材料。衬垫可使用等离子体增强化学气相沉积(PECVD)制程形成,但可替代地使用其他合适的制程,例如物理气相沉积或热处理。金属材料填充深开口的剩余部分,因此金属材料和第一半导体晶圆WF1被衬垫隔离。换言之,金属材料不与第一半导体晶圆WF1接触。金属材料的材料可包括导电材料,例如铜或替代地铝、钨、银、金或掺杂多晶硅。可以执行研磨和/或平坦化制程例如化学研磨制程、机械研磨制程或其组合以去除金属材料和衬垫的多余材料以形成金属柱MP。
互联机电路结构ICC1可以形成在第一半导体晶圆WF1和金属柱MP上。互联机电路结构ICC1可以包括金属接线和在介电层中形成的通孔(未示出),介电层可以是低k介电层。金属接线和通孔可以电连接到金属柱MP。互联机电路结构ICC1还可包括钝化层、接合垫(未示出)等。另外,互联机电路结构ICC1中最外层的互连布线可以包括导电衬垫PD,而导电衬垫PD可以是铝垫、铜垫或其他合适的金属垫。
接点BMA分别形成在导电衬垫PD上。接点BMA可以是焊球、金属柱、受控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯-浸金技术(ENEPIG)形成的凸块、它们的组合(例如,附有焊球的金属柱),或类似。接点BMA可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或其组合的导电材料。在一些实施例中,作为示例,接点BMA包括共晶材料并且可以包括焊料凸块或焊球。在一些实施例中,接点BMA包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(例如铜柱),其上具有或不具有焊料材料。金属柱可以是无焊料的并且具有基本上垂直的侧壁或锥形侧壁。
在图6B中,第一半导体晶圆WF1通过胶层GL暂时连接到载具CR1。第一半导体晶圆WF1的取向是接点BMA面向载具CR1。胶层GL可以包围接点BMA。载具CR1可以在后续的加工过程中承载第一半导体晶圆WF1。例如,对载具CR1承载的第一半导体晶圆WF1进行TSV(硅穿孔)显露制程。在TSV显露制程中,载具CR1承载的第一半导体晶圆WF1可能会依序地受到:背面研磨制程直到金属柱MP暴露在与接点BMA侧面相对的背侧处;平坦化制程抛光研磨第一半导体晶圆WF1的表面及金属柱MP;蚀刻制程去除第一半导体基底的一部分以形成凹谷结构,露出金属柱MP;清洗制程;形成隔离层填充凹谷结构的过程;另一个平坦化制程;和清洗制程。在一些实施例中,平坦化制程可以包括化学机械抛光(CMP),但不以此限。从而,形成图6C的结构。
在图6C中,形成了第一半导体晶粒400,而第一半导体晶粒400包括第一半导体基底410、硅穿孔420和互联机电路结构430。减薄的第一半导体晶圆WF1定义了第一半导体基底110。金属柱MP的一部分在背侧410B处从第一半导体基底410突出以形成硅穿孔420。第一半导体基底410对应的互联机电路结构ICC1定义为第一半导体晶粒400的互联机电路结构430。此外,第一半导体晶粒400还包括覆盖第一半导体基底410的背侧410B并包围硅穿孔420的突出部分的隔离层440。硅穿孔420的末端与隔离层440的表面共面。在一些实施例中,隔离层440可由氧化物、氮化物或其组合制成。隔离层440可以是沉积在第一半导体基底410上的氮化硅层。在一些替代实施例中,隔离层440可以由低温聚亚酰胺制成。
在图6D中,在隔离层440上的第一半导体基底410上形成了另一个互联机电路结构450。第一半导体晶粒400可以包括形成在第一半导体基底410的前侧410F处的互联机电路结构430、形成在第一半导体基底410的背侧410B处的互联机电路结构450、互联机电路结构450和第一半导体基底410之间的隔离层440以及从前侧410F延伸到背侧410B的硅穿孔420。硅穿孔420将互联机电路结构430电连接到互联机电路结构450。
另外,在第一半导体晶粒400上形成介电层结构510和导体结构520。介电层结构510可以由介电材料制成,例如低温聚亚酰胺。导体结构520可以穿过介电层结构510并在第一半导体基底410的背侧410B处电连接到互联机电路结构450。导体结构520可以是铜通孔、铜线性通孔等。在一些实施例中,介电层结构510和导体结构520可具有图5中所示的结构。换言之,热增强层可以形成在介电层结构510中并且导体结构520可以由热增强层和导通孔中的垫部分形成。
在图6E中,图6D的结构倒置,载具CR1与第一半导体晶圆WF1分开并由另一个载具CR2支撑。此外,胶层GL也从第一个半导体晶粒400中移除。由此,第一半导体基底410的背侧410B处的接点BMA被暴露。在第一半导体晶圆WF1上执行锯切制程以从第一半导体晶圆WF1中切单(singulated)而成第一半导体晶粒400。
在图6F中,通过芯片晶圆(chip on wafer)接合制程将其上带有导体结构520的单个第一半导体晶粒400接合到第二半导体晶圆WF2。第一半导体晶粒400定向为接点BMA面向第二半导体晶圆WF2。第一半导体晶粒400可以通过将互联机电路结构ICC2的接点BMA连接到表面接垫而结合到第二半导体晶圆WF2。在一些实施例中,第一半导体晶粒400可以通过混合接合制程结合到第二半导体晶圆WF2,使得第一半导体晶粒400和第二半导体晶圆WF2之间可以没有间隙。
第二半导体晶圆WF2在其上形成有互联机电路结构ICC2并且取向为互联机电路结构ICC2面向第一半导体晶粒400。互联机电路结构ICC2可以包括形成在介电层中的金属接线和通孔(未示出)。介电层可能是低k介电层。此外,绝缘层穿孔TIV1可以形成在第二半导体晶圆WF2上并且电连接到互联机电路结构ICC2。在一些实施例中,可以省略绝缘层穿孔TIV1。
在图6G中,在将第一半导体晶粒400通过接点BMA接合到第二半导体晶圆WF2之后,在第二半导体晶圆WF2上形成底部填充剂530和第一绝缘包封体540。形成底部填充剂530以密封接点BMA并填充第一半导体晶粒400和第二半导体晶圆WF2之间的间隙。在一些实施例中,可以省略底部填充剂530。第一绝缘包封体540封装了第一半导体晶粒400、底部填充剂530和绝缘层穿孔TIV1。第一半导体晶粒400的侧壁边缘、介电层结构510的侧壁边缘和底部填充剂530的封闭边缘与第一绝缘包封体540接触并被第一绝缘包封体540覆盖。此外,执行平坦化制程以暴露绝缘层穿孔TIV1和导体结构520。绝缘层穿孔TIV1和导体结构520可以与介电层结构510和第一绝缘包封体540共面。
在图6H中,图6G中的第二半导体晶圆WF2从背侧变薄,由载具CR3承载并经受锯切以从第二半导体晶圆WF2中切单而得到第二半导体晶粒550,从而形成堆栈结构560。从第二半导体晶圆WF2切单而得到的第二半导体晶粒550至少包括作为图6G中第二半导体晶圆WF2的一部分的第二半导体基底552和作为图6G中互联机电路结构ICC2的一部分的互联机电路结构554。互联机电路结构554设置在第二半导体基底552的前侧上。
堆栈结构560包括堆栈在第二半导体晶粒550上的第一半导体晶粒400,第一半导体晶粒400通过接点BMA粘合到第二半导体晶粒550。第一半导体晶粒400的横向尺寸小于第一半导体晶粒550的横向尺寸。第一半导体晶粒400和介电层结构510以及底部填充剂530和绝缘层穿孔TIV1被第二半导体晶粒550上的第一绝缘包封体540侧向封装。第二半导体晶粒550通过接点BMA与第一半导体晶粒400电连接。第一半导体晶粒400有硅穿孔420形成从前侧到背侧的导电路径。在半导体晶粒400的背侧处形成的导体结构520与第一半导体晶粒400的背侧处的互联机电路结构450电连接。
在图6I中,背侧扇出重布线路结构570形成在载具CR4上,堆栈结构560以第一绝缘包封体540、导体结构520和介电层结构510形成在第一半导体晶粒400和绝缘层穿孔TIV1背离背侧扇出重布线路结构570的方向连接到背侧扇出重布线路结构570。此外,绝缘层穿孔TIV2形成在背侧扇出重布线路结构570上并电连接至背侧扇出重布线路结构570。在一些实施例中,堆栈结构560使用晶粒贴合膜DAF以第二半导体晶粒550位在第一半导体晶粒400和背侧扇出重布线路结构570之间的方式连接在背侧扇出重布线路结构570上。
在图6J中,堆栈结构560被第二绝缘包封体580侧向封装,绝缘层穿孔TIV2被第二绝缘包封体580包围。第二绝缘包封体580的形成可以包括在载具CR4上涂覆绝缘材料,例如环氧聚合物或其他合适的介电材料。在载具CR4上形成的绝缘材料的量足以完全覆盖绝缘层穿孔TIV2。载具CR4上的绝缘材料可以固化以封装堆栈结构560和绝缘层穿孔TIV2。此外,执行研磨制程以去除第二绝缘包封体580的多余材料直到暴露绝缘层穿孔TIV2、绝缘层穿孔TIV1、介电层结构510和导体结构520。绝缘层穿孔TIV1、绝缘层穿孔TIV2和导体结构520可能与第二绝缘包封体580和第一绝缘包封体540共面。第一绝缘包封体540的侧壁和第二半导体晶粒550的侧壁可以与第二绝缘包封体580直接接触。
在图6K中,前侧扇出重布线路结构590形成在堆栈结构560和第二绝缘包封体580上。前侧扇出重布线路结构590与绝缘层穿孔TIV1、绝缘层穿孔TIV2和导体结构520电连接。前侧扇出重布线路结构590可以通过导体结构520电连接到第一半导体晶粒400,通过绝缘层穿孔TIV1和/或第一半导体晶粒400电连接到第二半导体晶粒550,并且通过绝缘层穿孔TIV2电连接到背侧扇出重布线路结构570。
另外,在前侧扇出重布线路结构590上形成接合结构600。在一些实施例中,接合结构600可以包括凸块下金属、焊球等。接合结构600可以结合到外部组件例如电路板等。半导体封装610形成在载具CR4上,包括堆栈结构560、第二绝缘包封体580侧向封装堆栈结构560、绝缘层穿孔TIV2穿过第二绝缘包封体580、背侧扇出重布线路结构570形成在堆栈结构560的一侧、前侧扇出重布线路结构590形成在堆栈结构560的另一侧和接合结构600。
在图6L中,半导体封装610与载具CR4分离,并通过接合结构630连接到另一个半导体封装620以形成迭层封装(PoP)结构640。半导体封装620可以是DRAM封装并且通过接合结构630电连接到背侧扇出重布线路结构570。
图7示意性地示出了根据揭露的一些实施例的半导体封装。半导体封装700包括第一半导体晶粒710、第二半导体晶粒720、底部填充剂730、第一绝缘包封体740、第二绝缘包封体750、背侧扇出重布线路结构760、前侧扇出重布线路结构770和绝缘层穿孔TIV。第一半导体晶粒710的横向尺寸可以大于第二半导体晶粒720的横向尺寸。第二半导体晶粒720通过接点BMB与第一半导体晶粒710接合。底部填充剂730填补了第一半导体晶粒710和第二半导体晶粒720之间的空隙并包围了接点BMB。第一绝缘包封体740设置在第一半导体晶粒710上以侧向封装第二半导体晶粒720。第二绝缘包封体750封装了第一半导体晶粒710和第一绝缘包封体740。绝缘层穿孔TIV可以布置成穿过第二绝缘包封体750。背侧扇出重布线路结构760和前侧扇出重布线路结构770可以设置在第二绝缘包封体750的相对侧并且通过绝缘层穿孔TIV彼此电连接。
第一半导体晶粒710可以通过图6A至6E的上述步骤制造,但是揭露不以此限。第一半导体晶粒710包括第一半导体基底712,硅穿孔714穿过第一半导体基底712,互联机电路结构716设置在第一半导体基底712的前侧,隔离层718设置在第一半导体基底712的背侧。
导电衬垫PD可以形成在第一半导体基底712的前侧上。导电衬垫PD可以包括通过接点BMB和第二导电衬垫PD2结合到第二半导体晶粒720上的接垫的第一导电衬垫PD1。第二导电衬垫PD2未接合到第二半导体晶粒720。第二导电衬垫PD2可分为第二导电衬垫PD2A和第二导电衬垫PD2B,其中第二导电衬垫PD2A可与底部填充剂730接触,第二导电衬垫PD2B可与第一绝缘包封体740接触。第二接合垫PD2用作在形成底部填充剂730和第一绝缘包封体740之前结合到测试卡等的测试接垫。
在图7中,热增强层780可以在第一半导体基底712的背侧上形成在隔离层718上,导通孔790可以形成在热增强层780上。热增强层780可以由具有良好导热性能的材料制成并且可以包括与硅穿孔714接触的垫部分782。导通孔790设置在垫部分782上以形成导体结构792,将硅穿孔714电连接到前侧扇出重布线路结构770。热增强层780和导体结构792中的结构可以参考上面对图5中热增强层252和导体结构750的描述。在一些实施例中,可以省略热增强层780并且因此导体结构792可以类似图6E中所示的导体结构520。
根据一些实施例的半导体封装可以通过使用诸如图1A至1G中所示的步骤的TSV(硅穿孔)显露优先(TSV reveal first)制程或诸如图4A至图4E中所示的步骤的TSV显露后行(TSV reveal last)制程来制造。具体地,在TSV显露后行制程中,在去除围绕基板穿孔的第一半导体基底的蚀刻制程之前,具有硅穿孔的第一半导体晶粒被第一绝缘包封体封装。在一些实施例中,可以选择图2A至图2I所示的方法、图3A至图3G所示的方法和图4A至图4E所示的方法之一。因此,在蚀刻过程中,第一绝缘包封体的材料不容易在蚀刻室中被去除或扩散,从而可以防止蚀刻室上的材料污染。在TSV显露优先制程中,在使用第一绝缘包封体封装第一半导体晶粒之前执行去除围绕基板穿孔的第一半导体基底的蚀刻制程。因此,不会发生蚀刻室上的封装材料的污染。在一些实施例中,半导体封装可以包括热增强层以提高散热效果以保证半导体封装的性能。在一些实施例中,半导体封装可以包括形成在第一半导体晶粒的前侧上并且被诸如底部填充剂或绝缘包封体的封装材料覆盖而没有结合到第二半导体晶粒的悬空接垫。
根据揭露的一些实施例,提供包括第一半导体晶粒、第二半导体晶粒、第一绝缘包封体、介电层结构、导体结构和第二绝缘包封体的半导体封装。第一半导体晶粒包括第一半导体基底和硅穿孔。硅穿孔从半导体基底的第一侧延伸到半导体基底的第二侧,第一侧与第二侧相对。第二半导体晶粒设置在半导体基底的第一侧。第一绝缘包封体设置在第二半导体晶粒上并封装第一半导体晶粒。硅穿孔的末端与第一个绝缘包封体的表面共面。介电层结构覆盖了第一半导体晶粒和第一绝缘包封体。导体结构延伸穿过介电层结构并与硅穿孔接触。第二绝缘包封体侧向封装并与第二半导体晶粒、第一绝缘封装和介电层结构接触。在一些实施例中,第二绝缘包封体的表面与导体结构的表面共面。在一些实施例中,第一半导体晶粒还可以包括设置在第一半导体基底和介电层结构之间的隔离层,并且隔离层的表面可以与硅穿孔的末端共面。隔离层可由低温聚亚酰胺制成。隔离层可以包括第一隔离层和第二隔离层,第一隔离层可以包括第二隔离层和第一半导体基底之间的平面部分以及从平面部分的外围向硅穿孔的末端的水平高度垂直延伸的竖直部分。垂直部分可以包括在顶视图中围绕第二隔离层的第一子部分和在顶视图中围绕硅穿孔的第二子部分。在一些实施例中,半导体封装还包括设置在第一半导体基底上的热增强层和设置在热增强层上的导通孔,其中热增强层可以包括连接在硅穿孔和导通孔之间的垫部分,导体结构由垫部分和导通孔构成。热增强层还可包括与垫部分分离并分布在第一半导体基底上的导热部分。在一些实施例中,半导体封装还可包括与介电层结构和第二绝缘包封体接触的第一扇出重布线路结构。半导体封装还可以包括第二扇出重布线路结构,其中第二半导体晶粒连接到第二扇出重布线路结构。第一扇出重布线路结构和第二扇出重布线路结构可以位在第二绝缘包封体的相对侧。在一些实施例中,半导体封装还可包括延伸穿过第二绝缘包封体的绝缘层穿孔,其中绝缘层穿孔的末端与介电层结构和导体结构共面。在一些实施例中,第一半导体基底可以包括周边部分和变薄部分。变薄部分被周边部分包围。硅穿孔设置在变薄部分中,周边部分的表面与硅穿孔的末端和第一绝缘包封体的表面共面。
根据揭露的一些其他实施例,提供了一种制造半导体封装的方法,包括以下步骤。具有硅穿孔的第一半导体基底连接到第二半导体基底。第一半导体基底使用第一绝缘包封体封装在第二半导体基底上。执行蚀刻制程以去除第一半导体基底的一部分直到露出硅穿孔的一部分而第一绝缘包封体被覆盖。在第一半导体基底和第一绝缘包封体上形成介电层结构。形成延伸穿过介电层结构并电连接到硅穿孔的导体结构。形成与第二半导体基底的侧壁边缘、第一绝缘包封体的侧壁边缘和介电层结构的侧壁边缘接触的第二绝缘包封体。在一些实施例中,第一绝缘包封体在蚀刻制程期间被保护层覆盖。该方法还可以包括形成隔离层,其中隔离层填充通过蚀刻制程形成的凹谷结构并覆盖第一绝缘包封体上方的保护层。可以进一步执行研磨制程,直到去除第一绝缘包封体之上的隔离层和保护层并且直到暴露硅穿孔的末端。保护层可以包括与隔离层相同的材料或光阻材料。
根据揭露的一些其他实施例,提供了一种制造半导体封装的方法,包括以下步骤。硅穿孔延伸穿过第一半导体基底形成半导体晶粒。第一半导体晶粒上形成介电层结构和导体结构,其中介电层结构覆盖第一半导体晶粒的第一侧,导体结构延伸穿过介电层结构与硅穿孔电连接。第一半导体晶粒在第一半导体晶粒的第二侧连接到第二半导体晶粒。第二侧与第一侧相对。第一半导体和介电层结构使用第二半导体晶粒上的第一绝缘包封体封装。第二半导体晶粒和第一绝缘包封体使用第二绝缘包封体封装。硅穿孔的一部分可以通过硅穿孔显露制程在第一半导体晶粒的第一侧从第一半导体基底突出,并且可以进一步形成隔离层以包围硅穿孔的突出部分。在使用第一绝缘包封体封装第一半导体之前执行硅穿孔显露制程。
前面概述了几个实施例的特征,以便本领域技术人员可以更好地理解本揭露的方面。本领域技术人员应当理解,他们可以容易地使用本揭露作为设计或修改其他制程的基础,而使用结构来实现与本文介绍的实施例相同的目的和/或实现相同的优点。本领域技术人员也应该认识到,这样的等效构造并不脱离本揭露的精神和范围,在不脱离本揭露的精神和范围的情况下,可以在本文中进行各种变化、替换和变更。
Claims (10)
1.一种半导体封装,包括:
第一半导体晶粒,包括第一半导体基底和硅穿孔,所述硅穿孔从所述半导体基底的第一侧延伸到所述半导体基底的第二侧,所述第二侧与所述第一侧相对;
第二半导体晶粒,设置在所述半导体基底的所述第一侧;
第一绝缘包封体,设置在所述第二半导体晶粒上并封装所述第一半导体晶粒,所述硅穿孔的末端与所述第一绝缘包封体的表面共面;
介电层结构,覆盖所述第一半导体晶粒和所述第一绝缘包封体;
导体结构,延伸穿过所述介电层结构并与所述硅穿孔接触;以及
第二绝缘包封体,横向封装切横向接触所述第二半导体晶粒、所述第一绝缘封装和所述介电层结构。
2.如请求项1所述的半导体封装,其中所述第二绝缘包封体的表面与所述导体结构的表面共面。
3.如请求项1所述的半导体封装,其中所述第一半导体晶粒更包括设置在所述第一半导体基底和所述介电层结构之间的隔离层,并且所述隔离层的表面与所述硅穿孔的所述末端共面。
4.如请求项1所述的半导体封装,还包括设置在所述第一半导体基底上的热增强层和设置在所述热增强层上的导通孔,其中所述热增强层包括连接在所述硅穿孔和所述导通孔之间的垫部分,并且所述导体结构由所述垫部分和所述导通孔构成。
5.如请求项1所述的半导体封装,其中所述第一半导体基底包括周边部分和变薄部分,变薄部分被所述周边部分包围,所述硅穿孔布置在所述变薄部分中并且所述周边部分的表面与所述硅穿孔的所述末端和所述第一绝缘包封体的所述表面共面。
6.一种制造半导体封装的方法,包括:
将具有硅穿孔的第一半导体基底与第二半导体基底接合;
在所述第二半导体基底上使用第一绝缘包封体封装所述第一半导体基底;
进行蚀刻制程以在所述第一绝缘包封体被覆盖下,去除所述第一半导体基底的一部分直到露出所述硅穿孔的一部分;
在所述第一半导体基底和所述第一绝缘包封体上形成介电层结构;
形成延伸穿过所述介电层结构并电连接至所述硅穿孔的导体结构;以及
形成与所述第二半导体基底的侧壁边缘、所述第一绝缘包封体的侧壁边缘和所述介电层结构的侧壁边缘接触的第二绝缘包封体。
7.如请求项6所述的方法,其中在所述蚀刻制程期间所述第一绝缘包封体被保护层覆盖。
8.如请求项7所述的方法,进一步形成隔离层,其中所述隔离层填充由所述蚀刻制程形成的凹谷结构并覆盖所述第一绝缘包封体之上的所述保护层;以及
进一步执行研磨制程直到所述第一绝缘包封体之上的所述隔离层和所述保护层被去除并且直到所述硅穿孔的末端被暴露。
9.一种制造半导体封装的方法,包括:
形成延伸穿过半导体晶粒中的第一半导体基底的硅穿孔;
在所述第一半导体晶粒上形成介电层结构和导体结构,所述介电层结构覆盖所述第一半导体晶粒的第一侧,所述导体结构延伸通过所述介电层结构以电连接至所述硅穿孔;
在所述第一半导体晶粒的第二侧将所述第一半导体晶粒连接到第二半导体晶粒,所述第二侧与所述第一侧相对;
在所述第二半导体晶粒上使用第一绝缘包封体封装所述第一半导体晶粒和所述介电层结构;以及
使用第二绝缘包封体封装所述第二半导体晶粒和所述第一绝缘包封体。
10.如请求项9所述的方法,其中在将所述第一半导体晶粒连接到所述第二半导体晶粒和使用所述第一绝缘包封体封装所述第一半导体晶粒之前执行所述硅穿孔显露制程。
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