CN113990855A - 封装件及制造方法 - Google Patents

封装件及制造方法 Download PDF

Info

Publication number
CN113990855A
CN113990855A CN202110936175.3A CN202110936175A CN113990855A CN 113990855 A CN113990855 A CN 113990855A CN 202110936175 A CN202110936175 A CN 202110936175A CN 113990855 A CN113990855 A CN 113990855A
Authority
CN
China
Prior art keywords
package
die
conductive
integrated circuit
interposer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110936175.3A
Other languages
English (en)
Inventor
黄冠育
黄松辉
侯上勇
许书嘉
黄裕允
张文耀
郑育真
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN113990855A publication Critical patent/CN113990855A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10155—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165—Material
    • H01L2224/16501—Material at the bonding interface
    • H01L2224/16503—Material at the bonding interface comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17517—Bump connectors having different functions including bump connectors providing primarily mechanical support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053—Bonding environment
    • H01L2224/80054—Composition of the atmosphere
    • H01L2224/80055—Composition of the atmosphere being oxidating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053—Bonding environment
    • H01L2224/80054—Composition of the atmosphere
    • H01L2224/80065—Composition of the atmosphere being reducing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053—Bonding environment
    • H01L2224/80054—Composition of the atmosphere
    • H01L2224/80075—Composition of the atmosphere being inert
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053—Bonding environment
    • H01L2224/80095—Temperature settings
    • H01L2224/80096—Transient conditions
    • H01L2224/80097—Heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80801—Soldering or alloying
    • H01L2224/80815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80905—Combinations of bonding methods provided for in at least two different groups from H01L2224/808 - H01L2224/80904
    • H01L2224/80906—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909—Post-treatment of the bonding area
    • H01L2224/80948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

在实施例中，中介层具有：第一侧；第一集成电路器件，通过第一组导电连接件附接至中介层的第一侧，第一组导电连接件中的每个均具有第一高度；第一管芯封装件，通过第二组导电连接件附接至中介层的第一侧，第二组导电连接件包括第一导电连接件和第二导电连接件，第一导电连接件具有第二高度，第二导电连接件具有第三高度，第三高度不同于第二高度；第一伪导电连接件，位于中介层的第一侧和第一管芯封装件之间；底部填充物，设置在第一集成电路器件和第一管芯封装件下方；以及密封剂，设置在第一集成电路器件和第一管芯封装件周围。本申请的实施例涉及封装件及制造方法。

Description

封装件及制造方法
技术领域
本申请的实施例涉及封装件及制造方法。
背景技术
由于许多电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成度的不断提高，半导体工业经历了快速发展。对于大部分而言，这种集成密度的改进来自于最小部件尺寸的连续减小，这使得更多的组件集成到给定的区域。随着对缩小电子器件的需求的增长，已经出现了对更小且更具创造性的半导体管芯封装技术的需求。这种封装系统的示例是堆叠封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部，以提供高水平的集成度和组件密度。PoP技术通常能够在印刷电路板(PCB)上生产功能增强且占用区域小的半导体器件。
发明内容
本申请的一些实施例提供了一种封装件，包括：中介层，具有第一侧；第一集成电路器件，通过第一组导电连接件附接至所述中介层的第一侧，所述第一组导电连接件中的每个均具有第一高度；第一管芯封装件，通过第二组导电连接件附接至所述中介层的第一侧，所述第二组导电连接件包括第一导电连接件和第二导电连接件，所述第一导电连接件具有第二高度，所述第二导电连接件具有第三高度，所述第三高度不同于所述第二高度；第一伪导电连接件，位于所述中介层的第一侧和所述第一管芯封装件之间；底部填充物，设置在所述第一集成电路器件和所述第一管芯封装件下方；以及密封剂，设置在所述第一集成电路器件和所述第一管芯封装件周围。
本申请的另一些实施例提供了一种制造封装件的方法，包括：在中介层的第一侧上形成第一再分布结构，所述第一再分布结构包括位于介电层中的金属线和通孔，所述第一再分布结构包括位于所述第一再分布结构的第一表面上的有源焊盘和伪焊盘，所述有源焊盘电耦接至所述金属线和通孔，所述伪焊盘与所述金属线与通孔电隔离；在所述有源焊盘上形成有源连接件；在所述伪焊盘上形成伪连接件；将第一集成电路器件附接至所述有源连接件的第一子集；将第二集成电路器件附接至所述有源连接件的第二子集，所述伪连接件位于所述中介层和所述第二集成电路器件之间；在所述中介层的第一侧上形成底部填充物，所述底部填充物具有位于所述第一集成电路器件下方的第一部分和位于所述第二集成电路器件下方的第二部分；以及用密封剂密封所述第一集成电路器件和所述第二集成电路器件。
本申请的又一些实施例提供了一种制造封装件的方法，包括：通过第一组连接件将第一集成电路器件附接至中介层的第一侧，所述第一组连接件具有同一高度；通过第二组连接件将管芯封装件附接至所述中介层的第一侧，所述第二组连接件具有多个高度，第一组伪连接件位于所述中介层和所述管芯封装件之间，所述第一组伪连接件与所述管芯封装件和所述第一集成电路器件电隔离；在所述第一集成电路器件和所述管芯封装件下方，在所述中介层的第一侧上形成底部填充物；以及用密封剂密封所述第一集成电路器件和所述管芯封装件。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1示出根据一些实施例的集成电路管芯的截面图。
图2至图6示出根据一些实施例的在用于形成管芯封装件的工艺期间的中间步骤的截面图。
图7至图12B和图19至图26是根据一些实施例的在用于形成半导体器件的工艺期间的中间步骤的截面图和俯视图。
图13至图18D是根据一些实施例的有源和伪连接件的配置的截面图和俯视图。
图27和图28是根据一些实施例的有源和伪连接件的配置的截面图。
具体实施方式
以下公开内容提供了许多不同的实施例或实例以实现本发明的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据一些实施例，使用具有可变高度的连接件将集成电路器件附接至晶圆，以解决集成电路管芯和/或晶圆的任何翘曲。在一些实施例中，连接件是通过镀方法形成的微凸块。在那些实施例中，在形成工艺期间，通过在集成电路器件和晶圆中的一者或两者上插入伪微凸块来调节特定区域中的微凸块的图案密度，来实现可变高度的微凸块。例如，如果期望第一区域具有比第二区域更短的微凸块高度，则将通过在第一区域中插入伪微凸块来增加第一区域中的微凸块的图案密度。可变高度连接件的这种形成可以防止冷焊或连接件损坏，因此可以提高器件的可靠性和良率。
现在将关于片上系统(“SoC”)来描述实施例。然而，实施例不旨在被限制，并且可以在各种各样的实施例中采用。在一些实施例中，形成管芯封装件，其包括接合在一起的多个管芯。例如，可以使用混合接合将管芯接合在一起。管芯封装件可以包括衬底贯通孔和/或介电贯通孔。除了诸如存储器管芯、I/O管芯等的另一半导体器件之外，还可以形成结合有管芯封装件的封装件。管芯封装件和半导体器件可以包括用于电连接到单个再分布结构的不同尺寸的导电部件。通过形成接合管芯的管芯封装件并且通过将管芯封装件和半导体器件结合在同一封装件中，可以减小封装件的尺寸，并且可以改善封装件的高速操作。
图1是根据一些实施例的集成电路器件50的截面图。集成电路器件50可以是逻辑管芯(例如，中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或其组合。集成电路器件50可以形成在晶圆中，其可以包括在后续步骤中被分割以形成多个集成电路器件50的不同的器件区域。集成电路器件50包括衬底52和互连结构54。
衬底52可以包括块状半导体衬底、绝缘体上半导体(SOI)衬底、多层半导体衬底等。衬底52的半导体材料可以为：硅；锗；包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或其组合。也可以使用诸如多层或梯度衬底的其他衬底。衬底52可以是掺杂或未掺杂的。诸如晶体管、电容器、电阻器、二极管等的器件可以形成在衬底52的有源表面(例如，面向上的表面)中和/或上。
具有一个或多个介电层和相应的金属化图案的互连结构54形成在衬底52的有源表面上。介电层可以是金属间介电(IMD)层。例如，可以通过诸如旋涂、化学气相沉积(CVD)、等离子体增强CVD(PECVD)、高密度等离子体化学气相沉积(HDP-CVD)等的本领域内已知的任何合适的方法由诸如未掺杂的硅酸盐玻璃(USG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、其化合物、其复合物、其组合等的低K介电材料形成IMD层。介电层中的金属化图案可以例如通过使用通孔和/或迹线在器件之间传递电信号，并且还可以包含各种电器件，诸如电容器、电阻器、电感器等。各种器件和金属化图案可以互连以执行一个或多个功能。功能可以包括存储器结构、处理结构、传感器、放大器、功率分配、输入/输出电路等。附加地，在互连结构54中和/或上形成诸如导电柱或接触焊盘的管芯连接件，以提供到电路和器件的外部电连接。本领域普通技术人员将理解，提供以上示例是出于说明性目的。可以针对给定应用适当地使用其他电路。
在一些实施例中，集成电路器件50是包括多个衬底52的堆叠器件。例如，集成电路器件50可以是诸如混合存储器立方体(HMC)模块、高带宽存储器(HBM)模块等包括多个存储器管芯的存储器件。在这样的实施例中，集成电路器件50包括通过通孔互连的多个衬底52。每个衬底52可以具有(或可以不具有)单独的互连结构54。
图2至图6示出根据一些实施例的管芯封装件100(参见图6)的形成的截面图。在一些实施例中，管芯封装件100是例如片上系统(SoC)封装件、集成电路上系统(SoIC)封装件等。现在参考图1，示出半导体器件102。半导体器件102可以是半导体器件，诸如存储器件、逻辑器件、功率器件、这些器件的组合等，其被设计为与管芯封装件100内的其他器件协同工作。然而，可以利用任何合适的功能。
在实施例中，半导体器件102包括第一衬底104、第一有源器件(未单独示出)、第一金属化层106、接合层108以及接合层108内的接合金属110。第一衬底104可以包括掺杂或未掺杂的块状硅、或绝缘体上硅(SOI)衬底的有源层。通常，SOI衬底包括诸如硅、锗、锗硅、SOI、绝缘体上锗硅(SGOI)或其组合的半导体材料的层。可以使用的其他衬底包括多层衬底、梯度衬底或混合取向衬底。
包括各种有源器件的第一有源器件和诸如晶体管、电容器、电阻器、电感器等的无源器件可以用于产生用于半导体器件102的设计的期望的结构和功能需求。可以在第一衬底104内或上使用任何合适的方法形成第一有源器件。
第一金属化层106形成在第一衬底104和第一有源器件上方并且被设计为连接各个有源器件以形成功能电路。在实施例中，第一金属化层106由介电材料和导电材料的交替层形成并且可以通过诸如沉积、镶嵌、双镶嵌等的任何适合的工艺形成。在实施例中，可能存在通过至少一个层间介电层(ILD)与第一衬底104分离的四个金属化层，但是第一金属化层106的精确数目取决于设计。
接合层108沉积在第一金属化层106上方。接合层108可以用于熔融接合(也称为氧化物-氧化物接合或电介质-电介质接合)。根据一些实施例，接合层108由诸如氧化硅、氮化硅等的含硅介电材料形成。可以使用诸如CVD、高密度等离子体化学气相沉积(HDPCVD)、PVD、原子层沉积(ALD)等的任何适当方法来沉积接合层108。可以例如使用化学机械抛光(CMP)工艺来平坦化接合层108。
接合金属110可以形成在接合层108内。在实施例中，可以通过首先在接合层108的顶面上方施加光刻胶并图案化，首先在接合层108内形成开口来形成接合金属110。然后将图案化的光刻胶用作蚀刻掩模以蚀刻接合层108来形成开口。可以通过诸如干蚀刻(例如，反应离子蚀刻(RIE)或中性束蚀刻(NBE)等)、湿蚀刻等合适的工艺来蚀刻接合层108。接合金属110也可以被称为“接合焊盘”或“金属焊盘”。
一旦形成开口，就在接合层108内的开口中填充接合金属110。在实施例中，接合金属110可以包括晶种层和金属板。晶种层可以毯式沉积在接合层108的顶面上方，并且可以包括例如铜层。取决于期望的材料，可以使用诸如溅射、蒸发或等离子体增强化学气相沉积(PECVD)等工艺来沉积晶种层。可以通过诸如电或无电镀的镀工艺将板状金属沉积在晶种层上方。板状金属可以包括铜、铜合金等。在一些实施例中，板状金属可以是填充材料。阻挡层(未单独示出)可以在晶种层之前毯式沉积在接合层108的顶面上方。阻挡层可以包括钛、氮化钛、钽、氮化钽等。
仍然参考图2，半导体器件102可以包括延伸穿过衬底104以促进电信号传输的衬底贯通孔(TSV)112。在其他实施例中，半导体器件102不包括TSV 112。在实施例中，可以通过首先在衬底104中形成衬底贯通孔(TSV)开口来形成TSV 112。可以通过施加并图案化光刻胶(未示出)以暴露衬底104的区域，然后将衬底104的暴露部分蚀刻到期望的深度，来形成TSV开口。可以形成TSV开口以便至少比形成在衬底104内和/或上的有源器件在衬底104内延伸更远，并且可以延伸到大于衬底104的最终期望高度的深度。因此，虽然深度取决于整体设计，但是距衬底104上的有源器件的深度可以在约20μm至约200μm之间，例如距衬底104上的有源器件的深度为约50μm。
一旦在衬底104内形成TSV开口，就可以将TSV开口加衬有衬垫(未示出)。衬垫可以例如是由原硅酸四乙酯(TEOS)或氮化硅形成的氧化物，但是可以替代地使用任何合适的介电材料。可以使用等离子体增强化学汽相沉积(PECVD)工艺形成衬垫，但是可以可选地使用诸如物理汽相沉积或热工艺的其他合适的工艺。附加地，衬垫可以形成为介于约0.1μm和约5μm之间的厚度，诸如约1μm。
一旦沿TSV开口的侧壁和底部形成衬垫，就可以形成阻挡层(也未独立示出)，并且可以用第一导电材料填充TSV开口的其余部分，从而形成TSV 112。第一导电材料可以包括铜，但是可以可选地利用诸如铝、合金、掺杂的多晶硅、其组合等的其他合适的材料。可以通过将铜电镀到晶种层(未示出)上，填充和过填充TSV开口来形成第一导电材料。一旦TSV开口被填充，就可以通过诸如化学机械抛光(CMP)的平坦化工艺去除TSV开口之外的多余衬垫、阻挡层、晶种层和第一导电材料，但是可以使用任何合适的去除工艺。在一些实施例中，TSV 112可以形成为具有介于约0.5μm和10μm之间的宽度，诸如约2μm。在一些实施例中，TSV112可以形成为具有介于约1μm和40μm之间的间距，诸如约10μm。然而，可以利用任何适当的尺寸。
在一些实施例中，多个半导体器件102形成在同一衬底104上，然后被分割以形成单独的半导体器件102。可以使用锯切工艺、激光工艺、蚀刻工艺等或其组合来分割半导体器件102。在一些实施例中，在分割之后，半导体器件102的厚度可以介于约30μm与约200μm之间，诸如约100μm。在一些实施例中，半导体器件102可以具有介于约1mm2和约850mm2之间的面积，诸如约30mm2。半导体器件102可以具有除这些之外的其他尺寸。在一些实施例中，可以在分割之前或之后将已知良好管芯(KGD)与有缺陷的管芯分离。
图3示出半导体器件102接合至第一晶圆120。在一些实施例中，第一晶圆120可以是应用处理器晶圆，其中形成半导体管芯(未单独示出)以与半导体器件102协同工作。但是，也可以利用任何适当的功能，诸如附加存储器或其他功能。第一晶圆120可以包括第二衬底122和第二有源器件(在图3中未单独示出)。在实施例中，第二衬底122和第二有源器件可以类似于以上关于图2描述的第一衬底104和第一有源器件。例如，第二衬底122可以是半导体衬底，并且第二有源器件可以是第二衬底122上或中形成的有源和无源器件。但是，可以利用任何合适的衬底和有源器件。
第一晶圆120还可以包括第二金属化层124、第二接合层126和第二接合金属128。在一个实施例中，第二金属化层124、第二接合层126和第二接合金属128可以类似于第一金属化层106、第一接合层108和第一接合金属110。例如，第二接合金属128可以是在已经形成第二接合层126之后置于第二接合层126中的金属。
在另一实施例中，第二接合金属128和第二接合层126形成为第二金属化层124的一部分。例如，第二接合层126可以形成为位于有源器件上面的初始介电层，同时第二接合金属128可以形成在第二接合层126内并且与有源器件相邻，但是被称为“via0”配置。然而，可以利用用于第二接合金属128和第二接合层126的任何合适的布置。
在形成第二接合层126和第二接合金属128之后，可以将半导体器件102接合至第一晶圆120。在一些实施例中，可以使用例如混合接合工艺将半导体器件102接合至第一晶圆120，其中第一接合层108接合至第二接合层126，并且第一接合金属110接合至第二接合金属128。在一些实施例中，可以首先利用例如干处理、湿处理、等离子体处理、暴露于惰性气体、暴露于H2、暴露于N2、暴露于O2等或其组合来激活第一晶圆120和半导体器件102的顶面。但是，可以使用任何合适的激活工艺。
在激活工艺之后，可以使用例如化学冲洗来清洁第一晶圆120和半导体器件102，然后对准半导体器件102并使其与第一晶圆120物理接触。例如，可以使用拾取和放置工艺将半导体器件102放置在第一晶圆120上。然后，第一晶圆120和半导体器件102经受热处理和接触压力以使第一晶圆120与半导体器件102混合接合。例如，第一晶圆120和半导体器件102可以经受的压力为约200kPa或更小，并且温度为介于约200℃和约400℃之间，以熔合第一接合层108和第二接合层126。然后，第一晶圆120和半导体器件102可以经受在第一接合金属110和第二接合金属128的材料的共晶点处或之上的温度，例如，介于约150℃和约650℃之间，以熔合金属接合焊盘。以这种方式，第一晶圆120和半导体器件102的熔合形成混合接合器件。在一些实施例中，对接合管芯进行烘焙、退火、加压或其他的处理，以强化或完成接合。
附加地，尽管以上描述将第二接合金属128描述为在第二金属化层124内，并且将第一接合金属110描述为在第一金属化层106上方，但这仅是示例性的，而不是限制性的。而是，任何合适的组合，包括第一接合金属110位于第一金属化层106内(例如，在via0层内)。在其他实施例中，可以通过直接表面接合、金属-金属接合或另一接合工艺将第一晶圆120接合至半导体器件102。直接表面接合工艺通过以下步骤来创建电介质-电介质接合或衬底-衬底接合：清洁和/或表面激活工艺、随后对相连的表面应用压力、加热和/或其他的接合工艺步骤。在一些实施例中，第一晶圆120、半导体器件102通过利用熔合导电元件而实现的金属-金属接合来接合。可以利用任何合适的接合工艺。
图4示出半导体器件102的减薄以便暴露TSV 112。在实施例中，可以利用诸如化学机械平坦化(CMP)工艺的平坦化工艺来执行半导体器件102的减薄，其中蚀刻剂和研磨剂与研磨台板一起使用，以便反应并研磨掉材料，直到形成平坦表面并暴露TSV 112。然而，也可以利用任何其他合适的暴露TSV 112的方法，诸如一系列的一个或多个蚀刻工艺。
图5示出在第二接合金属128上形成介电贯通孔(TDV)130。在其他实施例中，未形成TDV 130。在实施例中，可以通过首先在第二接合金属128上方(或者如果需要的话，在单独放置的晶种层上方)放置并图案化光刻胶(图5中未单独示出)来形成TDV 130。在实施例中，形成在光刻胶中的图案是用于TDV 130的图案。TDV 130可以形成在半导体器件102的不同侧上。然而，也可以利用用于TDV 130的图案的任何合适的布置。在一些实施例中，TDV130的间距可以大于TSV 112的间距。
一旦放置并图案化光刻胶，就可以在光刻胶内形成TDV 130。在实施例中，TDV 130包括诸如铜、钨、其他导电金属等的一种或多种导电材料，并且可以例如通过电镀、化学镀等形成。在已经形成TDV 130的导电材料之后，可以使用诸如等离子体灰化工艺或湿化学剥离的适当去除工艺来去除光刻胶。在一些实施例中，TDV 130可以形成为具有介于约10μm和约200μm之间的宽度，诸如约150μm。附加地，TDV 130可以形成为具有介于约35μm和约250μm之间的高度，诸如约180μm。然而，可以利用任何适当的尺寸。
在一些实施例中，在形成TDV 130之后，可以使每个半导体器件102的第一衬底104凹进。可以使用例如一个或多个蚀刻工艺(诸如湿蚀刻工艺或干蚀刻工艺)使第一衬底104凹进。然而，可以使用使第一衬底104凹进以使得TSV 112远离第一衬底104延伸的任何合适的方法。以这种方式，TSV 112可以从管芯封装件100的第一衬底104突出，以促进后续处理步骤中的外部连接。
参考图6，形成介电层132并执行分割工艺，从而形成单独的管芯封装件100。图6中示出单独的管芯封装件100。在使第一衬底104凹进之后，可以在半导体器件102和TDV 130上方形成介电层132。在一些实施例中，介电层132可以是诸如低温聚酰亚胺材料的材料，但是也可以利用任何其他合适的电介质，诸如PBO、另一聚合物、树脂、环氧树脂等或其组合。在一些情况下，介电层132可以被固化。
在形成介电层132之后，可以减薄第一晶圆120，然后执行分割工艺以分割单独的管芯封装件100。在实施例中，可以利用诸如CMP工艺或研磨工艺的平坦化工艺来减薄第一晶圆120的后侧。然而，也可以利用任何合适的用于减薄第一晶圆120的工艺，诸如一系列的一个或多个蚀刻或抛光和蚀刻的组合。
在一些实施例中，介电层132可以形成为覆盖TDV 130和TSV 112，并且随后可以被凹进以暴露TDV 130和TSV 112。例如，可以使用诸如CMP工艺或研磨工艺的平坦化工艺或诸如湿蚀刻工艺或干蚀刻工艺的一种或多种蚀刻工艺来使介电层132凹进。然而，可以使用使介电层132凹进的任何合适的方法。以这种方式，将TDV 130和TSV 112暴露以促进在随后的处理步骤中的外部连接。
在一些实施例中，在形成介电层132之后(并且在可选的凹进步骤之后)，在工艺变化内，介电层132、TDV 130和TSV 112的表面共面。可以使用锯切工艺、激光工艺、蚀刻工艺等或其组合来分割第一晶圆120。
图7至图12B和图19至图26是根据一些实施例的在用于形成半导体器件的工艺期间的中间步骤的截面图和俯视图。图13至图18D是根据各种实施例的有源和伪连接件的配置的截面图和俯视图。在图7至图12A和图19-图25中，通过将各种集成电路器件50和管芯封装件100接合至中介层(interposer)170的前侧来形成器件封装件200。在一些实施例中，器件封装件200是晶圆上芯片(CoW)封装件，但是应当理解，实施例可以应用于其他三维集成电路(3DIC)封装件。在图25中，通过将器件封装件200安装到封装衬底上来形成器件封装件400。在实施例中，器件封装件400是衬底上晶圆上芯片
Figure BDA0003213257780000111
封装件，但是应当理解，实施例可以应用于其他3DIC封装件。
图7是根据一些实施例的中介层170的截面图。尽管仅示出一个中介层170，但是应当理解，中介层170可以形成在具有多个器件区域的晶圆中，每个器件区域用于形成一个中介层170。中介层170包括衬底172、贯通孔174和互连结构176。
衬底172可以是块状半导体衬底、SOI衬底、多层半导体衬底等。衬底172的半导体材料可以为：硅；锗；包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或其组合。也可以使用诸如多层或梯度衬底的其他衬底。衬底172可以是掺杂或未掺杂的。诸如晶体管的有源器件可以(或者可以不)在衬底172的前表面(例如，面向上的表面)中和/或上。诸如电容器、电阻器、二极管等的无源器件可以(或可以不)在衬底172的前表面中和/或上。
贯通孔174形成为从衬底172的前表面延伸到衬底172中。当衬底172是硅衬底时，贯通孔174有时也称为衬底贯通孔或硅贯通孔(TSV)。可以通过例如通过蚀刻、铣削、激光技术、其组合等在衬底172中形成凹槽来形成贯通孔174。可以诸如通过使用氧化技术在凹槽中形成薄介电材料。薄阻挡层可以诸如通过CVD、原子层沉积(ALD)、物理气相沉积(PVD)、热氧化、其组合等共形沉积在衬底172的前侧上方和开口中。阻挡层可以由氮化物或氮氧化物形成，诸如氮化钛、氮氧化钛、氮化钽、氮氧化钽、氮化钨、其组合等。可以将导电材料沉积在薄阻挡层上方和开口中。可以通过电化学镀工艺、CVD、ALD、PVD、其组合等来形成导电材料。导电材料的示例是铜、钨、铝、银、金、其组合等。通过例如化学机械抛光(CMP)从衬底172的前侧去除多余的导电材料和阻挡层。因此，贯通孔174可以包括导电材料，并且薄阻挡层介于导电材料和衬底172之间。
互连结构176形成在衬底172的前表面上方，并且用于将衬底172的器件(如果有的话)和/或贯通孔174电连接在一起和/或电连接到外部器件。互连结构176可以包括一个或多个介电层178和位于介电层中的相应的金属化图案180。金属化图案180可以包括通孔和/或迹线，以将任何器件和/或贯通孔174互连在一起和/或互连到外部器件。介电层178可以由氧化硅、氮化硅、碳化硅、氮氧化硅、低K介电材料形成，诸如PSG、BPSG、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、其化合物、其复合物、其组合等。介电层178可以通过任何合适的方法沉积，诸如旋涂、CVD、PECVD、HDP-CVD等。可以例如通过使用光刻技术在介电层上沉积和图案化光刻胶材料以暴露介电层的要成为金属化图案的部分，来在介电层178中形成金属化图案180。可以使用诸如各向异性干蚀刻工艺的蚀刻工艺来在介电层178中创建与介电层178的暴露部分对应的凹槽和/或开口。凹槽和/或开口可以加衬有扩散阻挡层并填充有导电材料。扩散阻挡层可以由通过ALD等沉积的TaN、Ta、TiN、Ti、CoW等的一层或多层形成，并且导电材料可以由铜、铝、钨、银、其组合等形成，并且可以通过CVD、PVD等沉积。可以诸如通过使用CMP来去除介电层178上的任何多余的扩散阻挡层和/或导电材料。
图8至图10示出在图7的一部分的详细视图中在互连176上形成电连接件。在图8中，示出介电层178在最顶部金属化图案180上方延伸并覆盖。然而，在一些实施例中，介电层178的顶面和最顶部金属化图案180在工艺变化内共面。在图8中，金属化图案180A电耦接至互连结构中的其他金属化图案，并且随后可以电耦接至集成电路器件50和/或管芯封装件100(也可以称为有源金属化图案180A)。金属化图案180B与互连结构中的其他金属化图案电隔离(也可以称为伪金属化图案180B)，并且随后将不电耦接至集成电路器件50和/或管芯封装件100。在一些实施例中，最顶部金属化图案180(所示的180A和180B是其一部分)可以被称为焊盘180或凸块下金属化(UBM)180。
尽管示出单个伪焊盘180B，但是在一些实施例中，根据需要可以包括更多伪焊盘180B。例如，取决于中介层170和整个封装结构的设计，单个互连结构176可以包括数百、数千或更多的伪焊盘180B。如下面更详细地讨论的，伪焊盘180B放置在互连件176的特定区/区域中，以增加焊盘180的图案密度，并且在那些特定区/区域中形成导电凸块204，使得焊盘180的图案密度的差异和形成导电凸块204改变那些特定区/区域中的导电凸块204的形成速率。例如，可以通过诸如电镀的镀工艺来形成导电凸块204，并且焊盘180和导电凸块204的图案密度影响并改变镀速率。具体地，焊盘180和导电凸块204的图案密度较高的区/区域的镀速率较慢，焊盘180和导电凸块204的图案密度较低的区/区域的镀速率较高。如下面进一步讨论的，镀速率的这种差异可以用于调节中介层170的不同区/区域中的导电凸块204的高度，以处理中介层170和/或随后附接至中介层170的集成电路器件50和管芯封装件100的翘曲。
在图9中，在互连结构176上沉积并图案化光刻胶材料182，以暴露介电层178的部分，其中将使用后续图案化工艺来图案化暴露的介电层178。诸如各向异性干蚀刻工艺的蚀刻工艺可以用于在介电层178中创建凹槽和/或开口，以使焊盘180的与介电层178的暴露部分对应的部分暴露。
在图10中，包括导电凸块204和导电连接件206的电连接件形成在暴露焊盘180上。导电凸块204A和导电连接件206A(也可以称为有源导电凸块204A和有源导电连接件206A)电耦接至有源金属化图案180A，并且随后可以电耦接至集成电路器件50和/或管芯封装件100。导电凸块204B和导电连接件206B(也可以称为伪导电凸块204B和伪导电连接件206B)电耦接至伪金属化图案180B，并且与互连结构中的其他金属化图案电隔离，并且随后将不电耦接至集成电路器件50和/或管芯封装件100。
导电凸块204由诸如铜、铝、金、镍、钯等的导电材料或其组合形成，并且可以通过溅射、印刷、电镀、无电镀、CVD等形成。导电凸块204可以是无焊料的并且具有基本竖直的侧壁，并且可以被称为柱。导电凸块204电和物理连接到互连结构176。有源导电连接件206A将导电凸块204接合至其他器件(诸如随后接合的器件100和50)上的连接件(见图12A-图12B)。伪导电连接件206B不将导电凸块204接合至任何其他器件(见图12A-图12B)。导电连接件206可以由诸如焊料的导电材料形成，并且可以被称为焊帽。可以通过诸如蒸发、电镀、印刷、焊料转移、焊球放置等方法，通过首先在导电凸块204上形成焊料层来形成导电连接件206。一旦形成焊料层，就可以执行回流工艺以便将导电连接件206成形为期望的凸块形状。导电凸块204和导电连接件206一起形成微凸块。
图11示出图7中的结构，其中如图8至图10的详细视图中所讨论的，在焊盘180上形成导电凸块204和导电连接件206。
在图12A中，将多个集成电路器件50和一个或多个管芯封装件100附接至中介层170。可以例如使用拾取和放置工具将多个集成电路器件50和一个或多个管芯封装件100附接至互连结构176。
各种集成电路器件50可以包括具有不同功能的多个器件。互连结构54和176被连接以物理和电连接集成电路器件50和中介层170。集成电路器件50每个均可以具有单个功能(例如，逻辑器件、存储器管芯等)，或者可以具有多种功能(例如，SoC)。在实施例中，集成电路器件50是诸如HBM模块的存储器件。集成电路器件50还可以包括诸如CPU的逻辑器件。
管芯封装件100(在图6中示出示例性管芯封装件100)包括多个器件。管芯封装件100的TDV 130和贯通孔112连接到导电连接件206，以物理和电连接管芯封装件100和中介层170。
一个或多个管芯封装件100的后表面距互连结构176的高度为H1，集成电路器件50的后表面距互连结构176的高度为H2。高度H1和H2可以相同或可以不同。在一些实施例中，高度H1在约50μm至约800μm的范围内，并且高度H2在约50μm至约800μm的范围内。
在中介层170形成在晶圆中的实施例中，多个集成电路器件50和一个或多个管芯封装件100可以附接在晶圆的不同器件区域中，其将在后续步骤中被分割以形成多个器件封装件200。图12B是图12A的结构的示例性俯视图，示出区域200A和200B。区域200A和200B每个均包含多个器件50和单个管芯封装件100。在一些实施例中，诸如图12B的实施例，集成电路器件50对称地布置在管芯封装件100附近。在一些实施例中，集成电路器件50不对称地布置在管芯封装件100附近。不对称的布局可以允许集成电路器件50位于更靠近管芯封装件100的输入/输出(I/O)连接区域的位置。
在所示的实施例中，多个集成电路器件50和一个或多个管芯封装件100通过包括导电凸块202(也可以称为有源导电凸块202)、有源导电凸块204A和导电连接件206的连接附接到互连结构176。有源导电凸块202电和物理连接到互连结构54，有源导电凸块204A电和物理连接到互连结构176。导电连接件206将有源导电凸块202和204A接合。
互连结构176上的伪导电凸块204B和伪导电连接件206B不连接至接合到互连结构的多个集成电路器件50或一个或多个管芯封装件100。在所示的实施例中，没有对应的有源导电凸块202被接合到伪导电凸块204B和伪导电连接件206B。在一些实施例中，多个集成电路器件50和一个或多个管芯封装件100还可以包括伪导电凸块202，其可以接合至伪导电凸块204B和伪导电连接件206B。
图13和图14示出在接合管芯封装件100和中介层170之前和之后的封装件300的一部分的简化形式。在图13中，在被接合在一起之前示出管芯封装件100和中介层170的一部分。如图13所示，使管芯封装件100翘曲或弯曲，使得形成在管芯封装件100上的有源导电凸块202上的有源导电连接件206A的接合表面遵循弯曲轮廓310A。在该示例中，管芯封装件100是弯曲的，使得边缘延伸得比中心区域高(有时称为微笑轮廓(smiling profile))。在一些实施例中，管芯封装件是弯曲的，使得边缘延伸得比中心区域低(有时称为皱眉轮廓(frowning profile))(例如参见图17)。如果形成在中介层170上的有源导电凸块204A的有源导电连接件206A的接合表面不具有相似的弯曲轮廓，则形成在管芯封装件100上的有源导电凸块202上的有源导电连接件206A的接合表面的弯曲轮廓310A可能引起诸如冷焊或连接件损坏的问题。
如以上所述和下面更详细地讨论的，伪导电凸块204B放置在中介层170的特定区/区域中，以增加那些特定区/区域中的导电凸块204的图案密度，使得导电凸块204的图案密度的差异改变那些特定区/区域中的导电凸块204的形成速率。形成速率的这种差异可以用于调节中介层170的不同区/区域中的导电凸块204的高度，以处理中介层170和/或随后附接至中介层170的集成电路器件50和管芯封装件100的翘曲。因此，如图13所示，形成在中介层170上的有源导电凸块204A上的有源导电连接件206A的接合表面遵循类似于管芯封装件100的弯曲轮廓310A的弯曲轮廓310B。在图13所示的实施例中，中介层170上的有源导电凸块204A形成为在中介层170的中心区域中较短，并且随着远离中心区域而变高。例如，外部有源导电凸块204A可以形成为高度H3，中心有源导电凸块204A可以形成为高度H5，并且外部凸块和中心凸块之间的有源导电凸块204A可以形成为高度H4。在一些实施例中，高度H3大于H4和H5，高度H4大于H5并且小于H3，并且高度H5小于H4和H5。在一些其他实施例中，这些高度的关系可以颠倒，使得H5最大，而H3最小。在其他实施例中，高度H4可以是最大高度。
在一些实施例中，管芯封装件100可以在管芯封装件100的下表面弯曲，使得在管芯封装件100的边缘处的下表面比管芯封装件100的中心区域的下表面高出距离D1。在一些实施例中，距离D1在从20μm到50μm的范围内。
在图14中，将管芯封装件100接合至中介层170，其中，中介层170上的有源导电凸块204A具有变化的高度，以解决管芯封装件100的翘曲和/或弯曲。
图15示出中介层170的一部分上的有源和伪导电焊盘180A和180B的示例性布局(以及有源和伪导电凸块204A和204B的布局)。在示出的部分中，中介层170被划分为区域402和404，其中区域402是可以形成伪焊盘180B的区域，区域404是不能形成伪焊盘180B的区域。在一些实施例中，区域402与有源焊盘180A分开距离D2。在一些实施例中，距离D2在从15μm到50μm的范围内。距离D2确保伪导电凸块204B确实干扰有源导电凸块204A。虽然，图15示出区域402和404的棋盘图案，但是其他图案，例如区域402的行、列、同心圆等或其组合，在本公开的范围内。
图16A、图16B、图16C和图16D是区域200A或200B(见图12B)的布局的实施例，以使有源导电凸块204A实现图13和图14中的微笑弯曲轮廓310B。如图16A所示，管芯封装件100的占用区域内的有源和伪焊盘180A和180B的布局配置在多个分区或区(在图16A-图16D中标记为分区1-3)中，使得伪焊盘180B的配置可以在每个不同分区中不同。在图16A-图16D中，管芯封装件100的占用区域内的伪焊盘180B的布局被划分为三个分区，分区1和2由以管芯封装件100的占用区域的中心点为中心的同心圆形成，分区3是管芯封装件100的占用区域的剩余部分。在图16A-图16D中，分区1在管芯封装件100的占用区域的中心，分区2是围绕区域1的环，分区3是管芯封装件100的占用区域的不在分区1或分区2中的剩余部分。
如上所述，有源和伪焊盘180A和180B的图案密度影响有源导电凸块204A的形成高度，使得有源和伪焊盘180A和180B的较大图案密度导致较短的有源导电凸块204A。为了实现图13和图14中的微笑弯曲轮廓310B，其中较高的有源导电凸块204A朝向管芯封装件100的占用区域的外边缘，而较短的有源导电凸块204A在管芯封装件100的占用区域的中心区域，因此在管芯封装件100的占用区域的中心区域中，有源和伪焊盘180A和180B的图案密度需要更大。在该实施例中，分区1中的有源和伪焊盘180A和180B的图案密度大于分区2和3两者，分区3中的有源和伪焊盘180A和180B的图案密度小于分区2和1两者，并且分区2中的有源和伪焊盘180A和180B的图案密度在分区2和1之间。
在图16A中，伪焊盘180B的形状为圆形，并且在不同分区中具有不同的尺寸。例如，伪焊盘180B在分区1中最大，在分区2中较小，在分区3中最小(或不存在)。图16B示出与图16A类似的配置，除了伪焊盘180B具有不同的形状并且为正方形或长方形。
在图16C中，伪焊盘180B的形状为圆形，并且在每个分区中具有相似的尺寸，其中不同分区在每个区域402中具有不同数量的伪焊盘180B。例如，分区1具有每区域402最多的伪焊盘180B，分区2具有的每区域402的伪焊盘180B少于分区1，分区3具有的每区域402的伪焊盘180B少于分区2(可能为零)。图16D示出与图16C类似的配置，除了伪焊盘180B具有不同的形状并且为正方形或长方形。
尽管仅示出具有各种尺寸和形状的四个配置，但是本公开考虑了伪焊盘180B的更多尺寸和形状，以实现分区1-3的变化的图案密度目标。此外，管芯封装件100的占用区域(或甚至整个中介层170的占用区域)可以被划分为更多或更少的分区，诸如2个分区、4个分区、5个分区或甚至更多的分区。
尽管伪焊盘、伪凸块和伪连接件已被描述为仅在管芯封装件100的占用区域内，但是在一些实施例中，存在伪焊盘、伪凸块和伪连接件。例如，在集成电路器件50的占用区域内或在集成电路器件50和管芯封装件100的占用区域外，可以存在伪焊盘、伪凸块和伪连接件。
在实施例中，其中仅在管芯封装件100的占用区域内形成伪焊盘、伪凸块和伪连接件，集成电路器件50的占用区域内的导电凸块204和202形成为具有相同的高度，而管芯封装件100的占用区域内的导电凸块204和/或202形成为具有不同的高度。
图17示出在接合管芯封装件100和中介层170之前的封装件300的一部分的简化形式。该实施例类似于图13和图14中的实施例，除了该实施例具有皱眉弯曲轮廓312A和312B。例如，在该实施例中，较高的有源导电凸块204A在中介层170的中心区域中，而较短的有源导电凸块204A在中心区域之外。关于该实施例的细节类似于先前描述的实施例的细节，本文不再赘述。
图18A、图18B、图18C和图18D是区域200A或200B(见图12B)的布局的实施例，以使有源导电凸块204A实现图17中的皱眉弯曲轮廓312B。该实施例类似于图16A-图16B中的实施例，除了该实施例具有皱眉弯曲轮廓312A和312B。关于该实施例的细节类似于先前描述的实施例的细节，本文不再赘述。
为了实现图17中的皱眉弯曲轮廓312B，其中较高的有源导电凸块204A在管芯封装件100的占用区域的中心区域中，而较短的有源导电凸块204A在管芯封装件100的占用区域的中心区域之外，因此在管芯封装件100的占用区域的中心区域外，有源和伪焊盘180A和180B的图案密度需要更大。在该实施例中，分区1中的有源和伪焊盘180A和180B的图案密度小于分区2和3两者，分区3中的有源和伪焊盘180A和180B的图案密度大于分区2和1两者，并且分区2中的有源和伪焊盘180A和180B的图案密度在分区2和1之间。
在图18A中，伪焊盘180B的形状为圆形，并且在不同分区中具有不同的尺寸。例如，伪焊盘180B在分区3中最大，在分区2中较小，在分区1中最小(或不存在)。图18B示出与图18A类似的配置，除了伪焊盘180B具有不同的形状并且为正方形或长方形。
在图18C中，伪焊盘180B的形状为圆形，并且在每个分区中具有相似的尺寸，其中不同分区在每个区域402中具有不同数量的伪焊盘180B。例如，分区3具有每区域402最多的伪焊盘180B，分区2具有的每区域402的伪焊盘180B少于分区3，分区1具有的每区域402的伪焊盘180B少于分区2(可能为零)。图18D示出与图16C类似的配置，除了伪焊盘180B具有不同的形状并且为正方形或长方形。
中介层170具有带有可变高度的连接件，其可以解决集成电路管芯和/或晶圆的翘曲。在一些实施例中，连接件是通过镀方法形成的微凸块。在那些实施例中，在形成工艺期间，通过在集成电路器件和晶圆中的一者或两者上插入伪微凸块来调节特定区域中的微凸块的图案密度，来实现可变高度的微凸块。例如，如果期望第一区域具有比第二区域更短的微凸块高度，则将通过在第一区域中插入伪微凸块来增加第一区域中的微凸块的图案密度。可变高度连接件的这种形成可以防止冷焊或连接件损坏，因此可以提高器件的可靠性和良率。
在图19中，将底部填充材料210分配在集成电路器件50与管芯封装件100和互连结构176之间。底部填充材料210围绕有源和导电凸块202A/B和204A/B、有源和伪导电连接件206A/B。底部填充材料210具有沿集成电路器件50和管芯封装件100的侧部向上延伸的倒角。底部填充材料210可以是任何可接受的材料，诸如聚合物、环氧树脂、模制底部填充物等。底部填充材料210可以通过毛细管流动工艺形成。底部填充物210将伪导电凸块204B和伪导电连接件206B与管芯封装件100分离并隔离。
在图20中，在各个组件上形成密封剂212。密封剂212可以是模塑料、环氧树脂等，并且可以通过压缩模塑、传递模塑等来应用。密封剂212可以形成在互连结构176上方，使得集成电路器件50、管芯封装件100和底部填充材料210被掩埋或覆盖。然后使密封剂212固化。在一些实施例中，使密封剂212减薄，使得密封剂212、集成电路器件50和管芯封装件100的顶面齐平。
在图21中，将中间结构翻转以准备对衬底172的后侧进行处理。可以将中间结构放置在载体衬底214或其他合适的支撑结构上以进行后续处理。例如，载体衬底214可以附接至密封剂212。中间结构可以通过释放层216附接至载体衬底214。释放层216可以由聚合物基材料形成，释放层可以与载体衬底214一起被从上面的结构中去除。在一些实施例中，载体衬底214是诸如块状半导体或玻璃衬底的衬底，并且可以具有任何厚度，诸如约300mm的厚度。在一些实施例中，释放层216是诸如光热转换(LTHC)释放涂层的环氧树脂基热释放材料，该材料在被加热时失去其粘性。
在图22中，使衬底172减薄以暴露贯通孔174。在一些实施例中，衬底172和贯通孔174的暴露表面齐平。贯通孔174的暴露可以通过诸如研磨过程、化学机械抛光(CMP)或其他可接受的去除工艺的减薄工艺来实现。在一些实施例(未示出)中，可以执行凹进工艺以使衬底172凹进，使得贯通孔174从衬底172的后侧突出。凹进工艺可以是例如适当的回蚀刻工艺。可以在衬底172的后侧上形成绝缘层，其围绕并保护贯通孔174的突出部分。
在图12中，再分布结构220形成在衬底172的后侧上方。再分布结构220包括介电层222、UBM 224和导电凸块226。作为实例示出了再分布结构220。更多或更少的介电层和导电层可以形成在再分布结构220中。如果将要形成更多的介电层和金属化图案，那么可以重复下面所讨论的步骤和工艺。
作为形成再分布结构220的示例，将介电层222沉积在衬底172的后侧和贯通孔174上。在一些实施例中，介电层222由光敏材料形成，诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等，可以使用光刻掩模将其图案化。可通过旋转涂布、层压、CVD等或其组合形成介电层222。然后图案化介电层222。图案化形成开口以暴露贯通孔174的一部分。当介电层222为感光材料时，诸如通过将介电层222暴露于光的可接受的工艺实施图案化，或者例如，通过使用各向异性蚀刻的蚀刻实施图案化。如果介电层222是光敏材料，则可以在曝光之后使介电层222显影。
然后，形成UBM 224。UBM 224包括在介电层222的主表面上并沿其延伸的导线。UBM224还包括延伸穿过介电层222以物理和电连接到贯通孔174的导电通孔。晶种层(未示出)形成在介电层222上方和延伸穿过介电层222的开口中。在一些实施例中，晶种层为金属层，其可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。例如，可以使用PVD等形成晶种层。
然后在晶种层上形成并且图案化介电层228。在一些实施例中，介电层228由可以使用光刻掩模图案化的诸如光刻胶、PBO、聚酰亚胺、BCB等的光敏材料形成。介电层228可以通过旋涂、层压、CVD等或其组合形成，并且可以暴露于光以进行图案化。介电层228的图案对应于UBM 224。图案化形成穿过介电层228的开口以暴露晶种层。然后，在介电层228的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，诸如铜、钛、钨、铝等。导电材料和晶种层下面的部分的组合形成UBM 224。
然后形成导电凸块226。在UBM 224和介电层228上形成并图案化介电层230。介电层230可以类似于介电层228。介电层230可以暴露于光以进行图案化。介电层230的图案对应于导电凸块226。图案化形成穿过介电层230的开口，以暴露UBM 224的一部分。然后，在介电层230的开口中和UBM 224的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，诸如铜、钛、钨、铝等。因为UBM 224被介电层230中的开口暴露，所以在开口中没有形成晶种层。而是，导电材料直接且物理地形成在UBM224上。通过执行镀工艺来形成导电材料，该镀工艺具有与用于形成UBM 224的导电材料的镀工艺相同的镀工艺参数。特别地，在UBM 224和导电凸块226之间没有形成晶种层。而是，导电凸块226的导电材料通过使用UBM 224的晶种层执行镀工艺而形成。
在图24中，导电连接件232形成在导电凸块226上。导电连接件232可以由诸如焊料的导电材料形成，并且可以通过诸如蒸发、电镀、印刷、焊料转移、焊球放置等方法，通过首先在导电凸块226上形成焊料层来形成。一旦形成焊料层，就可以执行回流工艺以便将导电连接件232成形为期望的凸块形状。导电连接件232可以是球栅阵列(BGA)连接件、焊球、可控塌陷芯片连接(C4)凸块等。UBM 224从贯通孔174横向偏移导电连接件232。由于在UBM224和导电凸块226之间没有形成晶种层，所以导电凸块226是从UBM 224连续延伸到导电连接件232的导电材料。
在图25中，执行载体去接合以将载体衬底214与密封剂212分离(去接合)。根据一些实施例，脱粘包括将诸如激光或极紫外(UV)光的光投射到释放层216上，使得释放层216在光的热量下分解，并且可以去除载体衬底214。然后翻转该结构并且放置在带上。随后，将中介层170沿着相邻器件区域之间的划线区域分割以形成器件封装件200。可以通过锯切、切割等来进行分割。作为分割工艺的结果，中介层170和密封剂212的边缘是邻接的。换句话说，中介层170的外侧壁具有与密封剂212的外侧壁相同的宽度。介电层228和介电层230可以在载体去接合之前或之后可选地被去除。
在图26中，通过将器件封装件200安装到封装衬底410上来形成器件封装件300。封装衬底410可以由半导体材料制成，诸如硅、锗等。替代地，也可以使用化合物材料，诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化砷镓、磷化镓铟、其组合等。附加地，封装衬底410可以是SOI衬底。在一些实施例中，SOI衬底包括半导体材料层，诸如外延生长的硅、锗、硅锗、SOI或其组合。在一个替代实施例中，封装衬底410基于诸如玻璃纤维增强树脂芯的绝缘芯。一种示例性芯材料是玻璃纤维树脂，诸如FR4。芯材料的替代材料包括双马来酰亚胺-三嗪(BT)树脂，或者其他印刷电路板(PCB)材料或膜。诸如味之素(Ajinomoto)堆积膜(ABF)的堆积膜或其他叠层可以用于封装衬底410。
封装衬底410可以包括有源和无源器件。作为本领域的普通技术人员将会意识到，可以使用各种器件(诸如晶体管、电容器、电阻器、其组合等)来满足器件封装件400设计的结构和功能要求。可以使用任何合适的方法来形成器件。
封装衬底410还可以包括金属化层和通孔以及位于金属化层和通孔上方的接合焊盘412。金属化层可以形成在有源和无源器件上方并且设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如低k介电材料)和导电材料(例如铜)的交替层形成，具有将导电材料层互连的通孔，并且可以通过任何合适的工艺(例如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，封装衬底410基本上没有有源和无源器件。
导电连接件232回流以将器件封装件200附接至接合焊盘412，从而将中介层170接合至封装衬底410。导电连接件232将封装衬底410(包括位于封装衬底410中的金属化层)电和物理耦接至器件封装件200。如上所述，底部填充材料210的物理上分离的部分可以减少器件封装件200的翘曲。因此可以减小封装衬底410和中介层170之间的对峙高度变化，这可以帮助避免导电连接件232回流时的冷焊和桥接。因此可以提高制造良率。
导电连接件232可以在其回流之前在其上形成环氧树脂助焊剂，而在将器件封装件200附接到封装衬底410之后，剩余环氧树脂助焊剂的至少一些环氧树脂部分。剩余的环氧树脂部分可以用作底部填充物，以减少应力并保护由导电连接件232回流引起的接头。
在一些实施例中，在安装到封装衬底410上之前，将无源器件(例如，未示出的表面安装器件(SMD))附接至器件封装件400(例如，接合至接合焊盘412)。在一些实施例中，无源器件可以与导电连接件232接合至封装衬底410的同一表面。
底部填充物414可以形成在器件封装件200和封装衬底410之间，围绕导电连接件232、导电凸块226和UBM 224。由于形成UBM 224的工艺，它们在形成后不被电介质或绝缘层包围。这样，底部填充物414直接接触并沿UBM 224的侧部延伸。此外，底部填充物414是从封装衬底410延伸到介电层222的连续材料。底部填充物414可以在附接器件封装件200之后通过毛细管流动工艺形成，或者可以在附接器件封装件200之前通过适当的沉积方法形成。
可选地，散热器可以附接至器件封装件400，覆盖并围绕器件封装件200。散热器可以由具有高导热率的材料形成，诸如钢、不锈钢、铜等或其组合。散热器保护器件封装件200，并形成热路径以传导来自器件封装件400各个组件的热量。
图27示出在接合管芯封装件100和中介层170之前的封装件300的一部分的简化形式。该实施例类似于图13和图14中的实施例，除了该实施例包括位于管芯封装件100上的伪导电凸块202A，而不是位于中介层170上的伪导电凸块204A。图13-图15、图16A-图16D、图17和图18A-图18D中公开的有源和伪凸块的各种配置适用于图27中的实施例。关于该实施例的细节类似于先前描述的实施例的细节，本文不再赘述。
图28示出在接合管芯封装件100和中介层170之前的封装件300的一部分的简化形式。该实施例类似于图13、图14和图27中的实施例，除了该实施例包括位于管芯封装件100上的伪导电凸块202A和位于中介层170上的伪导电凸块204A。图13-图15、图16A-图16D、图17和图18A-图18D中公开的有源和伪凸块的各种配置适用于图28中的实施例。关于该实施例的细节类似于先前描述的实施例的细节，本文不再赘述。
还可以包括其他部件和工艺。例如，可以包括测试结构以辅助3D封装或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘(其允许对3D封装或3DIC进行测试)、使用探针和/或探针卡等。验证测试可以在中间结构以及最终结构上执行。附加地，本文公开的结构和方法可以与结合了已知良好管芯的中间验证的测试方法结合使用，以增加产量并降低成本。
本文描述的实施例可以实现优势。根据一些实施例，实施例包括带有可变高度的连接件，其可以解决集成电路管芯和/或中介层的翘曲。在一些实施例中，连接件是通过镀方法形成的微凸块。在那些实施例中，在形成工艺期间，通过在集成电路器件和晶圆中的一者或两者上插入伪微凸块来调节特定区域中的微凸块的图案密度，来实现可变高度的微凸块。例如，如果期望第一区域具有比第二区域更短的微凸块高度，则将通过在第一区域中插入伪微凸块来增加第一区域中的微凸块的图案密度。可变高度连接件的这种形成可以防止冷焊或连接件损坏，因此可以提高器件的可靠性和良率。
此外，本文所述的封装件能够结合具有不同功能或技术的器件，这可以增加功能并降低成本。通过接合半导体器件以在封装件内形成接合管芯封装件(例如，片上系统(SoC)等)，可以减小封装件的尺寸。封装件可以包括接合管芯封装件和另一半导体管芯，诸如存储器管芯、I/O管芯等。可以将接合管芯封装件和半导体管芯连接至同一再分布结构，这可以允许接合管芯封装件和半导体管芯之间的布线更短。再分布结构可以具有不同尺寸的通孔以连接到不同的器件，诸如连接到接合管芯封装件的贯通孔或连接到半导体管芯的接触焊盘。在器件的连接(例如，贯通孔或导电焊盘)的间距较小的情况下，再分布结构的单个通孔可以连接至多个连接。以这种方式使用接合管芯封装件或较短的布线可以改善封装件的高频或高速操作。接合管芯封装件可以包括多个半导体器件或半导体器件的堆叠件，这可以允许降低的成本和更大的设计灵活性。在一些情况下，在接合管芯封装件内使用不同的保护材料可以减少发生例如由于CTE不匹配或掺杂剂扩散到接合管芯封装件中而引起的缺陷的可能性。
在实施例中，中介层具有：第一侧；第一集成电路器件，通过第一组导电连接件附接至中介层的第一侧，第一组导电连接件中的每个均具有第一高度。封装件还包括：第一管芯封装件，通过第二组导电连接件连接至中介层的第一侧，第二组导电连接件包括第一导电连接件和第二导电连接件，第一导电连接件具有第二高度，第二导电连接件具有第三高度，第三高度不同于第二高度。封装件还包括位于中介层的第一侧和第一管芯封装件之间的第一伪导电连接件。封装件还包括设置在第一集成电路器件和第一管芯封装件下方的底部填充物。封装件还包括设置在第一集成电路器件和第一管芯封装件周围的密封剂。
实施例可以包括以下特征中的一个或多个。封装件，其中第一管芯封装件包括：第一管芯，通过金属-金属接合和电介质-电介质接合连接至第二管芯；第一介电材料，位于第一管芯和第二管芯上方，其中，第一介电材料围绕第一管芯；以及第一贯通孔，延伸穿过第一介电材料，其中，第一贯通孔连接至第一管芯。第一管芯封装件还包括延伸穿过第一介电材料的第二贯通孔，其中，第二贯通孔连接至第二管芯。第一管芯封装件还包括延伸穿过第一介电材料的第三贯通孔，其中，第三贯通孔连接至第二管芯。中介层的第一侧上的第一管芯封装件的占用区域包括第一区、第二区和第三区，第一导电连接件和第一伪导电连接件位于第一区中，第二导电连接件位于第二区中，第二高度小于第三高度。第二区围绕第一区。第一区围绕第二区。第二区包括第二伪导电连接件，并且第三区没有伪导电连接件。封装件还包括：第三导电连接件，位于第二区中，第三导电连接件具有的高度大于第二高度；以及第四导电连接件，位于第三区中，第四导电连接件具有的高度大于第三导电连接件的高度。底部填充物将第一伪导电连接件与第一管芯封装件分离。
在一个实施例中，在中介层的第一侧上形成第一再分布结构，第一再分布结构包括位于介电层中的金属线和通孔，第一再分布结构包括位于第一再分布结构的第一表面上的有源焊盘和伪焊盘，有源焊盘电连接至金属线和通孔，伪焊盘与金属线和通孔电隔离。方法还包括在有源焊盘上形成有源连接件。方法还包括在伪焊盘上形成伪连接件。方法还包括将第一集成电路器件附接至有源连接件的第一子集。方法还包括将第二集成电路装置附接至有源连接件的第二子集，伪连接件介于中介层和第二集成电路器件之间。方法还包括在中介层的第一侧上形成底部填充物，底部填充物具有位于第一集成电路器件下方的第一部分和位于第二集成电路器件下方的第二部分。方法还包括用密封剂密封第一集成电路器件和第二集成电路器件。
实施例可以包括以下特征中的一个或多个。方法还包括形成第二集成电路器件，该形成包括：通过金属-金属接合和电介质-电介质接合将第一管芯接合至第二管芯；在第一管芯和第二管芯上方形成第一介电材料，第一介电材料围绕第一管芯；以及形成延伸穿过第一介电材料的第一贯通孔，第一贯通孔连接至第一管芯。第一再分布结构上的第二集成电路器件的占用区域包括第一区、第二区和第三区，第一区和第二区包括伪连接件，第一区、第二区和第三区包括有源连接件，第三区没有伪连接件。第三区中的有源连接件比第一区和第二区中的有源连接件高。第一区中的有源和伪连接件具有第一图案密度，第三区中的有源连接件具有第二图案密度，第二图案密度小于第一图案密度。第二区围绕第一区，并且其中，第二区将第一区与第三区分离。有源连接件的第一子集具有同一高度，并且其中，有源连接件的第二子集具有多个高度。方法还包括形成延伸穿过中介层的衬底的贯通孔，第一再分布结构电耦接至贯通孔。
在实施例中，利用第一组连接件将第一集成电路器件附接至中介层的第一侧，第一组连接件具有同一高度。方法还包括利用第二组连接件将管芯封装件附接至中介层的第一侧，第二组连接件具有多个高度，第一组伪连接件介于中介层和管芯封装件之间，第一组伪连接件与管芯封装件和第一集成电路器件电隔离。方法还包括在第一集成电路器件和管芯封装件下方在中介层的第一侧上形成底部填充物。方法还包括用密封剂密封第一集成电路器件和管芯封装件。
实施例可以包括以下特征中的一个或多个。在方法中，中介层的第一侧上的管芯封装件的占用区域包括第一区、第二区和第三区，第二区围绕第一区，第二区位于第一区和第三区之间，第一区和第二区包括第一组伪连接件，第一区、第二区和第三区包括有源连接件。
以上论述了若干实施例的部件，使得本领域的技术人员可以更好地理解本发明的各个实施例。本领域技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优势。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种封装件，包括：
中介层，具有第一侧；
第一集成电路器件，通过第一组导电连接件附接至所述中介层的第一侧，所述第一组导电连接件中的每个均具有第一高度；
第一管芯封装件，通过第二组导电连接件附接至所述中介层的第一侧，所述第二组导电连接件包括第一导电连接件和第二导电连接件，所述第一导电连接件具有第二高度，所述第二导电连接件具有第三高度，所述第三高度不同于所述第二高度；
第一伪导电连接件，位于所述中介层的第一侧和所述第一管芯封装件之间；
底部填充物，设置在所述第一集成电路器件和所述第一管芯封装件下方；以及
密封剂，设置在所述第一集成电路器件和所述第一管芯封装件周围。
2.根据权利要求1所述的封装件，其中，所述第一管芯封装件包括：
第一管芯，通过金属-金属接合和电介质-电介质接合连接至第二管芯；
第一介电材料，位于所述第一管芯和所述第二管芯上方，其中，所述第一介电材料围绕所述第一管芯；以及
第一贯通孔，延伸穿过所述第一介电材料，其中，所述第一贯通孔连接至所述第一管芯。
3.根据权利要求2所述的封装件，其中，所述第一管芯封装件还包括延伸穿过所述第一介电材料的第二贯通孔，其中，所述第二贯通孔连接至所述第二管芯。
4.根据权利要求2所述的封装件，其中，所述第一管芯封装件还包括延伸穿过所述第一介电材料的第三贯通孔，其中，所述第三贯通孔连接至所述第二管芯。
5.根据权利要求1所述的封装件，其中，所述中介层的第一侧上的第一管芯封装件的占用区域包括第一区、第二区和第三区，所述第一导电连接件和所述第一伪导电连接件位于所述第一区中，所述第二导电连接件位于所述第二区中，所述第二高度小于所述第三高度。
6.根据权利要求5所述的封装件，其中，所述第二区围绕所述第一区。
7.根据权利要求5所述的封装件，其中，所述第一区围绕所述第二区。
8.根据权利要求5所述的封装件，其中，所述第二区包括第二伪导电连接件，并且所述第三区没有伪导电连接件。
9.一种制造封装件的方法，包括：
在中介层的第一侧上形成第一再分布结构，所述第一再分布结构包括位于介电层中的金属线和通孔，所述第一再分布结构包括位于所述第一再分布结构的第一表面上的有源焊盘和伪焊盘，所述有源焊盘电耦接至所述金属线和通孔，所述伪焊盘与所述金属线与通孔电隔离；
在所述有源焊盘上形成有源连接件；
在所述伪焊盘上形成伪连接件；
将第一集成电路器件附接至所述有源连接件的第一子集；
将第二集成电路器件附接至所述有源连接件的第二子集，所述伪连接件位于所述中介层和所述第二集成电路器件之间；
在所述中介层的第一侧上形成底部填充物，所述底部填充物具有位于所述第一集成电路器件下方的第一部分和位于所述第二集成电路器件下方的第二部分；以及
用密封剂密封所述第一集成电路器件和所述第二集成电路器件。
10.一种制造封装件的方法，包括：
通过第一组连接件将第一集成电路器件附接至中介层的第一侧，所述第一组连接件具有同一高度；
通过第二组连接件将管芯封装件附接至所述中介层的第一侧，所述第二组连接件具有多个高度，第一组伪连接件位于所述中介层和所述管芯封装件之间，所述第一组伪连接件与所述管芯封装件和所述第一集成电路器件电隔离；
在所述第一集成电路器件和所述管芯封装件下方，在所述中介层的第一侧上形成底部填充物；以及
用密封剂密封所述第一集成电路器件和所述管芯封装件。
CN202110936175.3A 2020-08-17 2021-08-16 封装件及制造方法 Pending CN113990855A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202063066366P 2020-08-17 2020-08-17
US63/066,366 2020-08-17
US17/226,643 2021-04-09
US17/226,643 US11990443B2 (en) 2020-08-17 2021-04-09 Semiconductor die package and method of manufacture

Publications (1)

Publication Number Publication Date
CN113990855A true CN113990855A (zh) 2022-01-28

Family

ID=79735177

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110936175.3A Pending CN113990855A (zh) 2020-08-17 2021-08-16 封装件及制造方法

Country Status (5)

Country Link
US (2) US11990443B2 (zh)
KR (1) KR102611254B1 (zh)
CN (1) CN113990855A (zh)
DE (1) DE102021109273A1 (zh)
TW (1) TWI773354B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220352109A1 (en) * 2021-04-28 2022-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and manufacturing method thereof
US20230011353A1 (en) * 2021-07-08 2023-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package structure and method for forming the same
US12062585B2 (en) * 2021-10-18 2024-08-13 Artilux, Inc. Wafer-level device measurement for optical sensors

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101131138B1 (ko) 2006-01-04 2012-04-03 삼성전자주식회사 다양한 크기의 볼 패드를 갖는 배선기판과, 그를 갖는반도체 패키지 및 그를 이용한 적층 패키지
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9343419B2 (en) 2012-12-14 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
CN204927277U (zh) * 2015-09-10 2015-12-30 江阴长电先进封装有限公司 一种硅基模块的封装结构
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10510634B2 (en) * 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method
US10510650B2 (en) * 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
US10790254B2 (en) 2018-05-09 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure
US11075133B2 (en) 2018-06-29 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill structure for semiconductor packages and methods of forming the same
KR20200046282A (ko) 2018-10-24 2020-05-07 삼성전자주식회사 집적 회로 장치 및 고 대역폭 메모리 장치
KR102577265B1 (ko) 2018-12-06 2023-09-11 삼성전자주식회사 반도체 패키지
US10847485B2 (en) 2018-12-21 2020-11-24 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10840190B1 (en) * 2019-05-16 2020-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof

Also Published As

Publication number Publication date
KR102611254B1 (ko) 2023-12-06
DE102021109273A1 (de) 2022-02-17
US11990443B2 (en) 2024-05-21
US20230387058A1 (en) 2023-11-30
TW202209589A (zh) 2022-03-01
US20220052009A1 (en) 2022-02-17
TWI773354B (zh) 2022-08-01
KR20220022090A (ko) 2022-02-24

Similar Documents

Publication Publication Date Title
US10957616B2 (en) Package structure and method
CN110970407B (zh) 集成电路封装件和方法
KR102114454B1 (ko) 반도체 디바이스 패키지 및 방법
CN109427702B (zh) 散热器件和方法
TWI783269B (zh) 封裝、半導體封裝及其形成方法
CN110610907B (zh) 半导体结构和形成半导体结构的方法
US11264362B2 (en) Semiconductor structure and method of fabricating the same
US11164824B2 (en) Package structure and method of fabricating the same
US11990443B2 (en) Semiconductor die package and method of manufacture
US20220301890A1 (en) Integrated Circuit Package and Method of Forming Thereof
US20240266297A1 (en) Package-On-Package Device
US20220262783A1 (en) Integrated Circuit Package and Method
KR102698672B1 (ko) 집적회로 패키지 및 그 형성 방법
CN221747211U (zh) 集成电路封装
US20230420330A1 (en) Semiconductor Packages and Methods of Forming the Same
US20230352367A1 (en) Semiconductor package and method
CN118116882A (zh) 集成电路封装件及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination