TW202046464A - 積體電路封裝及其形成方法 - Google Patents

積體電路封裝及其形成方法 Download PDF

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TW202046464A
TW202046464A TW108145496A TW108145496A TW202046464A TW 202046464 A TW202046464 A TW 202046464A TW 108145496 A TW108145496 A TW 108145496A TW 108145496 A TW108145496 A TW 108145496A TW 202046464 A TW202046464 A TW 202046464A
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Taiwan
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die
dielectric layer
layer
semiconductor substrate
bonding
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TW108145496A
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English (en)
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許家豪
林詠淇
邱文智
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台灣積體電路製造股份有限公司
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Publication of TW202046464A publication Critical patent/TW202046464A/zh

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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
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Abstract

本發明實施例提供積體電路封裝以及形成所述積體電路封裝的方法。一種積體電路封裝包括至少一個第一晶粒、多個凸塊、第二晶粒以及介電層。所述凸塊在所述至少一個第一晶粒的第一側電連接到所述至少一個第一晶粒。所述第二晶粒在所述至少一個第一晶粒的第二側電連接到所述至少一個第一晶粒。所述至少一個第一晶粒的所述第二側與所述第一側相對。所述介電層設置在所述至少一個第一晶粒與所述第二晶粒之間且覆蓋所述至少一個第一晶粒的側壁。

Description

積體電路封裝及其形成方法
本發明實施例是關於積體電路封裝及其形成方法。
近年來，由於各種電子組件（例如，電晶體、二極體、電阻器、電容器等）的集成密度持續提高，半導體行業已經歷快速成長。在很大程度上，集成密度的這種提高來自於最小特徵大小（minimum feature size）的連續減小，這使得更多組件能夠集成到給定區域中。
這些較小的電子組件也需要與先前的封裝相比佔據較小面積的較小的封裝。半導體封裝的類型的實例包括方形扁平封裝（quad flat pack，QFP）、引腳柵陣列（pin grid array，PGA）、球柵陣列（ball grid array，BGA）、倒裝晶片（flip chip，FC）、三維積體電路（three dimensional integrated circuit，3DIC）封裝、晶片級封裝（wafer level package，WLP）及疊層封裝（package on package，PoP）元件。一些3DIC是通過在半導體晶片級的晶粒之上放置晶粒製備而成。3DIC提供提高的集成密度及其他優點（例如，較快的速度及較高的頻寬），這是由於堆疊晶片之間的內連線的長度減小。然而，存在許多與3DIC有關的挑戰。
根據本公開的一些實施例，一種積體電路封裝包括至少一個第一晶粒、多個凸塊、第二晶粒以及介電層。所述凸塊在所述至少一個第一晶粒的第一側電連接到所述至少一個第一晶粒。所述第二晶粒在所述至少一個第一晶粒的第二側電連接到所述至少一個第一晶粒。所述至少一個第一晶粒的所述第二側與所述第一側相對。所述介電層設置在所述至少一個第一晶粒與所述第二晶粒之間且覆蓋所述至少一個第一晶粒的側壁。
根據本公開的替代實施例，一種積體電路封裝包括至少一個第一晶粒、積體電路結構、介電層以及多個凸塊。所述至少一個第一晶粒在所述至少一個第一晶粒的第一側結合到所述積體電路結構。所述介電層覆蓋所述至少一個第一晶粒的頂部及側壁。所述凸塊在所述至少一個第一晶粒的第二側電連接到所述至少一個第一晶粒。所述至少一個第一晶粒的所述第二側與所述第一側相對。
根據本公開的又一些替代實施例，一種形成積體電路封裝的方法包括以下操作。將至少一個第一晶粒在所述至少一個第一晶粒的第一側結合到第一載體，且所述第一晶粒包括第一半導體基底、穿透過所述第一半導體基底的多個第一基底穿孔以及位於所述第一半導體基底之上的第一內連結構。局部地移除所述第一半導體基底，以暴露出所述第一基底穿孔的一些部分。形成介電層，所述介電層位在所述至少一個第一晶粒的頂部及側壁之上以及圍繞所述第一基底穿孔的被暴露出的所述部分。將第二晶粒在所述至少一個第一晶粒的第二側結合到所述至少一個第一晶粒。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述組件及排列的具體實例是為了以簡化方式傳達本公開。當然，這些僅為實例而非旨在進行限制。舉例來說，在以下說明中，在第一特徵之上或第一特徵上形成第二特徵可包括其中第二特徵與第一特徵被形成為直接接觸的實施例，且也可包括其中第二特徵與第一特徵之間可形成附加特徵從而使得第二特徵與第一特徵可不直接接觸的實施例。另外，在本公開的各種實例中可使用相同的參考編號和/或字母來指代相同或相似的部件。參考編號的這種重複使用是為了簡明及清晰起見，且自身並不表示所論述的各個實施例和/或配置之間的關係。
此外，本文中可能使用例如“在…之下”、“在…下方”、“下部的”、“在…上”、“在…之上”、“上覆在…上”、“在…上方”、“上部的”等空間相對性用語來便於闡述圖中所示一個構件或特徵與另一（其他）構件或特徵的關係。除圖中所繪示的取向以外，所述空間相對性用語更旨在囊括元件在使用或操作中的不同取向。裝置可具有另外的取向（旋轉90度或處於其他取向），且本文所使用的空間相對性描述語可同樣相應地作出解釋。
圖1A到圖1G是根據一些實施例的形成積體電路封裝的方法的剖視圖。應理解，本公開不受以下所述方法限制。對於所述方法的附加實施例來說，可在所述方法之前、期間和/或之後提供附加操作，且可替換或消除以下所述操作中的一些操作。
儘管圖1A到圖1G是相對於方法闡述的，然而應理解，圖1A到圖1G中所公開的結構並非僅限於這種方法，而是可單獨作為獨立於所述方法的結構。
參照圖1A，提供第一晶粒100。第一晶粒100可包括一個或多個主動組件和/或被動組件。在一些實施例中，第一晶粒100可包括邏輯晶粒、記憶體晶粒、中央處理器（central processing unit，CPU）、圖形處理單元（Graphic processing unit，GPU）、xPU、微機電系統（Micro-electromechanical system，MEMS）晶粒、系統晶片（System on Chip，SoC）晶粒等。在一些實施例中，第一晶粒100包括半導體基底S1、多個基底穿孔TSV1以及內連結構IS1。
半導體基底S1包含元素半導體（例如矽、鍺）和/或化合物半導體（例如矽鍺、碳化矽、砷化鎵、砷化銦、氮化鎵或磷化銦）。半導體基底S1可包括含矽材料。舉例來說，半導體基底S1是絕緣體上矽（silicon-on-insulator，SOI）基底或矽基底。在各種實施例中，半導體基底S1可採用以下形式：平面基底、具有多個鰭的基底、奈米線或所屬領域的普通技術人員已知的其他形式。根據設計要求，半導體基底S1可為P型基底或N型基底，且其中可具有摻雜區。摻雜區可被配置成用於N型元件或P型元件。半導體基底S1包括界定至少一個主動區域的隔離結構，且在主動區域上和/或主動區域中設置有至少一個元件。在一些實施例中，元件包括閘極介電層、閘電極、源極/汲極區、間隔件等。
基底穿孔（例如，矽穿孔）TSV1穿透過半導體基底S1。基底穿孔TSV1可包含Cu、Ti、Ta、W、Ru、Co、Ni等或其組合。在一些實施例中，在每一基底穿孔TSV1與半導體基底S1之間可設置有晶種層和/或阻擋層。晶種層可包含Ti/Cu。阻擋層可包含Ta、TaN、Ti、TiN、CoW或其組合。在一些實施例中，基底穿孔TSV1的頂部部分延伸到內連結構IS1中。
內連結構IS1可設置在半導體基底S1的第一側（例如，前側）之上。具體來說，內連結構IS1可設置在元件之上並電連接到元件。在一些實施例中，內連結構IS1包括金屬間介電層IMD1及嵌入在金屬間介電層IMD1中的金屬特徵。金屬間介電層IMD1可包含氧化矽、氮化矽、氮氧化矽、介電常數小於3.5的低介電常數（低k）材料等或其組合。金屬特徵可包含Al、Cu、Ti、Ta、W、Ru、Co、Ni等或其組合。在一些實施例中，在每一金屬特徵與對應的金屬間介電層IMD1之間可設置有晶種層和/或阻擋層。晶種層可包含Ti/Cu。阻擋層可包含Ta、TaN、Ti、TiN、CoW或其組合。在一些實施例中，金屬特徵包括上部襯墊UP1及下部襯墊LP1，上部襯墊UP1被配置成將第一晶粒100結合到期望組件（例如凸塊），下部襯墊LP1被配置成供基底穿孔TSV1著陸在其上。在一些實施例中，上部襯墊UP1及下部襯墊LP1包含不同的材料。舉例來說，上部襯墊UP1可包含Al，且下部襯墊LP1可包含Cu。在替代實施例中，上部襯墊UP1與下部襯墊LP1可包含相同的材料。
在第一晶粒100中視需要包括結合膜BF1。結合膜BF1可設置在半導體基底S1的第一側（例如，前側）之上。具體來說，結合膜BF1可設置在內連結構IS1之上。在一些實施例中，結合膜BF1包含氧化矽、氮化矽等或其組合。在另一實施例中，利用聚合物（例如苯並環丁烯（benzocyclobutene，BCB）、環氧樹脂、有機膠等）作為結合膜BF1的結合材料。
仍然參照圖1A，提供載體C1。載體C1上形成有結合膜BFC1 。在一些實施例中，載體C1是玻璃基底或半導體基底，且結合膜BFC1 包含氧化矽、氮化矽等或其組合。在另一實施例中，利用聚合物（例如苯並環丁烯（BCB）、環氧樹脂、有機膠等）作為結合膜BFC1 的結合材料。在一些實施例中，載體C1的結合膜BFC1 包含與第一晶粒100的結合膜BF1的材料相同的材料。在替代實施例中，載體C1的結合膜BFC1 與第一晶粒100的結合膜BF1可包含不同的材料。
再次參照圖1A，將第一晶粒100在第一晶粒100的第一側（例如，前側）結合到載體C1。在一些實例中，第一晶粒100可被稱為第一層晶粒（tier-1 die）。在一些實施例中，通過熔融結合將第一晶粒100結合到載體C1。具體來說，將第一晶粒100的結合膜BF1結合到載體C1的結合膜BFC1 。然而，本公開並非僅限於此，且可應用另一種結合技術，例如直接結合、金屬擴散、陽極結合、包括金屬到金屬結合及介電質到介電質結合的混合結合等。
參照圖1B，局部地移除半導體基底S1以暴露出基底穿孔TSV1的一些部分（例如，底部部分）。在一些實施例中，局部移除操作包括執行等向性蝕刻，例如乾式蝕刻。在一些實施例中，蝕刻氣體包括含氟氣體，例如NF3 、SF6 、CF4 、CHF3 、CH2 F2 等或其組合。
在一些實施例中，在局部地移除半導體基底S1之後，內連結構IS1寬於剩餘的半導體基底S1。具體來說，局部移除操作不僅移除半導體基底S1的底部部分以暴露出基底穿孔TSV1的底部部分，而且更移除半導體基底S1的側部分以暴露出內連結構IS1的金屬間介電層IMD1的一部分。在一些實施例中，在局部地移除半導體基底S1的操作期間，局部地移除載體C1的結合膜BFC1 。因此，剩餘的結合膜BFC1 在中心區較厚而在邊緣區較薄。
參照圖1C，形成介電層DL，所述介電層DL位在第一晶粒100的頂部及側壁之上並圍繞基底穿孔TSV1的被暴露出的部分（例如，底部部分）。在一些實施例中，介電層DL更遠離第一晶粒100沿橫向延伸並覆蓋載體C1的結合膜BFC1 的被暴露出的頂表面。
本公開的介電層DL不僅用作用於將第一晶粒100結合到期望組件（例如第二晶粒）的結合膜，而且還用作用於將第一晶粒100與不期望的組件或材料隔離的隔離膜。在一些實施例中，介電層DL可包含氧化矽、氮化矽、氮氧化矽、介電常數小於3.5的低介電常數材料（例如，碳摻雜氧化物）等或其組合。形成介電層DL的方法包括以下操作。通過合適的製程（例如化學氣相沉積（chemical vapor deposition，CVD）或電漿增強CVD（plasma enhanced CVD，PECVD））在載體C1之上形成覆蓋第一晶粒100的介電材料層，但是也可利用任何合適的製程。此後，執行平坦化製程（例如化學機械研磨（chemical mechanical polishing，CMP））以局部地移除介電材料層，直到暴露出基底穿孔TSV1的表面（例如，底表面）。
參照圖1D，提供第二晶粒200。第二晶粒200可包括一個或多個主動組件和/或被動組件。在一些實施例中，第二晶粒200可包括邏輯晶粒、記憶體晶粒、CPU、GPU、xPU、MEMS晶粒、SoC晶粒等。第二晶粒200的功能可不同於第一晶粒100的功能。舉例來說，第一晶粒及第二晶粒中的一者是邏輯晶粒，且第一晶粒及第二晶粒中的另一者是記憶體晶粒。第一晶粒與第二晶粒可視需要具有相似的功能。
第二晶粒200的結構可相似於第一晶粒100的結構，且第二晶粒200的材料及配置可參照第一晶粒100的材料及配置。在一些實施例中，第二晶粒200包括半導體基底S2及內連結構IS2。
半導體基底S2可相似於半導體基底S1，因此半導體基底S2的材料及配置可參照半導體基底S1的材料及配置。在一些實施例中，半導體基底S2可視需要具有基底穿孔，例如矽穿孔。在一些實施例中，半導體基底S2包括界定至少一個主動區域的隔離結構，且在主動區域上和/或主動區域中設置有至少一個元件。在一些實施例中，半導體基底S2的寬度大於半導體基底S1的寬度，如圖1D所示。然而，本公開並非僅限於此。在替代實施例中，半導體基底S2實質上與半導體基底S1一樣寬。在又一些替代實施例中，半導體基底S2的寬度可視需要小於半導體基底S1的寬度。
內連結構IS2可相似於內連結構IS1，因此內連結構IS2的材料及配置可參照內連結構IS1的材料及配置。在一些實施例中，內連結構IS2可設置在半導體基底S2的第一側（例如，前側）之上。具體來說，內連結構IS2設置在元件之上並電連接到元件。在一些實施例中，內連結構IS2包括金屬間介電層IMD2及嵌入在金屬間介電層IMD2中的金屬特徵。在一些實施例中，金屬特徵包括襯墊P2，襯墊P2被配置成將第二晶粒200結合到第一晶粒100的基底穿孔TSV1。在一些實施例中，內連結構IS2實質上與內連結構IS1一樣寬，如圖1D所示。然而，本公開並非僅限於此。在替代實施例中，內連結構IS2與內連結構IS1可具有不同的寬度。
仍然參照圖1D，將第二晶粒200在第一晶粒100的第二側（例如，背側）結合到第一晶粒100。在一些實例中，第二晶粒200可被稱為第二層晶粒。在一些實施例中，通過包括金屬到金屬結合及介電質到介電質結合的混合結合將第二晶粒200結合到第一晶粒100。具體來說，將第二晶粒200的襯墊P2結合到第一晶粒100的基底穿孔TSV1，且將金屬間介電層IMD2結合到第一晶粒100之上的介電層DL。然而，本公開並非僅限於此，且可應用另一種結合技術，例如直接結合、金屬擴散、陽極結合、熔融結合等。
在一些實施例中，第二晶粒200與第一晶粒100以面對背配置堆疊，如圖1D所示。然而，本公開並非僅限於此，且可應用另一種背對背配置。
參照圖1E，形成介電包封體E，所述介電包封體E圍繞第一晶粒100及第二晶粒200。在一些實例中，介電包封體E可被稱為間隙填充層。在一些實施例中，介電包封體E包含模塑化合物、模塑底部填料、樹脂等。在一些實施例中，介電包封體E包含聚合物材料，例如聚苯並惡唑（PBO）、聚醯亞胺、苯並環丁烯（BCB）等或其組合。在替代實施例中，介電包封體E包含氧化矽、氮化矽或其組合。在一些實施例中，形成介電包封體E的方法包括以下操作。通過合適的製程（例如模塑製程或沉積製程）在載體C1之上形成覆蓋第一晶粒100及第二晶粒200的包封材料層，但是也可利用任何合適的製程。此後，執行平坦化製程（例如化學機械研磨（CMP））以局部地移除包封材料層，直到暴露出半導體基底S2的表面（例如，底表面）。
參照圖1F，在第二晶粒200及介電包封體E之上形成結合膜BF2。在一些實施例中，結合膜BF2包含氧化矽、氮化矽等或其組合。在另一實施例中，利用聚合物（例如苯並環丁烯（BCB）、環氧樹脂、有機膠等）作為結合膜BF2的結合材料。
參照圖1G，提供第二載體C2。載體C2上形成有結合膜BFC2 。在一些實施例中，載體C2是玻璃基底或半導體基底，且結合膜BFC2 包含氧化矽、氮化矽等或其組合。在一些實例中，載體C2可被稱為蓋體構件。在另一實施例中，利用聚合物（例如苯並環丁烯（BCB）、環氧樹脂、有機膠等）作為結合膜BFC2 的結合材料。在一些實施例中，載體C2的結合膜BFC2 包含的材料與位於第二晶粒200之上的結合膜BF2的材料相同。在替代實施例中，載體C2的結合膜BFC2 與位於第二晶粒200之上的結合膜BF2可包含不同的材料。
仍然參照圖1G，將第二載體C2結合到第二晶粒200。在一些實施例中，通過熔融結合將載體C2結合到第二晶粒200。具體來說，將載體C2的結合膜BFC2 結合到第二晶粒200的結合膜BF2。然而，本公開並非僅限於此，且可應用另一種結合技術，例如直接結合、金屬擴散、陽極結合、包括金屬到金屬結合及介電質到介電質結合的混合結合等。
再次參照圖1G，移除載體C1。在一些實施例中，在移除載體C1的操作期間，同時移除第一晶粒100的結合膜BF1及載體C1的結合膜BFC1 。
此後，在第一晶粒100的第一側（例如，前側）之上形成絕緣層IL。在一些實施例中，絕緣層IL可包含氧化矽或合適的介電材料且可通過合適的沉積製程形成。
然後，在第一晶粒100的第一側（例如，前側）形成多個凸塊B。凸塊B設置在內連結構IS1的上部襯墊UP1之上且電連接到內連結構IS1的上部襯墊UP1。在一些實施例中，凸塊B包含銅、焊料、鎳或其組合。在一些實施例中，凸塊B可為焊料球、受控塌陷晶粒連接（controlled collapse chip connection，C4）凸塊、球柵陣列（BGA）球、微凸塊、化學鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊、銅支柱、混合結合凸塊等。本公開的積體電路封裝10由此完成。
提供其仲介電層DL是單層的上述實施例是出於說明目的，且上述實施例不應被視為限制本公開。具體來說，本公開的介電層DL可視需要形成為具有多層式結構。在一些實施例中，當圖1C所示介電層DL被形成為具有包括下部介電層LDL及上部介電層UDL的多層式結構時，形成本公開的積體電路封裝10a，如圖2所示。下部介電層LDL與上部介電層UDL可包含不同的材料並提供不同的功能。舉例來說，下部介電層LDL用作用於改善上部介電層UDL與銅或矽之間的黏合的黏合膜，且上部介電層UDL用作用於將第一晶粒100結合到第二晶粒200的結合膜。在一些實施例中，下部介電層LDL及上部介電層UDL中的每一者可包含氧化矽、氮化矽、氮氧化矽、介電常數小於3.5的低介電常數材料（例如，碳摻雜氧化物）等或其組合。
提供其中積體電路封裝具有結合到第二晶粒的第一晶粒的上述實施例是出於說明目的，且上述實施例不應被視為限制本公開。在一些實施例中，可提供包括多個第一晶粒的晶粒堆疊，且接著將晶粒堆疊結合到第二晶粒。在替代實施例中，可視需要調整第二晶粒的數目。
圖3A到圖3F是根據一些實施例的形成積體電路封裝的方法的剖視圖。應理解，本公開不受以下所述方法限制。對於所述方法的附加實施例來說，可在所述方法之前、期間和/或之後提供附加操作，且可替換或消除以下所述操作中的一些操作。
儘管圖3A到圖3F是相對於方法闡述的，然而應理解，圖3A到圖3F中所公開的結構並非僅限於這種方法，而是可單獨作為獨立於所述方法的結構。
參照圖3A，將第一層第一晶粒100在第一層第一晶粒100的第一側（例如，前側）結合到載體C1。圖3A所示操作相似於圖1A所示操作，且在本文中不再對其予以贅述。
參照圖3B，局部地移除第一層第一晶粒100的半導體基底S1以暴露出基底穿孔TSV1的一些部分，且形成介電層DL1，所述介電層DL1位在第一層第一晶粒100的頂部及側壁之上並圍繞基底穿孔TSV1的被暴露出的部分。圖3B所示操作包括與圖1B及圖1C所述操作相似的操作，且在本文中不再對其予以贅述。在一些實施例中，介電層DL更遠離第一層第一晶粒100沿橫向延伸並覆蓋載體C1的結合膜BFC1 的被暴露出的頂表面。在一些實施例中，介電層DL1可包含氧化矽、氮化矽、氮氧化矽、介電常數小於3.5的低介電常數材料（例如，碳摻雜氧化物）等或其組合。
參照圖3C，將第二層第一晶粒100在第一層第一晶粒100的第二側（例如，背側）結合到第一層第一晶粒100。在一些實施例中，通過包括金屬到金屬結合及介電質到介電質結合的混合結合將第二層第一晶粒100結合到第一層第一晶粒100。具體來說，將第二層第一晶粒100的上部襯墊UP1結合到第一層第一晶粒100的基底穿孔TSV1，且將第二層第一晶粒100的金屬間介電層IMD1結合到第一層第一晶粒100之上的介電層DL1。然而，本公開並非僅限於此，且可應用另一種結合技術，例如直接結合、金屬擴散、陽極結合、熔融結合等。
在一些實施例中，第二層第一晶粒100與第一層第一晶粒100以面對背配置堆疊，如圖3C所示。然而，本公開並非僅限於此，且可應用另一種背對背配置。
在一些實施例中，第二層第一晶粒100的內連結構IS1的上部襯墊UP1與下部襯墊LP1可包含相同的材料（例如Cu）；然而，第一層第一晶粒100的內連結構IS1的上部襯墊UP1與下部襯墊LP1可分別包含不同的材料（例如Al及Cu）。
此後，局部地移除第二層第一晶粒100的半導體基底S1以暴露出基底穿孔TSV1的一些部分，且形成介電層DL2，所述介電層DL2位在第二層第一晶粒的頂部及側壁之上並圍繞基底穿孔TSV1的被暴露出的部分。在一些實施例中，介電層DL2更覆蓋第一層第一晶粒100的側壁上的介電層DL1，且遠離第一晶粒100沿橫向延伸。在一些實施例中，介電層DL2可包含氧化矽、氮化矽、氮氧化矽、介電常數小於3.5的低介電常數材料（例如，碳摻雜氧化物）等或其組合。在一些實施例中，介電層DL2與介電層DL1包含相同的材料並且通過相同的製程形成，但本公開並非僅限於此。在替代實施例中，介電層DL2與介電層DL1可視需要包含不同的材料。
參照圖3D，通過包括金屬到金屬結合及介電質到介電質結合的混合結合將第三層第一晶粒100結合到第二層第一晶粒100。此後，局部地移除第三層第一晶粒100的半導體基底S1以暴露出基底穿孔TSV1的一些部分，且形成介電層DL3，所述介電層DL3位在第三層第一晶粒100的頂部及側壁之上並圍繞基底穿孔TSV1的被暴露出的部分。圖3D所示操作包括與圖3B及圖3C所述操作相似的操作。在一些實施例中，介電層DL3更覆蓋第一層第一晶粒100及第二層第一晶粒100的側壁上的介電層DL2，且遠離第一晶粒100沿橫向延伸。在一些實施例中，介電層DL3可包含氧化矽、氮化矽、氮氧化矽、介電常數小於3.5的低介電常數材料（例如，碳摻雜氧化物）等或其組合。在一些實施例中，介電層DL3與介電層DL2包含相同的材料並且通過相同的製程形成，但本公開並非僅限於此。在替代實施例中，介電層DL3與介電層DL2可視需要包含不同的材料。
參照圖3E，通過包括金屬到金屬結合及介電質到介電質結合的混合結合將第四層第一晶粒100結合到第三層第一晶粒100。此後，局部地移除第四層第一晶粒100的半導體基底S1以暴露出基底穿孔TSV1的一些部分，且形成介電層DL4，所述介電層DL4位在第四層第一晶粒100的頂部及側壁之上並圍繞基底穿孔TSV1的被暴露出的部分。圖3E所示操作包括與圖3B及圖3C所述操作相似的操作。在一些實施例中，介電層DL4更覆蓋第一層第一晶粒100、第二層第一晶粒100及第三層第一晶粒100的側壁上的介電層DL3，且遠離第一晶粒100沿橫向延伸。在一些實施例中，介電層DL4可包含氧化矽、氮化矽、氮氧化矽、介電常數小於3.5的低介電常數材料（例如，碳摻雜氧化物）等或其組合。在一些實施例中，介電層DL4與介電層DL3包含相同的材料並且通過相同的製程形成，但本公開並非僅限於此。在替代實施例中，介電層DL4與介電層DL3可視需要包含不同的材料。在一些實施例中，介電層DL1到DL4構成介電層DL。本公開的介電層DL不僅用作用於將第一晶粒100結合到期望組件（例如另一晶粒或重佈線層結構）的結合膜，而且還用作用於將第一晶粒100與不期望的組件或材料隔離的隔離膜。
有鑒於前述內容，將圖3B及圖3C所述操作執行三次，且因此形成包括第一層第一晶粒100到第四層第一晶粒100的晶粒堆疊。可視需要將圖3B及圖3C所述操作重複許多次，直到垂直地堆疊期望數目的第一晶粒100。
參照圖3F，將第二晶粒200在最頂部第一晶粒100的第二側（例如，背側）結合到晶粒堆疊的最頂部的第一晶粒100（例如，第四層第一晶粒100）。此後，形成介電包封體E，所述介電包封體E圍繞第一層第一晶粒100到第四層第一晶粒100。然後，在第二晶粒200及介電包封體E之上形成結合膜BF2。接著將第二載體C2結合到第二晶粒200。移除載體C1。在一些實施例中，在移除載體C1期間，同時移除介電層DL的一部分（例如，介電層DL1的位於載體C1上的部分）。接下來，在最底部第一晶粒100（例如，第一層第一晶粒100）的第一側（例如，前側）之上形成絕緣層IL。然後，在最底部第一晶粒100（例如，第一層第一晶粒100）的第一側（例如，前側）形成多個凸塊B。圖3F所示操作包括與圖1D到圖1G所述操作相似的操作，且在本文中不再對其予以贅述。本公開的積體電路封裝10b由此完成。
以下參照圖1G、圖2及圖3F說明本公開的結構。
在一些實施例中，積體電路封裝10/10a/10b包括至少一個第一晶粒100、多個凸塊B、第二晶粒200及介電層DL。凸塊B在所述至少一個第一晶粒100的第一側（例如，前側）電連接到所述至少一個第一晶粒100。第二晶粒200在所述至少一個第一晶粒100的第二側（例如，背側）電連接到所述至少一個第一晶粒100。在一些實施例中，（最頂部）第一晶粒100與第二晶粒200通過包括金屬到金屬結合及介電質到介電質結合的混合結合而結合在一起。所述至少一個第一晶粒100的第二側與第一側相對。
在一些實施例中，第一晶粒100包括半導體基底S1及內連結構IS1，且內連結構IS1寬於半導體基底S1。在一些實施例中，第二晶粒200包括半導體基底S2及內連結構IS2，且內連結構IS2實質上與半導體基底S2一樣寬。在一些實施例中，半導體基底S2寬於半導體基底S1。在替代實施例中，半導體基底S2的寬度可視需要等於或小於半導體基底S1的寬度。
本公開的介電層DL設置在所述至少一個第一晶粒100與第二晶粒200之間，且覆蓋所述至少一個第一晶粒100的側壁。在一些實施例中，介電層DL環繞所述至少一個第一晶粒100的基底穿孔TSV1的一些部分。在一些實施例中，介電層DL的表面與基底穿孔TSV1的表面實質上共面。
在一些實施例中，如圖1G所示，介電層DL是單層。在一些實施例中，如圖2及圖3F所示，介電層DL具有多層式結構。
在一些實施例中，介電層DL具有階梯式側壁，所述階梯式側壁具有多個轉捩點。在一些實施例中，介電層DL具有一個階梯的輪廓，如圖1G及圖2所示。在一些實施例中，介電層DL具有多階梯輪廓，如圖3F所示。在一些實施例中，介電層DL更遠離第一晶粒100沿橫向延伸，如圖3F所示。
在一些實施例中，如圖3F所示，所述至少一個第一晶粒100包括垂直地堆疊的多個第一晶粒100。在一些實施例中，兩個相鄰的第一晶粒100通過包括金屬到金屬結合及介電質到介電質結合的混合結合而結合在一起。在一些實施例中，位於遠離第二晶粒200的第一晶粒100（例如，第一層第一晶粒100）的側壁上的介電層DL厚於位於靠近第二晶粒200的第一晶粒（例如，第四層第一晶粒100）的側壁上的介電層DL。在一些實施例中，介電層DL更設置在兩個相鄰的第一晶粒100之間。
在一些實施例中，積體電路封裝10/10a/10b更包括介電包封體E以及載體C2，介電包封體E圍繞所述至少一個第一晶粒100及第二晶粒200設置，載體C2設置在第二晶粒200之上且結合到第二晶粒200。在一些實施例中，介電包封體E通過介電層DL與所述至少一個第一晶粒100隔開。
有鑒於上述，本公開的介電層設置在所述相鄰的晶粒之間且覆蓋晶粒的整個側壁。在一些實施例中，對應的晶粒之上的每一介電層的橫向部分用作用於將晶粒結合到期望組件的結合膜，且所述介電層的階梯式側壁部分用作用於將晶粒與不期望的組件或材料隔離的隔離膜。此外，本公開的方法簡單並且與現有製程相容。
圖4A到圖4D是根據替代實施例的形成積體電路封裝的方法的剖視圖。應理解，本公開不受以下所述方法限制。對於所述方法的附加實施例來說，可在所述方法之前、期間和/或之後提供附加操作，且可替換或消除以下所述操作中的一些操作。
儘管圖4A到圖4D是相對於方法闡述的，然而應理解，圖4A到圖4D中所公開的結構並非僅限於這種方法，而是可單獨作為獨立於所述方法的結構。
參照圖4A，提供第一晶粒101。第一晶粒101可包括一個或多個主動組件和/或被動組件。在一些實施例中，第一晶粒101可包括邏輯晶粒、記憶體晶粒、CPU、GPU、xPU、MEMS晶粒、SoC晶粒等。第一晶粒101可相似於第一晶粒100，且第一晶粒101的材料及配置可參照第一晶粒100的材料及配置。在一些實施例中，第一晶粒101包括半導體基底S、多個基底穿孔TSV以及內連結構IS。
半導體基底S可相似於半導體基底S1，因此半導體基底S的材料及配置可參照半導體基底S1的材料及配置。在一些實施例中，半導體基底S包括界定至少一個主動區域的隔離結構，且在主動區域上和/或主動區域中設置有至少一個元件。
基底穿孔TSV可相似於基底穿孔TSV1，因此基底穿孔TSV的材料及配置可參照基底穿孔TSV1的材料及配置。基底穿孔（例如，矽穿孔）TSV穿透過半導體基底S。在一些實施例中，基底穿孔TSV的頂部部分延伸到內連結構IS中。
內連結構IS可相似於內連結構IS1，因此內連結構IS的材料及配置可參照內連結構IS1的材料及配置。在一些實施例中，內連結構IS可設置在半導體基底S的第一側（例如，前側）之上。具體來說，內連結構IS可設置在元件之上並電連接到元件。在一些實施例中，內連結構IS包括金屬間介電層IMD及嵌入在金屬間介電層IMD中的金屬特徵。在一些實施例中，金屬特徵包括上部襯墊UP及下部襯墊LP，上部襯墊UP被配置成將第一晶粒101結合到期望組件（例如積體電路結構），下部襯墊LP被配置成供基底穿孔TSV著陸在其上。在一些實施例中，上部襯墊UP及下部襯墊LP包含相同的材料。舉例來說，上部襯墊UP及下部襯墊LP可包含Cu。在替代實施例中，上部襯墊UP與下部襯墊LP可包含不同的材料。
仍然參照圖4A，提供積體電路結構IC。積體電路結構IC可包括一個或多個功能元件，例如主動組件和/或被動組件。在一些實施例中，積體電路結構IC可包括邏輯晶粒、記憶體晶粒、CPU、GPU、xPU、MEMS晶粒、SoC晶粒等。積體電路結構IC的功能可不同於第一晶粒101的功能。舉例來說，第一晶粒101及積體電路結構IC中的一者是邏輯晶粒，且第一晶粒101及積體電路結構IC中的另一者是記憶體晶粒。第一晶粒101與積體電路結構IC可視需要具有相似的功能。
在一些實施例中，積體電路結構IC的尺寸大於第一晶粒101的尺寸，如圖4A所示。尺寸可為高度、寬度、大小、俯視圖面積或其組合。然而，本公開並非僅限於此。在替代實施例中，積體電路結構IC可具有與第一晶粒101的尺寸實質上相同的尺寸。
在一些實施例中，積體電路結構IC是單晶粒結構。在一些實例中，積體電路結構IC可被稱為底部晶片。在一些實施例中，積體電路結構IC包括半導體基底Si、內連結構ISi及結合結構BSi。
半導體基底Si可相似於半導體基底S，半導體基底Si的材料及配置可參照半導體基底S的材料及配置。內連結構ISi可設置在半導體基底S的第一側（例如，前側）之上。具體來說，內連結構IS可設置在位於半導體基底S上和/或半導體基底S中的元件之上並電連接到所述元件。在一些實施例中，內連結構ISi包括金屬間介電層及嵌入在金屬間介電層中的金屬特徵。
結合結構BSi可設置在半導體基底Si的第一側（例如，前側）之上。具體來說，結合結構BSi可設置在內連結構ISi之上且電連接到內連結構ISi。在一些實施例中，結合結構BSi包括至少一個結合膜BFi及嵌入在結合膜BFi中的結合金屬特徵。在一些實施例中，結合膜BFi包含氧化矽、氮化矽、聚合物或其組合。在一些實施例中，結合金屬特徵包括電連接到第一晶粒101的結合襯墊BPi。結合金屬特徵可包含Cu、Ti、Ta、W、Ru、Co、Ni、其組合等。在一些實施例中，在每一結合金屬特徵與結合膜BFi之間可設置有晶種層和/或阻擋層。晶種層可包含Ti/Cu。阻擋層可包含Ta、TaN、Ti、TiN、CoW或其組合。
再次參照圖4A，將第一晶粒101在第一晶粒101的第一側（例如，前側）結合到積體電路結構IC。在一些實施例中，通過包括金屬到金屬結合及介電質到介電質結合的混合結合將第一晶粒101結合到積體電路結構IC。具體來說，將第一晶粒101的上部襯墊UP結合到積體電路結構IC的結合襯墊BPi，且將第一晶粒101的金屬間介電層IMD結合到積體電路結構IC的結合膜BFi。然而，本公開並非僅限於此，且可應用另一種結合技術，例如直接結合、金屬擴散、陽極結合、熔融結合等。
在一些實施例中，第一晶粒101與積體電路結構IC以面對面配置堆疊，如圖4A所示。然而，本公開並非僅限於此，且可應用另一種面對背配置。
參照圖4B，局部地移除第一晶粒101的半導體基底S以暴露出基底穿孔TSV的一些部分（例如，底部部分）。在一些實施例中，局部移除操作包括執行等向性蝕刻，例如乾式蝕刻。在一些實施例中，蝕刻氣體包括含氟氣體，例如NF3 、SF6 、CF4 、CHF3 、CH2 F2 等或其組合。
在一些實施例中，在局部地移除半導體基底S之後，內連結構IS寬於剩餘的半導體基底S。具體來說，局部移除操作不僅移除半導體基底S的底部部分以暴露出基底穿孔TSV的底部部分，而且還移除半導體基底S的側部分以暴露出內連結構IS的金屬間介電層IMD的一部分。在一些實施例中，在局部地移除半導體基底S的操作期間，局部地移除積體電路結構IC的結合膜BFi。因此，剩餘的結合膜BFi在中心區較厚而在邊緣區較薄。
參照圖4C，形成介電層DL，所述介電層DL位在第一晶粒101的頂部及側壁之上以及圍繞基底穿孔TSV的被暴露出的部分（例如，底部部分）。在一些實施例中，介電層DL更遠離第一晶粒101沿橫向延伸並覆蓋積體電路結構IC的結合膜BFi的被暴露出的頂表面。
本公開的介電層DL不僅用作用於將第一晶粒101結合到期望組件（例如重佈線層結構）的結合膜，而且還用作用於將第一晶粒101與不期望的組件或材料隔離的隔離膜。在一些實施例中，介電層DL可包含氧化矽、氮化矽、氮氧化矽、介電常數小於3.5的低介電常數材料（例如，碳摻雜氧化物）等或其組合。形成介電層DL的方法包括以下操作。通過合適的製程（例如化學氣相沉積（CVD）或電漿增強CVD（PECVD））在覆蓋第一晶粒100的積體電路結構IC之上形成介電材料層，但是也可利用任何合適的製程。此後，執行平坦化製程（例如化學機械研磨（CMP））以局部地移除介電材料層，直到暴露出基底穿孔TSV1的表面（例如，底表面）。
參照圖4D，在第一晶粒101周圍以及積體電路結構IC之上形成介電包封體E。在一些實施例中，介電包封體E通過介電層DL與第一晶粒100或積體電路結構隔開。
仍然參照圖4D，在第一晶粒101及介電包封體E之上形成重佈線層結構RDL。重佈線層結構RDL形成在第一晶粒100的第二側（例如，背側）之上。在一些實例中，重佈線層結構RDL可被稱為背面重佈線層結構。重佈線層結構RDL包括至少一個聚合物層PL及被聚合物層PL嵌入的導電特徵。導電特徵包括上部金屬襯墊UMP以及下部金屬襯墊LMP，上部金屬襯墊UMP被配置成電連接到期望組件（例如凸塊），下部金屬襯墊LMP被配置成電連接到第一晶粒101的基底穿孔TSV。在一些實施例中，聚合物層PL可包含感光性材料，例如聚苯並惡唑（PBO）、聚醯亞胺（polyimide，PI）、苯並環丁烯（BCB）、其組合等。重佈線層結構RDL的聚合物層可視需要由介電層或絕緣層替換。在一些實施例中，下部金屬襯墊LMP及上部金屬襯墊UMP可包含Cu、Ti、Ta、W、Ru、Co、Ni、其組合等。在一些實施例中，在每一金屬襯墊與聚合物層PM之間可設置有晶種層和/或阻擋層。晶種層可包含Ti/Cu。阻擋層可包含Ta、TaN、Ti、TiN、CoW或其組合。
仍然參照圖4D，將凸塊B形成為電連接到重佈線層結構RDL。凸塊B在第一晶粒101的第二側（例如，背側）電連接到第一晶粒101。本公開的積體電路封裝20由此完成。
提供其仲介電層DL是單層的上述實施例是出於說明目的，且上述實施例不應被視為限制本公開。具體來說，本公開的介電層DL可視需要形成為具有多層式結構。在一些實施例中，當圖4C所示介電層DL被形成為具有包括下部介電層LDL及上部介電層UDL的多層式結構時，形成本公開的積體電路封裝20a，如圖5所示。下部介電層LDL與上部介電層UDL可包含不同的材料並提供不同的功能。舉例來說，下部介電層LDL用作用於改善上部介電層UDL與銅或矽之間的黏合的黏合膜，且上部介電層UDL用作用於將第一晶粒101與不期望的組件或材料隔離的隔離膜。在一些實施例中，下部介電層LDL及上部介電層UDL中的每一者可包含氧化矽、氮化矽、氮氧化矽、介電常數小於3.5的低介電常數材料（例如，碳摻雜氧化物）等或其組合。
提供其中積體電路封裝具有結合到積體電路結構的第一晶粒的上述實施例是出於說明目的，且上述實施例不應被視為限制本公開。在一些實施例中，可提供包括多個第一晶粒的晶粒堆疊，且接著將晶粒堆疊結合到積體電路結構。在替代實施例中，可視需要調整積體電路結構中所包括的晶粒的數目。
在一些實施例中，將圖4B及圖4C所述操作執行兩次，且因此形成包括第一層第一晶粒101到第二層第一晶粒101的晶粒堆疊。可視需要將圖4B及圖4C所述操作重複許多次，直到垂直地堆疊期望數目的第一晶粒101。此後，在最頂部第一晶粒101（例如，第二層第一晶粒101）的第二側（例如，背側）之上形成重佈線層結構RDL，且將凸塊B形成為電連接到重佈線層結構RDL。本公開的積體電路封裝20b由此完成。
以下參照圖4D、圖5及圖6說明本公開的結構。
在一些實施例中，積體電路封裝20/20a/20b包括至少一個第一晶粒101、積體電路結構IC、介電層DL及多個凸塊B。所述至少一個第一晶粒101在所述至少一個第一晶粒101的第一側（例如，前側）結合到積體電路結構IC。在一些實施例中，（最底部）第一晶粒101與積體電路結構IC通過包括金屬到金屬結合及介電質到介電質結合的混合結合而結合在一起。介電層DL覆蓋所述至少一個第一晶粒101的頂部及側壁。凸塊B在第一晶粒101的第二側（例如，背側）電連接到（最頂部）第一晶粒101。所述至少一個第一晶粒101的第二側與第一側相對。
在一些實施例中，第一晶粒101包括半導體基底S及內連結構IS，且內連結構IS寬於半導體基底S。在一些實施例中，積體電路結構IC包括半導體基底Si及內連結構ISi，且內連結構ISi實質上與半導體基底Si一樣寬。在一些實施例中，半導體基底Si寬於半導體基底S。
在一些實施例中，積體電路封裝20/20a/20b更包括位於最頂部第一晶粒101的第二側（例如，背側）與凸塊B之間的重佈線層結構RDL。
本公開的介電層DL設置在最頂部第一晶粒101與重佈線層結構RDL之間，並覆蓋所述至少一個第一晶粒101的側壁。在一些實施例中，介電層DL環繞所述至少一個第一晶粒101的基底穿孔TSV的一些部分。在一些實施例中，介電層DL的表面與基底穿孔TSV的表面實質上共面。
在一些實施例中，如圖4D所示，介電層DL是單層。在一些實施例中，如圖5及圖6所示，介電層DL具有多層式結構。
在一些實施例中，介電層DL具有階梯式側壁，所述階梯式側壁具有多個轉捩點。在一些實施例中，介電層DL具有一個階梯的輪廓，如圖4D及圖5所示。在一些實施例中，介電層DL具有多階梯輪廓，如圖6所示。在一些實施例中，介電層DL更遠離第一晶粒101沿橫向延伸，如圖4D、圖5及圖6所示。
在一些實施例中，如圖6所示，所述至少一個第一晶粒101包括垂直地堆疊的多個第一晶粒101。在一些實施例中，兩個相鄰的第一晶粒101通過包括金屬到金屬結合及介電質到介電質結合的混合結合而結合在一起。在一些實施例中，位於靠近積體電路結構IC的第一晶粒101（例如，第一層第一晶粒101）的側壁上的介電層DL厚於位於遠離積體電路結構IC的第一晶粒（例如，第二層第一晶粒101）的側壁上的介電層DL。在一些實施例中，介電層DL更設置在兩個相鄰的第一晶粒101之間。
在一些實施例中，積體電路封裝20/20a/20b更包括介電包封體E，介電包封體E圍繞所述至少一個第一晶粒101設置且設置在積體電路結構IC之上。在一些實施例中，介電包封體E通過介電層DL與所述至少一個第一晶粒101隔開。
有鑒於上述，本公開的介電層設置在所述相鄰的晶粒之間以及最頂部晶粒與重佈線層結構之間並覆蓋晶粒的整個側壁。在一些實施例中，對應的晶粒之上的每一介電層用作用於將晶粒與不期望的組件或材料隔開的隔離膜。此外，本公開的方法簡單並且與現有製程相容。
本公開預期涵蓋以上實例的許多變化。應理解，不同的實施例可具有不同的優點，且所有實施例未必需要特定的優點。
根據本公開的一些實施例，一種積體電路封裝包括至少一個第一晶粒、多個凸塊、第二晶粒以及介電層。所述凸塊在所述至少一個第一晶粒的第一側電連接到所述至少一個第一晶粒。所述第二晶粒在所述至少一個第一晶粒的第二側電連接到所述至少一個第一晶粒。所述至少一個第一晶粒的所述第二側與所述第一側相對。所述介電層設置在所述至少一個第一晶粒與所述第二晶粒之間且覆蓋所述至少一個第一晶粒的側壁。
在一些實施例中，所述第一晶粒包括第一半導體基底及穿透過所述第一半導體基底的多個第一基底穿孔，且所述介電層環繞所述第一基底穿孔的一些部分。在一些實施例中，所述第一晶粒更包括位於所述凸塊與所述第一半導體基底之間的第一內連結構，且所述第一內連結構寬於所述第一半導體基底。在一些實施例中，所述積體電路封裝更包括：介電包封體，圍繞所述至少一個第一晶粒及所述第二晶粒設置；以及載體，設置在所述第二晶粒之上且結合到所述第二晶粒。在一些實施例中，所述至少一個第一晶粒包括垂直地堆疊的多個第一晶粒，且位於遠離所述第二晶粒的所述第一晶粒的側壁上的所述介電層厚於位於靠近所述第二晶粒的所述第一晶粒的側壁上的所述介電層。在一些實施例中，所述介電層更設置在兩個相鄰的所述第一晶粒之間。在一些實施例中，所述介電層具有階梯式側壁，所述階梯式側壁具有多個轉捩點。在一些實施例中，所述介電層具有多層式結構。在一些實施例中，所述第一晶粒包括第一半導體基底，所述第二晶粒包括第二半導體基底，且所述第二半導體基底寬於所述第一半導體基底。
根據本公開的替代實施例，一種積體電路封裝包括至少一個第一晶粒、積體電路結構、介電層以及多個凸塊。所述至少一個第一晶粒在所述至少一個第一晶粒的第一側結合到所述積體電路結構。所述介電層覆蓋所述至少一個第一晶粒的頂部及側壁。所述凸塊在所述至少一個第一晶粒的第二側電連接到所述至少一個第一晶粒。所述至少一個第一晶粒的所述第二側與所述第一側相對。
在一些實施例中，所述第一晶粒包括第一半導體基底及穿透過所述第一半導體基底的多個第一基底穿孔，且所述介電層環繞所述第一基底穿孔的一些部分。在一些實施例中，所述第一晶粒更包括位於所述積體電路結構與所述第一半導體基底之間的第一內連結構，且所述第一內連結構寬於所述第一半導體基底。在一些實施例中，所述介電層更遠離所述至少一個第一晶粒沿橫向延伸。在一些實施例中，所述至少一個第一晶粒包括垂直地堆疊的多個第一晶粒，且位於靠近所述積體電路結構的所述第一晶粒的側壁上的所述介電層厚於位於遠離所述積體電路結構的所述第一晶粒的側壁上的所述介電層。在一些實施例中，所述介電層更設置在兩個相鄰的所述第一晶粒之間。在一些實施例中，所述介電層具有階梯式側壁，所述階梯式側壁具有多個轉捩點。
根據本公開的又一些替代實施例，一種形成積體電路封裝的方法包括以下操作。將至少一個第一晶粒在所述至少一個第一晶粒的第一側結合到第一載體，且所述第一晶粒包括第一半導體基底、穿透過所述第一半導體基底的多個第一基底穿孔以及位於所述第一半導體基底之上的第一內連結構。局部地移除所述第一半導體基底，以暴露出所述第一基底穿孔的一些部分。形成介電層，所述介電層位在所述至少一個第一晶粒的頂部及側壁之上以及圍繞所述第一基底穿孔的被暴露出的所述部分。將第二晶粒在所述至少一個第一晶粒的第二側結合到所述至少一個第一晶粒。
在一些實施例中，在局部地移除所述第一半導體基底之後，所述第一內連結構寬於所述第一半導體基底。在一些實施例中，形成所述介電層包括：在所述第一載體之上形成介電材料層，所述介電材料層覆蓋所述至少一個第一晶粒；以及對所述介電材料層執行平坦化製程，直到暴露出所述第一基底穿孔的表面。在一些實施例中，所述形成積體電路封裝的方法更包括：形成介電包封體，所述介電包封體圍繞所述至少一個第一晶粒及所述第二晶粒；將第二載體結合到所述第二晶粒；以及移除所述第一載體。
也可包括其他特徵及製程。舉例來說，可包括測試結構以説明對三維封裝或3DIC元件進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試襯墊（test pad），以便能夠對三維封裝或3DIC進行測試、對探針和/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，可將本文中所公開的結構及方法與包括對已知良好晶粒進行中間驗證的測試方法結合使用，以提高良率並降低成本。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應知，他們可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
100、300、400、500、600:積體晶片 10、10a、10b、20a:積體電路封裝 20、20b:積體電路封裝 100:第一晶粒 101:第一晶粒 200:第二晶粒 B:凸塊 BF1、BF2、BFC1、BFC2、BFi:結合膜 BPi:結合襯墊 BSi:結合結構 C1:載體 C2:載體 DL、DL1、DL2、DL3、DL4:介電層 E:介電包封體 IC:積體電路結構 IL:絕緣層 IMD、IMD1、IMD2:金屬間介電層 IS、IS1、IS2、ISi:內連結構 LDL:下部介電層 LMP:下部金屬襯墊 LP、LP1:下部襯墊 P2:襯墊 PL:聚合物層 RDL:重佈線層結構 S、S1、S2、Si:半導體基底 TSV、TSV1:基底穿孔 UDL:上部介電層 UMP:上部金屬襯墊 UP、UP1:上部襯墊
圖1A到圖1G是根據一些實施例的形成積體電路封裝的方法的剖視圖。 圖2是根據一些實施例的積體電路封裝的剖視圖。 圖3A到圖3F是根據一些實施例的形成積體電路封裝的方法的剖視圖。 圖4A到圖4D是根據替代實施例的形成積體電路封裝的方法的剖視圖。 圖5是根據替代實施例的積體電路封裝的剖視圖。 圖6是根據替代實施例的積體電路封裝的剖視圖。
10:積體電路封裝
100:第一晶粒
200:第二晶粒
B:凸塊
BFC2、BF2:結合膜
C2:載體
DL:介電層
E:介電包封體
IL:絕緣層
IMD1、IMD2:金屬間介電層
IS1、IS2:內連結構
LP1:下部襯墊
P2:襯墊
S1、S2:半導體基底
TSV1:基底穿孔
UP1:上部襯墊

Claims (1)

  1. 一種積體電路封裝，包括： 至少一個第一晶粒； 多個凸塊，在所述至少一個第一晶粒的第一側電連接到所述至少一個第一晶粒； 第二晶粒，在所述至少一個第一晶粒的第二側電連接到所述至少一個第一晶粒，其中所述至少一個第一晶粒的所述第二側與所述第一側相對；以及 介電層，設置在所述至少一個第一晶粒與所述第二晶粒之間且覆蓋所述至少一個第一晶粒的側壁。
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