CN112086407A - 集成电路封装及其形成方法 - Google Patents

集成电路封装及其形成方法 Download PDF

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Publication number
CN112086407A
CN112086407A CN202010069953.9A CN202010069953A CN112086407A CN 112086407 A CN112086407 A CN 112086407A CN 202010069953 A CN202010069953 A CN 202010069953A CN 112086407 A CN112086407 A CN 112086407A
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die
dielectric layer
semiconductor substrate
integrated circuit
dielectric
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许家豪
林咏淇
邱文智
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN112086407A publication Critical patent/CN112086407A/zh
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Abstract

本发明实施例提供集成电路封装以及形成所述集成电路封装的方法。一种集成电路封装包括至少一个第一管芯、多个凸块、第二管芯以及介电层。所述凸块在所述至少一个第一管芯的第一侧电连接到所述至少一个第一管芯。所述第二管芯在所述至少一个第一管芯的第二侧电连接到所述至少一个第一管芯。所述至少一个第一管芯的所述第二侧与所述第一侧相对。所述介电层设置在所述至少一个第一管芯与所述第二管芯之间且覆盖所述至少一个第一管芯的侧壁。

Description

集成电路封装及其形成方法
技术领域
本发明实施例是涉及集成电路封装及其形成方法。
背景技术
近年来，由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度持续提高，半导体行业已经历快速成长。在很大程度上，集成密度的这种提高来自于最小特征大小(minimum feature size)的连续减小，这使得更多组件能够集成到给定区域中。
这些较小的电子组件也需要与先前的封装相比占据较小面积的较小的封装。半导体封装的类型的实例包括方形扁平封装(quad flat pack，QFP)、引脚栅阵列(pin gridarray，PGA)、球栅阵列(ball grid array，BGA)、倒装芯片(flip chip，FC)、三维集成电路(three dimensional integrated circuit，3DIC)封装、晶片级封装(wafer levelpackage，WLP)及叠层封装(package on package，PoP)器件。一些3DIC是通过在半导体晶片级的管芯之上放置管芯制备而成。3DIC提供提高的集成密度及其他优点(例如，较快的速度及较高的带宽)，这是由于堆叠芯片之间的内连线的长度减小。然而，存在许多与3DIC有关的挑战。
发明内容
根据本公开的一些实施例，一种集成电路封装包括至少一个第一管芯、多个凸块、第二管芯以及介电层。所述凸块在所述至少一个第一管芯的第一侧电连接到所述至少一个第一管芯。所述第二管芯在所述至少一个第一管芯的第二侧电连接到所述至少一个第一管芯。所述至少一个第一管芯的所述第二侧与所述第一侧相对。所述介电层设置在所述至少一个第一管芯与所述第二管芯之间且覆盖所述至少一个第一管芯的侧壁。
根据本公开的替代实施例，一种集成电路封装包括至少一个第一管芯、集成电路结构、介电层以及多个凸块。所述至少一个第一管芯在所述至少一个第一管芯的第一侧结合到所述集成电路结构。所述介电层覆盖所述至少一个第一管芯的顶部及侧壁。所述凸块在所述至少一个第一管芯的第二侧电连接到所述至少一个第一管芯。所述至少一个第一管芯的所述第二侧与所述第一侧相对。
根据本公开的又一些替代实施例，一种形成集成电路封装的方法包括以下操作。将至少一个第一管芯在所述至少一个第一管芯的第一侧结合到第一载体，且所述第一管芯包括第一半导体衬底、穿透过所述第一半导体衬底的多个第一衬底穿孔以及位于所述第一半导体衬底之上的第一内连结构。局部地移除所述第一半导体衬底，以暴露出所述第一衬底穿孔的一些部分。形成介电层，所述介电层位在所述至少一个第一管芯的顶部及侧壁之上以及围绕所述第一衬底穿孔的被暴露出的所述部分。将第二管芯在所述至少一个第一管芯的第二侧结合到所述至少一个第一管芯。
附图说明
图1A到图1G是根据一些实施例的形成集成电路封装的方法的剖视图。
图2是根据一些实施例的集成电路封装的剖视图。
图3A到图3F是根据一些实施例的形成集成电路封装的方法的剖视图。
图4A到图4D是根据替代实施例的形成集成电路封装的方法的剖视图。
图5是根据替代实施例的集成电路封装的剖视图。
图6是根据替代实施例的集成电路封装的剖视图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例是为了以简化方式传达本公开。当然，这些仅为实例而非旨在进行限制。举例来说，在以下说明中，在第一特征之上或第一特征上形成第二特征可包括其中第二特征与第一特征被形成为直接接触的实施例，且也可包括其中第二特征与第一特征之间可形成附加特征从而使得第二特征与第一特征可不直接接触的实施例。另外，在本公开的各种实例中可使用相同的参考编号和/或字母来指代相同或相似的部件。参考编号的这种重复使用是为了简明及清晰起见，且自身并不表示所论述的各个实施例和/或配置之间的关系。
此外，本文中可能使用例如“在…之下”、“在…下方”、“下部的”、“在…上”、“在…之上”、“上覆在…上”、“在…上方”、“上部的”等空间相对性用语来便于阐述图中所示一个元件或特征与另一(其他)元件或特征的关系。除图中所绘示的取向以外，所述空间相对性用语还旨在囊括器件在使用或操作中的不同取向。装置可具有另外的取向(旋转90度或处于其他取向)，且本文所使用的空间相对性描述语可同样相应地作出解释。
图1A到图1G是根据一些实施例的形成集成电路封装的方法的剖视图。应理解，本公开不受以下所述方法限制。对于所述方法的附加实施例来说，可在所述方法之前、期间和/或之后提供附加操作，且可替换或消除以下所述操作中的一些操作。
尽管图1A到图1G是相对于方法阐述的，然而应理解，图1A到图1G中所公开的结构并非仅限于这种方法，而是可单独作为独立于所述方法的结构。
参照图1A，提供第一管芯100。第一管芯100可包括一个或多个有源组件和/或无源组件。在一些实施例中，第一管芯100可包括逻辑管芯、存储器管芯、中央处理器(centralprocessing unit，CPU)、图形处理单元(Graphic processing unit，GPU)、xPU、微机电系统(Micro-electromechanical system，MEMS)管芯、系统芯片(System on Chip，SoC)管芯等。在一些实施例中，第一管芯100包括半导体衬底S1、多个衬底穿孔TSV1以及内连结构IS1。
半导体衬底S1包含元素半导体(例如硅、锗)和/或化合物半导体(例如硅锗、碳化硅、砷化镓、砷化铟、氮化镓或磷化铟)。半导体衬底S1可包括含硅材料。举例来说，半导体衬底S1是绝缘体上硅(silicon-on-insulator，SOI)衬底或硅衬底。在各种实施例中，半导体衬底S1可采用以下形式：平面衬底、具有多个鳍的衬底、纳米线或所属领域的普通技术人员已知的其他形式。根据设计要求，半导体衬底S1可为P型衬底或N型衬底，且其中可具有掺杂区。掺杂区可被配置成用于N型器件或P型器件。半导体衬底S1包括界定至少一个有源区域的隔离结构，且在有源区域上和/或有源区域中设置有至少一个器件。在一些实施例中，器件包括栅极介电层、栅电极、源极/漏极区、间隔件等。
衬底穿孔(例如，硅穿孔)TSV1穿透过半导体衬底S1。衬底穿孔TSV1可包含Cu、Ti、Ta、W、Ru、Co、Ni等或其组合。在一些实施例中，在每一衬底穿孔TSV1与半导体衬底S1之间可设置有晶种层和/或阻挡层。晶种层可包含Ti/Cu。阻挡层可包含Ta、TaN、Ti、TiN、CoW或其组合。在一些实施例中，衬底穿孔TSV1的顶部部分延伸到内连结构IS1中。
内连结构IS1可设置在半导体衬底S1的第一侧(例如，前侧)之上。具体来说，内连结构IS1可设置在器件之上并电连接到器件。在一些实施例中，内连结构IS1包括金属间介电层IMD1及嵌入在金属间介电层IMD1中的金属特征。金属间介电层IMD1可包含氧化硅、氮化硅、氮氧化硅、介电常数小于3.5的低介电常数(低k)材料等或其组合。金属特征可包含Al、Cu、Ti、Ta、W、Ru、Co、Ni等或其组合。在一些实施例中，在每一金属特征与对应的金属间介电层IMD1之间可设置有晶种层和/或阻挡层。晶种层可包含Ti/Cu。阻挡层可包含Ta、TaN、Ti、TiN、CoW或其组合。在一些实施例中，金属特征包括上部衬垫UP1及下部衬垫LP1，上部衬垫UP1被配置成将第一管芯100结合到期望组件(例如凸块)，下部衬垫LP1被配置成供衬底穿孔TSV1着陆在其上。在一些实施例中，上部衬垫UP1及下部衬垫LP1包含不同的材料。举例来说，上部衬垫UP1可包含Al，且下部衬垫LP1可包含Cu。在替代实施例中，上部衬垫UP1与下部衬垫LP1可包含相同的材料。
在第一管芯100中视需要包括结合膜BF1。结合膜BF1可设置在半导体衬底S1的第一侧(例如，前侧)之上。具体来说，结合膜BF1可设置在内连结构IS1之上。在一些实施例中，结合膜BF1包含氧化硅、氮化硅等或其组合。在另一实施例中，利用聚合物(例如苯并环丁烯(benzocyclobutene，BCB)、环氧树脂、有机胶等)作为结合膜BF1的结合材料。
仍然参照图1A，提供载体C1。载体C1上形成有结合膜BFC1。在一些实施例中，载体C1是玻璃衬底或半导体衬底，且结合膜BFC1包含氧化硅、氮化硅等或其组合。在另一实施例中，利用聚合物(例如苯并环丁烯(BCB)、环氧树脂、有机胶等)作为结合膜BFC1的结合材料。在一些实施例中，载体C1的结合膜BFC1包含与第一管芯100的结合膜BF1的材料相同的材料。在替代实施例中，载体C1的结合膜BFC1与第一管芯100的结合膜BF1可包含不同的材料。
再次参照图1A，将第一管芯100在第一管芯100的第一侧(例如，前侧)结合到载体C1。在一些实例中，第一管芯100可被称为第一层管芯(tier-1die)。在一些实施例中，通过熔融结合将第一管芯100结合到载体C1。具体来说，将第一管芯100的结合膜BF1结合到载体C1的结合膜BFC1。然而，本公开并非仅限于此，且可应用另一种结合技术，例如直接结合、金属扩散、阳极结合、包括金属到金属结合及介电质到介电质结合的混合结合等。
参照图1B，局部地移除半导体衬底S1以暴露出衬底穿孔TSV1的一些部分(例如，底部部分)。在一些实施例中，局部移除操作包括执行等向性蚀刻，例如干式蚀刻。在一些实施例中，蚀刻气体包括含氟气体，例如NF3、SF6、CF4、CHF3、CH2F2等或其组合。
在一些实施例中，在局部地移除半导体衬底S1之后，内连结构IS1宽于剩余的半导体衬底S1。具体来说，局部移除操作不仅移除半导体衬底S1的底部部分以暴露出衬底穿孔TSV1的底部部分，而且还移除半导体衬底S1的侧部分以暴露出内连结构IS1的金属间介电层IMD1的一部分。在一些实施例中，在局部地移除半导体衬底S1的操作期间，局部地移除载体C1的结合膜BFC1。因此，剩余的结合膜BFC1在中心区较厚而在边缘区较薄。
参照图1C，形成介电层DL，所述介电层DL位在第一管芯100的顶部及侧壁之上并围绕衬底穿孔TSV1的被暴露出的部分(例如，底部部分)。在一些实施例中，介电层DL还远离第一管芯100沿横向延伸并覆盖载体C1的结合膜BFC1的被暴露出的顶表面。
本公开的介电层DL不仅用作用于将第一管芯100结合到期望组件(例如第二管芯)的结合膜，而且还用作用于将第一管芯100与不期望的组件或材料隔离的隔离膜。在一些实施例中，介电层DL可包含氧化硅、氮化硅、氮氧化硅、介电常数小于3.5的低介电常数材料(例如，碳掺杂氧化物)等或其组合。形成介电层DL的方法包括以下操作。通过合适的工艺(例如化学气相沉积(chemical vapor deposition，CVD)或等离子体增强CVD(plasmaenhanced CVD，PECVD))在载体C1之上形成覆盖第一管芯100的介电材料层，但是也可利用任何合适的工艺。此后，执行平坦化工艺(例如化学机械抛光(chemical mechanicalpolishing，CMP))以局部地移除介电材料层，直到暴露出衬底穿孔TSV1的表面(例如，底表面)。
参照图1D，提供第二管芯200。第二管芯200可包括一个或多个有源组件和/或无源组件。在一些实施例中，第二管芯200可包括逻辑管芯、存储器管芯、CPU、GPU、xPU、MEMS管芯、SoC管芯等。第二管芯200的功能可不同于第一管芯100的功能。举例来说，第一管芯及第二管芯中的一者是逻辑管芯，且第一管芯及第二管芯中的另一者是存储器管芯。第一管芯与第二管芯可视需要具有相似的功能。
第二管芯200的结构可相似于第一管芯100的结构，且第二管芯200的材料及配置可参照第一管芯100的材料及配置。在一些实施例中，第二管芯200包括半导体衬底S2及内连结构IS2。
半导体衬底S2可相似于半导体衬底S1，因此半导体衬底S2的材料及配置可参照半导体衬底S1的材料及配置。在一些实施例中，半导体衬底S2可视需要具有衬底穿孔，例如硅穿孔。在一些实施例中，半导体衬底S2包括界定至少一个有源区域的隔离结构，且在有源区域上和/或有源区域中设置有至少一个器件。在一些实施例中，半导体衬底S2的宽度大于半导体衬底S1的宽度，如图1D所示。然而，本公开并非仅限于此。在替代实施例中，半导体衬底S2实质上与半导体衬底S1一样宽。在又一些替代实施例中，半导体衬底S2的宽度可视需要小于半导体衬底S1的宽度。
内连结构IS2可相似于内连结构IS1，因此内连结构IS2的材料及配置可参照内连结构IS1的材料及配置。在一些实施例中，内连结构IS2可设置在半导体衬底S2的第一侧(例如，前侧)之上。具体来说，内连结构IS2设置在器件之上并电连接到器件。在一些实施例中，内连结构IS2包括金属间介电层IMD2及嵌入在金属间介电层IMD2中的金属特征。在一些实施例中，金属特征包括衬垫P2，衬垫P2被配置成将第二管芯200结合到第一管芯100的衬底穿孔TSV1。在一些实施例中，内连结构IS2实质上与内连结构IS1一样宽，如图1D所示。然而，本公开并非仅限于此。在替代实施例中，内连结构IS2与内连结构IS1可具有不同的宽度。
仍然参照图1D，将第二管芯200在第一管芯100的第二侧(例如，背侧)结合到第一管芯100。在一些实例中，第二管芯200可被称为第二层管芯。在一些实施例中，通过包括金属到金属结合及介电质到介电质结合的混合结合将第二管芯200结合到第一管芯100。具体来说，将第二管芯200的衬垫P2结合到第一管芯100的衬底穿孔TSV1，且将金属间介电层IMD2结合到第一管芯100之上的介电层DL。然而，本公开并非仅限于此，且可应用另一种结合技术，例如直接结合、金属扩散、阳极结合、熔融结合等。
在一些实施例中，第二管芯200与第一管芯100以面对背配置堆叠，如图1D所示。然而，本公开并非仅限于此，且可应用另一种背对背配置。
参照图1E，形成介电包封体E，所述介电包封体E围绕第一管芯100及第二管芯200。在一些实例中，介电包封体E可被称为间隙填充层。在一些实施例中，介电包封体E包含模塑化合物、模塑底部填料、树脂等。在一些实施例中，介电包封体E包含聚合物材料，例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等或其组合。在替代实施例中，介电包封体E包含氧化硅、氮化硅或其组合。在一些实施例中，形成介电包封体E的方法包括以下操作。通过合适的工艺(例如模塑工艺或沉积工艺)在载体C1之上形成覆盖第一管芯100及第二管芯200的包封材料层，但是也可利用任何合适的工艺。此后，执行平坦化工艺(例如化学机械抛光(CMP))以局部地移除包封材料层，直到暴露出半导体衬底S2的表面(例如，底表面)。
参照图1F，在第二管芯200及介电包封体E之上形成结合膜BF2。在一些实施例中，结合膜BF2包含氧化硅、氮化硅等或其组合。在另一实施例中，利用聚合物(例如苯并环丁烯(BCB)、环氧树脂、有机胶等)作为结合膜BF2的结合材料。
参照图1G，提供第二载体C2。载体C2上形成有结合膜BFC2。在一些实施例中，载体C2是玻璃衬底或半导体衬底，且结合膜BFC2包含氧化硅、氮化硅等或其组合。在一些实例中，载体C2可被称为盖体构件。在另一实施例中，利用聚合物(例如苯并环丁烯(BCB)、环氧树脂、有机胶等)作为结合膜BFC2的结合材料。在一些实施例中，载体C2的结合膜BFC2包含的材料与位于第二管芯200之上的结合膜BF2的材料相同。在替代实施例中，载体C2的结合膜BFC2与位于第二管芯200之上的结合膜BF2可包含不同的材料。
仍然参照图1G，将第二载体C2结合到第二管芯200。在一些实施例中，通过熔融结合将载体C2结合到第二管芯200。具体来说，将载体C2的结合膜BFC2结合到第二管芯200的结合膜BF2。然而，本公开并非仅限于此，且可应用另一种结合技术，例如直接结合、金属扩散、阳极结合、包括金属到金属结合及介电质到介电质结合的混合结合等。
再次参照图1G，移除载体C1。在一些实施例中，在移除载体C1的操作期间，同时移除第一管芯100的结合膜BF1及载体C1的结合膜BFC1。
此后，在第一管芯100的第一侧(例如，前侧)之上形成绝缘层IL。在一些实施例中，绝缘层IL可包含氧化硅或合适的介电材料且可通过合适的沉积工艺形成。
然后，在第一管芯100的第一侧(例如，前侧)形成多个凸块B。凸块B设置在内连结构IS1的上部衬垫UP1之上且电连接到内连结构IS1的上部衬垫UP1。在一些实施例中，凸块B包含铜、焊料、镍或其组合。在一些实施例中，凸块B可为焊料球、受控塌陷晶粒连接(controlled collapse chip connection，C4)凸块、球栅阵列(BGA)球、微凸块、化学镀镍钯浸金技术(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸块、铜支柱、混合结合凸块等。本公开的集成电路封装10由此完成。
提供其中介电层DL是单层的上述实施例是出于说明目的，且上述实施例不应被视为限制本公开。具体来说，本公开的介电层DL可视需要形成为具有多层式结构。在一些实施例中，当图1C所示介电层DL被形成为具有包括下部介电层LDL及上部介电层UDL的多层式结构时，形成本公开的集成电路封装10a，如图2所示。下部介电层LDL与上部介电层UDL可包含不同的材料并提供不同的功能。举例来说，下部介电层LDL用作用于改善上部介电层UDL与铜或硅之间的粘合的粘合膜，且上部介电层UDL用作用于将第一管芯100结合到第二管芯200的结合膜。在一些实施例中，下部介电层LDL及上部介电层UDL中的每一者可包含氧化硅、氮化硅、氮氧化硅、介电常数小于3.5的低介电常数材料(例如，碳掺杂氧化物)等或其组合。
提供其中集成电路封装具有结合到第二管芯的第一管芯的上述实施例是出于说明目的，且上述实施例不应被视为限制本公开。在一些实施例中，可提供包括多个第一管芯的管芯堆叠，且接着将管芯堆叠结合到第二管芯。在替代实施例中，可视需要调整第二管芯的数目。
图3A到图3F是根据一些实施例的形成集成电路封装的方法的剖视图。应理解，本公开不受以下所述方法限制。对于所述方法的附加实施例来说，可在所述方法之前、期间和/或之后提供附加操作，且可替换或消除以下所述操作中的一些操作。
尽管图3A到图3F是相对于方法阐述的，然而应理解，图3A到图3F中所公开的结构并非仅限于这种方法，而是可单独作为独立于所述方法的结构。
参照图3A，将第一层第一管芯100在第一层第一管芯100的第一侧(例如，前侧)结合到载体C1。图3A所示操作相似于图1A所示操作，且在本文中不再对其予以赘述。
参照图3B，局部地移除第一层第一管芯100的半导体衬底S1以暴露出衬底穿孔TSV1的一些部分，且形成介电层DL1，所述介电层DL1位在第一层第一管芯100的顶部及侧壁之上并围绕衬底穿孔TSV1的被暴露出的部分。图3B所示操作包括与图1B及图1C所述操作相似的操作，且在本文中不再对其予以赘述。在一些实施例中，介电层DL还远离第一层第一管芯100沿横向延伸并覆盖载体C1的结合膜BFC1的被暴露出的顶表面。在一些实施例中，介电层DL1可包含氧化硅、氮化硅、氮氧化硅、介电常数小于3.5的低介电常数材料(例如，碳掺杂氧化物)等或其组合。
参照图3C，将第二层第一管芯100在第一层第一管芯100的第二侧(例如，背侧)结合到第一层第一管芯100。在一些实施例中，通过包括金属到金属结合及介电质到介电质结合的混合结合将第二层第一管芯100结合到第一层第一管芯100。具体来说，将第二层第一管芯100的上部衬垫UP1结合到第一层第一管芯100的衬底穿孔TSV1，且将第二层第一管芯100的金属间介电层IMD1结合到第一层第一管芯100之上的介电层DL1。然而，本公开并非仅限于此，且可应用另一种结合技术，例如直接结合、金属扩散、阳极结合、熔融结合等。
在一些实施例中，第二层第一管芯100与第一层第一管芯100以面对背配置堆叠，如图3C所示。然而，本公开并非仅限于此，且可应用另一种背对背配置。
在一些实施例中，第二层第一管芯100的内连结构IS1的上部衬垫UP1与下部衬垫LP1可包含相同的材料(例如Cu)；然而，第一层第一管芯100的内连结构IS1的上部衬垫UP1与下部衬垫LP1可分别包含不同的材料(例如Al及Cu)。
此后，局部地移除第二层第一管芯100的半导体衬底S1以暴露出衬底穿孔TSV1的一些部分，且形成介电层DL2，所述介电层DL2位在第二层第一管芯的顶部及侧壁之上并围绕衬底穿孔TSV1的被暴露出的部分。在一些实施例中，介电层DL2还覆盖第一层第一管芯100的侧壁上的介电层DL1，且远离第一管芯100沿横向延伸。在一些实施例中，介电层DL2可包含氧化硅、氮化硅、氮氧化硅、介电常数小于3.5的低介电常数材料(例如，碳掺杂氧化物)等或其组合。在一些实施例中，介电层DL2与介电层DL1包含相同的材料并且通过相同的工艺形成，但本公开并非仅限于此。在替代实施例中，介电层DL2与介电层DL1可视需要包含不同的材料。
参照图3D，通过包括金属到金属结合及介电质到介电质结合的混合结合将第三层第一管芯100结合到第二层第一管芯100。此后，局部地移除第三层第一管芯100的半导体衬底S1以暴露出衬底穿孔TSV1的一些部分，且形成介电层DL3，所述介电层DL3位在第三层第一管芯100的顶部及侧壁之上并围绕衬底穿孔TSV1的被暴露出的部分。图3D所示操作包括与图3B及图3C所述操作相似的操作。在一些实施例中，介电层DL3还覆盖第一层第一管芯100及第二层第一管芯100的侧壁上的介电层DL2，且远离第一管芯100沿横向延伸。在一些实施例中，介电层DL3可包含氧化硅、氮化硅、氮氧化硅、介电常数小于3.5的低介电常数材料(例如，碳掺杂氧化物)等或其组合。在一些实施例中，介电层DL3与介电层DL2包含相同的材料并且通过相同的工艺形成，但本公开并非仅限于此。在替代实施例中，介电层DL3与介电层DL2可视需要包含不同的材料。
参照图3E，通过包括金属到金属结合及介电质到介电质结合的混合结合将第四层第一管芯100结合到第三层第一管芯100。此后，局部地移除第四层第一管芯100的半导体衬底S1以暴露出衬底穿孔TSV1的一些部分，且形成介电层DL4，所述介电层DL4位在第四层第一管芯100的顶部及侧壁之上并围绕衬底穿孔TSV1的被暴露出的部分。图3E所示操作包括与图3B及图3C所述操作相似的操作。在一些实施例中，介电层DL4还覆盖第一层第一管芯100、第二层第一管芯100及第三层第一管芯100的侧壁上的介电层DL3，且远离第一管芯100沿横向延伸。在一些实施例中，介电层DL4可包含氧化硅、氮化硅、氮氧化硅、介电常数小于3.5的低介电常数材料(例如，碳掺杂氧化物)等或其组合。在一些实施例中，介电层DL4与介电层DL3包含相同的材料并且通过相同的工艺形成，但本公开并非仅限于此。在替代实施例中，介电层DL4与介电层DL3可视需要包含不同的材料。在一些实施例中，介电层DL1到DL4构成介电层DL。本公开的介电层DL不仅用作用于将第一管芯100结合到期望组件(例如另一管芯或重布线层结构)的结合膜，而且还用作用于将第一管芯100与不期望的组件或材料隔离的隔离膜。
有鉴于前述内容，将图3B及图3C所述操作执行三次，且因此形成包括第一层第一管芯100到第四层第一管芯100的管芯堆叠。可视需要将图3B及图3C所述操作重复许多次，直到垂直地堆叠期望数目的第一管芯100。
参照图3F，将第二管芯200在最顶部第一管芯100的第二侧(例如，背侧)结合到管芯堆叠的最顶部的第一管芯100(例如，第四层第一管芯100)。此后，形成介电包封体E，所述介电包封体E围绕第一层第一管芯100到第四层第一管芯100。然后，在第二管芯200及介电包封体E之上形成结合膜BF2。接着将第二载体C2结合到第二管芯200。移除载体C1。在一些实施例中，在移除载体C1期间，同时移除介电层DL的一部分(例如，介电层DL1的位于载体C1上的部分)。接下来，在最底部第一管芯100(例如，第一层第一管芯100)的第一侧(例如，前侧)之上形成绝缘层IL。然后，在最底部第一管芯100(例如，第一层第一管芯100)的第一侧(例如，前侧)形成多个凸块B。图3F所示操作包括与图1D到图1G所述操作相似的操作，且在本文中不再对其予以赘述。本公开的集成电路封装10b由此完成。
以下参照图1G、图2及图3F说明本公开的结构。
在一些实施例中，集成电路封装10/10a/10b包括至少一个第一管芯100、多个凸块B、第二管芯200及介电层DL。凸块B在所述至少一个第一管芯100的第一侧(例如，前侧)电连接到所述至少一个第一管芯100。第二管芯200在所述至少一个第一管芯100的第二侧(例如，背侧)电连接到所述至少一个第一管芯100。在一些实施例中，(最顶部)第一管芯100与第二管芯200通过包括金属到金属结合及介电质到介电质结合的混合结合而结合在一起。所述至少一个第一管芯100的第二侧与第一侧相对。
在一些实施例中，第一管芯100包括半导体衬底S1及内连结构IS1，且内连结构IS1宽于半导体衬底S1。在一些实施例中，第二管芯200包括半导体衬底S2及内连结构IS2，且内连结构IS2实质上与半导体衬底S2一样宽。在一些实施例中，半导体衬底S2宽于半导体衬底S1。在替代实施例中，半导体衬底S2的宽度可视需要等于或小于半导体衬底S1的宽度。
本公开的介电层DL设置在所述至少一个第一管芯100与第二管芯200之间，且覆盖所述至少一个第一管芯100的侧壁。在一些实施例中，介电层DL环绕所述至少一个第一管芯100的衬底穿孔TSV1的一些部分。在一些实施例中，介电层DL的表面与衬底穿孔TSV1的表面实质上共面。
在一些实施例中，如图1G所示，介电层DL是单层。在一些实施例中，如图2及图3F所示，介电层DL具有多层式结构。
在一些实施例中，介电层DL具有台阶式侧壁，所述台阶式侧壁具有多个转折点。在一些实施例中，介电层DL具有一个台阶的轮廓，如图1G及图2所示。在一些实施例中，介电层DL具有多台阶轮廓，如图3F所示。在一些实施例中，介电层DL还远离第一管芯100沿横向延伸，如图3F所示。
在一些实施例中，如图3F所示，所述至少一个第一管芯100包括垂直地堆叠的多个第一管芯100。在一些实施例中，两个相邻的第一管芯100通过包括金属到金属结合及介电质到介电质结合的混合结合而结合在一起。在一些实施例中，位于远离第二管芯200的第一管芯100(例如，第一层第一管芯100)的侧壁上的介电层DL厚于位于靠近第二管芯200的第一管芯(例如，第四层第一管芯100)的侧壁上的介电层DL。在一些实施例中，介电层DL还设置在两个相邻的第一管芯100之间。
在一些实施例中，集成电路封装10/10a/10b还包括介电包封体E以及载体C2，介电包封体E围绕所述至少一个第一管芯100及第二管芯200设置，载体C2设置在第二管芯200之上且结合到第二管芯200。在一些实施例中，介电包封体E通过介电层DL与所述至少一个第一管芯100隔开。
有鉴于上述，本公开的介电层设置在所述相邻的管芯之间且覆盖管芯的整个侧壁。在一些实施例中，对应的管芯之上的每一介电层的横向部分用作用于将管芯结合到期望组件的结合膜，且所述介电层的台阶式侧壁部分用作用于将管芯与不期望的组件或材料隔离的隔离膜。此外，本公开的方法简单并且与现有工艺兼容。
图4A到图4D是根据替代实施例的形成集成电路封装的方法的剖视图。应理解，本公开不受以下所述方法限制。对于所述方法的附加实施例来说，可在所述方法之前、期间和/或之后提供附加操作，且可替换或消除以下所述操作中的一些操作。
尽管图4A到图4D是相对于方法阐述的，然而应理解，图4A到图4D中所公开的结构并非仅限于这种方法，而是可单独作为独立于所述方法的结构。
参照图4A，提供第一管芯101。第一管芯101可包括一个或多个有源组件和/或无源组件。在一些实施例中，第一管芯101可包括逻辑管芯、存储器管芯、CPU、GPU、xPU、MEMS管芯、SoC管芯等。第一管芯101可相似于第一管芯100，且第一管芯101的材料及配置可参照第一管芯100的材料及配置。在一些实施例中，第一管芯101包括半导体衬底S、多个衬底穿孔TSV以及内连结构IS。
半导体衬底S可相似于半导体衬底S1，因此半导体衬底S的材料及配置可参照半导体衬底S1的材料及配置。在一些实施例中，半导体衬底S包括界定至少一个有源区域的隔离结构，且在有源区域上和/或有源区域中设置有至少一个器件。
衬底穿孔TSV可相似于衬底穿孔TSV1，因此衬底穿孔TSV的材料及配置可参照衬底穿孔TSV1的材料及配置。衬底穿孔(例如，硅穿孔)TSV穿透过半导体衬底S。在一些实施例中，衬底穿孔TSV的顶部部分延伸到内连结构IS中。
内连结构IS可相似于内连结构IS1，因此内连结构IS的材料及配置可参照内连结构IS1的材料及配置。在一些实施例中，内连结构IS可设置在半导体衬底S的第一侧(例如，前侧)之上。具体来说，内连结构IS可设置在器件之上并电连接到器件。在一些实施例中，内连结构IS包括金属间介电层IMD及嵌入在金属间介电层IMD中的金属特征。在一些实施例中，金属特征包括上部衬垫UP及下部衬垫LP，上部衬垫UP被配置成将第一管芯101结合到期望组件(例如集成电路结构)，下部衬垫LP被配置成供衬底穿孔TSV着陆在其上。在一些实施例中，上部衬垫UP及下部衬垫LP包含相同的材料。举例来说，上部衬垫UP及下部衬垫LP可包含Cu。在替代实施例中，上部衬垫UP与下部衬垫LP可包含不同的材料。
仍然参照图4A，提供集成电路结构IC。集成电路结构IC可包括一个或多个功能器件，例如有源组件和/或无源组件。在一些实施例中，集成电路结构IC可包括逻辑管芯、存储器管芯、CPU、GPU、xPU、MEMS管芯、SoC管芯等。集成电路结构IC的功能可不同于第一管芯101的功能。举例来说，第一管芯101及集成电路结构IC中的一者是逻辑管芯，且第一管芯101及集成电路结构IC中的另一者是存储器管芯。第一管芯101与集成电路结构IC可视需要具有相似的功能。
在一些实施例中，集成电路结构IC的尺寸大于第一管芯101的尺寸，如图4A所示。尺寸可为高度、宽度、大小、俯视图面积或其组合。然而，本公开并非仅限于此。在替代实施例中，集成电路结构IC可具有与第一管芯101的尺寸实质上相同的尺寸。
在一些实施例中，集成电路结构IC是单管芯结构。在一些实例中，集成电路结构IC可被称为底部晶片。在一些实施例中，集成电路结构IC包括半导体衬底Si、内连结构ISi及结合结构BSi。
半导体衬底Si可相似于半导体衬底S，半导体衬底Si的材料及配置可参照半导体衬底S的材料及配置。内连结构ISi可设置在半导体衬底S的第一侧(例如，前侧)之上。具体来说，内连结构IS可设置在位于半导体衬底S上和/或半导体衬底S中的器件之上并电连接到所述器件。在一些实施例中，内连结构ISi包括金属间介电层及嵌入在金属间介电层中的金属特征。
结合结构BSi可设置在半导体衬底Si的第一侧(例如，前侧)之上。具体来说，结合结构BSi可设置在内连结构ISi之上且电连接到内连结构ISi。在一些实施例中，结合结构BSi包括至少一个结合膜BFi及嵌入在结合膜BFi中的结合金属特征。在一些实施例中，结合膜BFi包含氧化硅、氮化硅、聚合物或其组合。在一些实施例中，结合金属特征包括电连接到第一管芯101的结合衬垫BPi。结合金属特征可包含Cu、Ti、Ta、W、Ru、Co、Ni、其组合等。在一些实施例中，在每一结合金属特征与结合膜BFi之间可设置有晶种层和/或阻挡层。晶种层可包含Ti/Cu。阻挡层可包含Ta、TaN、Ti、TiN、CoW或其组合。
再次参照图4A，将第一管芯101在第一管芯101的第一侧(例如，前侧)结合到集成电路结构IC。在一些实施例中，通过包括金属到金属结合及介电质到介电质结合的混合结合将第一管芯101结合到集成电路结构IC。具体来说，将第一管芯101的上部衬垫UP结合到集成电路结构IC的结合衬垫BPi，且将第一管芯101的金属间介电层IMD结合到集成电路结构IC的结合膜BFi。然而，本公开并非仅限于此，且可应用另一种结合技术，例如直接结合、金属扩散、阳极结合、熔融结合等。
在一些实施例中，第一管芯101与集成电路结构IC以面对面配置堆叠，如图4A所示。然而，本公开并非仅限于此，且可应用另一种面对背配置。
参照图4B，局部地移除第一管芯101的半导体衬底S以暴露出衬底穿孔TSV的一些部分(例如，底部部分)。在一些实施例中，局部移除操作包括执行等向性蚀刻，例如干式蚀刻。在一些实施例中，蚀刻气体包括含氟气体，例如NF3、SF6、CF4、CHF3、CH2F2等或其组合。
在一些实施例中，在局部地移除半导体衬底S之后，内连结构IS宽于剩余的半导体衬底S。具体来说，局部移除操作不仅移除半导体衬底S的底部部分以暴露出衬底穿孔TSV的底部部分，而且还移除半导体衬底S的侧部分以暴露出内连结构IS的金属间介电层IMD的一部分。在一些实施例中，在局部地移除半导体衬底S的操作期间，局部地移除集成电路结构IC的结合膜BFi。因此，剩余的结合膜BFi在中心区较厚而在边缘区较薄。
参照图4C，形成介电层DL，所述介电层DL位在第一管芯101的顶部及侧壁之上以及围绕衬底穿孔TSV的被暴露出的部分(例如，底部部分)。在一些实施例中，介电层DL还远离第一管芯101沿横向延伸并覆盖集成电路结构IC的结合膜BFi的被暴露出的顶表面。
本公开的介电层DL不仅用作用于将第一管芯101结合到期望组件(例如重布线层结构)的结合膜，而且还用作用于将第一管芯101与不期望的组件或材料隔离的隔离膜。在一些实施例中，介电层DL可包含氧化硅、氮化硅、氮氧化硅、介电常数小于3.5的低介电常数材料(例如，碳掺杂氧化物)等或其组合。形成介电层DL的方法包括以下操作。通过合适的工艺(例如化学气相沉积(CVD)或等离子体增强CVD(PECVD))在覆盖第一管芯100的集成电路结构IC之上形成介电材料层，但是也可利用任何合适的工艺。此后，执行平坦化工艺(例如化学机械抛光(CMP))以局部地移除介电材料层，直到暴露出衬底穿孔TSV1的表面(例如，底表面)。
参照图4D，在第一管芯101周围以及集成电路结构IC之上形成介电包封体E。在一些实施例中，介电包封体E通过介电层DL与第一管芯100或集成电路结构隔开。
仍然参照图4D，在第一管芯101及介电包封体E之上形成重布线层结构RDL。重布线层结构RDL形成在第一管芯100的第二侧(例如，背侧)之上。在一些实例中，重布线层结构RDL可被称为背面重布线层结构。重布线层结构RDL包括至少一个聚合物层PL及被聚合物层PL嵌入的导电特征。导电特征包括上部金属衬垫UMP以及下部金属衬垫LMP，上部金属衬垫UMP被配置成电连接到期望组件(例如凸块)，下部金属衬垫LMP被配置成电连接到第一管芯101的衬底穿孔TSV。在一些实施例中，聚合物层PL可包含感光性材料，例如聚苯并恶唑(PBO)、聚酰亚胺(polyimide，PI)、苯并环丁烯(BCB)、其组合等。重布线层结构RDL的聚合物层可视需要由介电层或绝缘层替换。在一些实施例中，下部金属衬垫LMP及上部金属衬垫UMP可包含Cu、Ti、Ta、W、Ru、Co、Ni、其组合等。在一些实施例中，在每一金属衬垫与聚合物层PM之间可设置有晶种层和/或阻挡层。晶种层可包含Ti/Cu。阻挡层可包含Ta、TaN、Ti、TiN、CoW或其组合。
仍然参照图4D，将凸块B形成为电连接到重布线层结构RDL。凸块B在第一管芯101的第二侧(例如，背侧)电连接到第一管芯101。本公开的集成电路封装20由此完成。
提供其中介电层DL是单层的上述实施例是出于说明目的，且上述实施例不应被视为限制本公开。具体来说，本公开的介电层DL可视需要形成为具有多层式结构。在一些实施例中，当图4C所示介电层DL被形成为具有包括下部介电层LDL及上部介电层UDL的多层式结构时，形成本公开的集成电路封装20a，如图5所示。下部介电层LDL与上部介电层UDL可包含不同的材料并提供不同的功能。举例来说，下部介电层LDL用作用于改善上部介电层UDL与铜或硅之间的粘合的粘合膜，且上部介电层UDL用作用于将第一管芯101与不期望的组件或材料隔离的隔离膜。在一些实施例中，下部介电层LDL及上部介电层UDL中的每一者可包含氧化硅、氮化硅、氮氧化硅、介电常数小于3.5的低介电常数材料(例如，碳掺杂氧化物)等或其组合。
提供其中集成电路封装具有结合到集成电路结构的第一管芯的上述实施例是出于说明目的，且上述实施例不应被视为限制本公开。在一些实施例中，可提供包括多个第一管芯的管芯堆叠，且接着将管芯堆叠结合到集成电路结构。在替代实施例中，可视需要调整集成电路结构中所包括的管芯的数目。
在一些实施例中，将图4B及图4C所述操作执行两次，且因此形成包括第一层第一管芯101到第二层第一管芯101的管芯堆叠。可视需要将图4B及图4C所述操作重复许多次，直到垂直地堆叠期望数目的第一管芯101。此后，在最顶部第一管芯101(例如，第二层第一管芯101)的第二侧(例如，背侧)之上形成重布线层结构RDL，且将凸块B形成为电连接到重布线层结构RDL。本公开的集成电路封装20b由此完成。
以下参照图4D、图5及图6说明本公开的结构。
在一些实施例中，集成电路封装20/20a/20b包括至少一个第一管芯101、集成电路结构IC、介电层DL及多个凸块B。所述至少一个第一管芯101在所述至少一个第一管芯101的第一侧(例如，前侧)结合到集成电路结构IC。在一些实施例中，(最底部)第一管芯101与集成电路结构IC通过包括金属到金属结合及介电质到介电质结合的混合结合而结合在一起。介电层DL覆盖所述至少一个第一管芯101的顶部及侧壁。凸块B在第一管芯101的第二侧(例如，背侧)电连接到(最顶部)第一管芯101。所述至少一个第一管芯101的第二侧与第一侧相对。
在一些实施例中，第一管芯101包括半导体衬底S及内连结构IS，且内连结构IS宽于半导体衬底S。在一些实施例中，集成电路结构IC包括半导体衬底Si及内连结构ISi，且内连结构ISi实质上与半导体衬底Si一样宽。在一些实施例中，半导体衬底Si宽于半导体衬底S。
在一些实施例中，集成电路封装20/20a/20b还包括位于最顶部第一管芯101的第二侧(例如，背侧)与凸块B之间的重布线层结构RDL。
本公开的介电层DL设置在最顶部第一管芯101与重布线层结构RDL之间，并覆盖所述至少一个第一管芯101的侧壁。在一些实施例中，介电层DL环绕所述至少一个第一管芯101的衬底穿孔TSV的一些部分。在一些实施例中，介电层DL的表面与衬底穿孔TSV的表面实质上共面。
在一些实施例中，如图4D所示，介电层DL是单层。在一些实施例中，如图5及图6所示，介电层DL具有多层式结构。
在一些实施例中，介电层DL具有台阶式侧壁，所述台阶式侧壁具有多个转折点。在一些实施例中，介电层DL具有一个台阶的轮廓，如图4D及图5所示。在一些实施例中，介电层DL具有多台阶轮廓，如图6所示。在一些实施例中，介电层DL还远离第一管芯101沿横向延伸，如图4D、图5及图6所示。
在一些实施例中，如图6所示，所述至少一个第一管芯101包括垂直地堆叠的多个第一管芯101。在一些实施例中，两个相邻的第一管芯101通过包括金属到金属结合及介电质到介电质结合的混合结合而结合在一起。在一些实施例中，位于靠近集成电路结构IC的第一管芯101(例如，第一层第一管芯101)的侧壁上的介电层DL厚于位于远离集成电路结构IC的第一管芯(例如，第二层第一管芯101)的侧壁上的介电层DL。在一些实施例中，介电层DL还设置在两个相邻的第一管芯101之间。
在一些实施例中，集成电路封装20/20a/20b还包括介电包封体E，介电包封体E围绕所述至少一个第一管芯101设置且设置在集成电路结构IC之上。在一些实施例中，介电包封体E通过介电层DL与所述至少一个第一管芯101隔开。
有鉴于上述，本公开的介电层设置在所述相邻的管芯之间以及最顶部管芯与重布线层结构之间并覆盖管芯的整个侧壁。在一些实施例中，对应的管芯之上的每一介电层用作用于将管芯与不期望的组件或材料隔开的隔离膜。此外，本公开的方法简单并且与现有工艺兼容。
本公开预期涵盖以上实例的许多变化。应理解，不同的实施例可具有不同的优点，且所有实施例未必需要特定的优点。
根据本公开的一些实施例，一种集成电路封装包括至少一个第一管芯、多个凸块、第二管芯以及介电层。所述凸块在所述至少一个第一管芯的第一侧电连接到所述至少一个第一管芯。所述第二管芯在所述至少一个第一管芯的第二侧电连接到所述至少一个第一管芯。所述至少一个第一管芯的所述第二侧与所述第一侧相对。所述介电层设置在所述至少一个第一管芯与所述第二管芯之间且覆盖所述至少一个第一管芯的侧壁。
在一些实施例中，所述第一管芯包括第一半导体衬底及穿透过所述第一半导体衬底的多个第一衬底穿孔，且所述介电层环绕所述第一衬底穿孔的一些部分。在一些实施例中，所述第一管芯还包括位于所述凸块与所述第一半导体衬底之间的第一内连结构，且所述第一内连结构宽于所述第一半导体衬底。在一些实施例中，所述集成电路封装还包括：介电包封体，围绕所述至少一个第一管芯及所述第二管芯设置；以及载体，设置在所述第二管芯之上且结合到所述第二管芯。在一些实施例中，所述至少一个第一管芯包括垂直地堆叠的多个第一管芯，且位于远离所述第二管芯的所述第一管芯的侧壁上的所述介电层厚于位于靠近所述第二管芯的所述第一管芯的侧壁上的所述介电层。在一些实施例中，所述介电层还设置在两个相邻的所述第一管芯之间。在一些实施例中，所述介电层具有台阶式侧壁，所述台阶式侧壁具有多个转折点。在一些实施例中，所述介电层具有多层式结构。在一些实施例中，所述第一管芯包括第一半导体衬底，所述第二管芯包括第二半导体衬底，且所述第二半导体衬底宽于所述第一半导体衬底。
根据本公开的替代实施例，一种集成电路封装包括至少一个第一管芯、集成电路结构、介电层以及多个凸块。所述至少一个第一管芯在所述至少一个第一管芯的第一侧结合到所述集成电路结构。所述介电层覆盖所述至少一个第一管芯的顶部及侧壁。所述凸块在所述至少一个第一管芯的第二侧电连接到所述至少一个第一管芯。所述至少一个第一管芯的所述第二侧与所述第一侧相对。
在一些实施例中，所述第一管芯包括第一半导体衬底及穿透过所述第一半导体衬底的多个第一衬底穿孔，且所述介电层环绕所述第一衬底穿孔的一些部分。在一些实施例中，所述第一管芯还包括位于所述集成电路结构与所述第一半导体衬底之间的第一内连结构，且所述第一内连结构宽于所述第一半导体衬底。在一些实施例中，所述介电层还远离所述至少一个第一管芯沿横向延伸。在一些实施例中，所述至少一个第一管芯包括垂直地堆叠的多个第一管芯，且位于靠近所述集成电路结构的所述第一管芯的侧壁上的所述介电层厚于位于远离所述集成电路结构的所述第一管芯的侧壁上的所述介电层。在一些实施例中，所述介电层还设置在两个相邻的所述第一管芯之间。在一些实施例中，所述介电层具有台阶式侧壁，所述台阶式侧壁具有多个转折点。
根据本公开的又一些替代实施例，一种形成集成电路封装的方法包括以下操作。将至少一个第一管芯在所述至少一个第一管芯的第一侧结合到第一载体，且所述第一管芯包括第一半导体衬底、穿透过所述第一半导体衬底的多个第一衬底穿孔以及位于所述第一半导体衬底之上的第一内连结构。局部地移除所述第一半导体衬底，以暴露出所述第一衬底穿孔的一些部分。形成介电层，所述介电层位在所述至少一个第一管芯的顶部及侧壁之上以及围绕所述第一衬底穿孔的被暴露出的所述部分。将第二管芯在所述至少一个第一管芯的第二侧结合到所述至少一个第一管芯。
在一些实施例中，在局部地移除所述第一半导体衬底之后，所述第一内连结构宽于所述第一半导体衬底。在一些实施例中，形成所述介电层包括：在所述第一载体之上形成介电材料层，所述介电材料层覆盖所述至少一个第一管芯；以及对所述介电材料层执行平坦化工艺，直到暴露出所述第一衬底穿孔的表面。在一些实施例中，所述形成集成电路封装的方法还包括：形成介电包封体，所述介电包封体围绕所述至少一个第一管芯及所述第二管芯；将第二载体结合到所述第二管芯；以及移除所述第一载体。
也可包括其他特征及工艺。举例来说，可包括测试结构以帮助对三维封装或3DIC器件进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试衬垫(test pad)，以便能够对三维封装或3DIC进行测试、对探针和/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外，可将本文中所公开的结构及方法与包括对已知良好管芯进行中间验证的测试方法结合使用，以提高良率并降低成本。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应知，他们可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开的精神及范围，而且他们可在不背离本公开的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (1)

1.一种集成电路封装，其特征在于包括：
至少一个第一管芯；
多个凸块，在所述至少一个第一管芯的第一侧电连接到所述至少一个第一管芯；
第二管芯，在所述至少一个第一管芯的第二侧电连接到所述至少一个第一管芯，其中所述至少一个第一管芯的所述第二侧与所述第一侧相对；以及
介电层，设置在所述至少一个第一管芯与所述第二管芯之间且覆盖所述至少一个第一管芯的侧壁。
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