US11145623B2 - Integrated circuit packages and methods of forming the same - Google Patents

Integrated circuit packages and methods of forming the same Download PDF

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Publication number
US11145623B2
US11145623B2 US16/441,013 US201916441013A US11145623B2 US 11145623 B2 US11145623 B2 US 11145623B2 US 201916441013 A US201916441013 A US 201916441013A US 11145623 B2 US11145623 B2 US 11145623B2
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Prior art keywords
die
integrated circuit
dielectric layer
semiconductor substrate
circuit package
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US16/441,013
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US20200395338A1 (en
Inventor
Chia-Hao Hsu
Yung-Chi Lin
Wen-Chih Chiou
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US16/441,013 priority Critical patent/US11145623B2/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIOU, WEN-CHIH, HSU, CHIA-HAO, LIN, YUNG-CHI
Priority to TW108145496A priority patent/TW202046464A/zh
Priority to CN202010069953.9A priority patent/CN112086407A/zh
Publication of US20200395338A1 publication Critical patent/US20200395338A1/en
Priority to US17/458,549 priority patent/US11728314B2/en
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Publication of US11145623B2 publication Critical patent/US11145623B2/en
Priority to US18/342,749 priority patent/US20230343753A1/en
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    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps

Definitions

  • 3DICs are prepared by placing dies over dies on a semiconductor wafer level.
  • the 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked dies.
  • challenges related to 3DICs there are many challenges related to 3DICs.
  • FIG. 1A to FIG. 1G are cross-sectional views of a method of forming an integrated circuit package in accordance with some embodiments.
  • FIG. 2 is a cross-sectional view of an integrated circuit package in accordance with some embodiments.
  • FIG. 3A to FIG. 3F are cross-sectional views of a method of forming an integrated circuit package in accordance with some embodiments.
  • FIG. 4A to FIG. 4D are cross-sectional views of a method of forming an integrated circuit package in accordance with alternative embodiments.
  • FIG. 5 is a cross-sectional view of an integrated circuit package in accordance with alternative embodiments.
  • FIG. 6 is a cross-sectional view of an integrated circuit package in accordance with alternative embodiments.
  • the following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below for the purposes of conveying the present disclosure in a simplified manner. These are, of course, merely examples and are not intended to be limiting.
  • the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact.
  • the same reference numerals and/or letters may be used to refer to the same or similar parts in the various examples the present disclosure. The repeated use of the reference numerals is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
  • spatially relative terms such as “beneath”, “below”, “lower”, “on”, “over”, “overlying”, “above”, “upper” and the like, may be used herein to facilitate the description of one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • FIG. 1A to FIG. 1G are cross-sectional views of a method of forming an integrated circuit package in accordance with some embodiments. It is understood that the disclosure is not limited by the method described below. Additional operations can be provided before, during, and/or after the method and some of the operations described below can be replaced or eliminated, for additional embodiments of the methods.
  • FIG. 1A to FIG. 1G are described in relation to a method, it is appreciated that the structures disclosed in FIG. 1A to FIG. 1G are not limited to such a method, but instead may stand alone as structures independent of the method.
  • the first die 100 may include one or more active components and/or passive components.
  • the first die 100 may include a logic die, a memory die, a CPU, a GPU, an xPU, a MEMS die, a SoC die, or the like.
  • the first die 100 includes a semiconductor substrate S 1 , a plurality of through substrate vias TSV 1 and an interconnect structure IS 1 .
  • the semiconductor substrate S 1 includes an elementary semiconductor such as silicon, germanium and/or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride or indium phosphide.
  • the semiconductor substrate S 1 may include a silicon-containing material.
  • the semiconductor substrate S 1 is a silicon-on-insulator (SOI) substrate or a silicon substrate.
  • SOI silicon-on-insulator
  • the semiconductor substrate S 1 may take the form of a planar substrate, a substrate with multiple fins, nanowires, or other forms known to people having ordinary skill in the art.
  • the semiconductor substrate S 1 may be a P-type substrate or an N-type substrate and may have doped regions therein.
  • the doped regions may be configured for an N-type device or a P-type device.
  • the semiconductor substrate S 1 includes isolation structures defining at least one active area, and at least one device is disposed on and/or in the active area.
  • the device includes a gate dielectric layer, a gate electrode, source/drain regions, spacers, and the like.
  • the through substrate vias (e.g., through silicon vias) TSV 1 penetrate through the semiconductor substrate S 1 .
  • the through substrate vias TSV 1 may include Cu, Ti, Ta, W, Ru, Co, Ni, the like, or a combination thereof.
  • a seed layer and/or a barrier layer may be disposed between each through substrate via TSV 1 and the semiconductor substrate S 1 .
  • the seed layer may include Ti/Cu.
  • the barrier layer may include Ta, TaN, Ti, TiN, CoW or a combination thereof.
  • the top portions of the through substrate vias TSV 1 extend into the interconnect structure IS 1 .
  • the interconnect structure IS 1 may be disposed over a first side (e.g., front side) of the semiconductor substrate S 1 . Specifically, the interconnect structure IS 1 may be disposed over and electrically connected to the device.
  • the interconnect structure IS 1 includes inter-metal dielectric layers IMD 1 and metal features embedded in the inter-metal dielectric layers IMD 1 .
  • the inter-metal dielectric layers IMD 1 may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (low-k) material having a dielectric constant less than 3.5, the like, or a combination thereof.
  • the metal features may include Al, Cu, Ti, Ta, W, Ru, Co, Ni, the like, or a combination thereof.
  • a seed layer and/or a barrier layer may be disposed between each metal feature and the corresponding inter-metal dielectric layer IMD 1 .
  • the seed layer may include Ti/Cu.
  • the barrier layer may include Ta, TaN, Ti, TiN, CoW or a combination thereof.
  • the metal features include upper pads UP 1 configured to bond the first die 100 to the desired components such as bumps, and lower pads LP 1 configured for the through substrate vias TSV 1 to land thereon.
  • the upper pads UP 1 and the lower pads LP 1 include different materials.
  • the upper pads UP 1 may include Al
  • the lower pads LP 1 may include Cu.
  • the upper pads UP 1 and the lower pads LP 1 may include the same material.
  • a bonding film BF 1 is optionally included in the first die 100 .
  • the bonding film BF 1 may be disposed over the first side (e.g., front side) of the semiconductor substrate S 1 .
  • the bonding film BF 1 may be disposed over the interconnect structure IS 1 .
  • the bonding film BF 1 includes silicon oxide, silicon nitride, the like, or a combination thereof.
  • a polymer such as benzocyclobutene (BCB), epoxy, an organic glue, or the like, is utilized as a bonding material of the bonding film BF 1 .
  • a carrier C 1 is provided.
  • the carrier C 1 has a bonding film BF C1 formed thereon.
  • the carrier C 1 is a glass substrate or a semiconductor substrate, and the bonding film BF C1 includes silicon oxide, silicon nitride, the like, or a combination thereof.
  • a polymer such as benzocyclobutene (BCB), epoxy, an organic glue, or the like, is utilized as a bonding material of the bonding film BF C1 .
  • the bonding film BF C1 of the carrier C 1 includes a material the same as that of the bonding film BF 1 of the first die 100 .
  • the bonding film BF C1 of the carrier C 1 and the bonding film BF 1 of the first die 100 may include different materials.
  • the first die 100 is bonded to the carrier C 1 at the first side (e.g., front side) of the first die 100 .
  • the first die 100 may be referred to as a tier-1 die in some examples.
  • the first die 100 is bonded to the carrier C 1 through a fusion bonding.
  • the bonding film BF 1 of the first die 100 is bonded to the bonding film BF C1 of the carrier C 1 .
  • the disclosure is not limited thereto, and another bonding technique, such as direct bonding, metal diffusion, anodic bonding, hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding, or the like, may be applied.
  • the semiconductor substrate S 1 is partially removed to expose portions (e.g., bottom portions) of the through substrate vias TSV 1 .
  • the partial removal operation includes performing an isotropic etching, such as a dry etching.
  • the etching gas includes a fluorine-containing gas, such as NF 3 , SF 6 , CF 4 , CHF 3 , CH 2 F 2 , the like or a combination thereof.
  • the interconnect structure IS 1 is wider than the remaining semiconductor substrate S 1 .
  • the partial removal operation not only removes the bottom portion of the semiconductor substrate S 1 to expose the bottom portions of the through substrate vias TSV 1 , but also removes the side portion of the semiconductor substrate S 1 to expose a portion of the inter-metal dielectric layer IMD 1 of the interconnect structure IS 1 .
  • the bonding film BF C1 of the carrier C 1 is partially removed during the operation of partially removing the semiconductor substrate S 1 . Accordingly, the remaining bonding film BF C1 is thicker in the central region while thinner in the edge region thereof.
  • a dielectric layer DL is formed over the top and the sidewall of the first die 100 and around the exposed portions (e.g., bottom portions) of the through substrate vias TSV 1 .
  • the dielectric layer DL further extends laterally away from the first die 100 and covers the exposed top surface of the bonding film BF C1 of the carrier C 1 .
  • the dielectric layer DL of the disclosure not only functions as a bonding film for bonding the first die 100 to the desired component such as a second die, but also functions as an isolation film for isolating the first die 100 from undesired components or materials.
  • the dielectric layer DL may include silicon oxide, silicon nitride, silicon oxynitride, a low-k material having a dielectric constant less than 3.5 (e.g., carbon doped oxide), the like, or a combination thereof.
  • the method of forming the dielectric layer DL includes the following operations.
  • a dielectric material layer is formed over the carrier C 1 covering the first die 100 through a suitable process such as chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD), although any suitable process may be utilized. Thereafter, a planarization process such as a chemical mechanical polishing (CMP) is performed to partially remove the dielectric material layer, until the surfaces (e.g., bottom surfaces) of the through substrate vias TSV 1 are exposed.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced CVD
  • CMP chemical mechanical polishing
  • the second die 200 may include one or more active components and/or passive components.
  • the second die 200 may include a logic die, a memory die, a CPU, a GPU, an xPU, a MEMS die, a SoC die, or the like.
  • the function of the second die 200 may be different from that of the first die 100 .
  • one of the first and second dies is a logic die, and the other of the first and second dies is a memory die.
  • the first and second dies may have similar function as needed.
  • the second die 200 may have a structure similar to that of the first die 100 , and the materials and configurations thereof may refer to those of the first die 100 .
  • the second die 200 includes a semiconductor substrate S 2 and an interconnect structure IS 2 .
  • the semiconductor substrate S 2 may be similar to the semiconductor substrate S 1 , so the material and configuration thereof may refer to those of the semiconductor substrate S 1 .
  • the semiconductor substrate S 2 may have through substrate vias such as through silicon vias as needed.
  • the semiconductor substrate S 2 includes isolation structures defining at least one active area, and at least one device is disposed on and/or in the active area.
  • the width of the semiconductor substrate S 2 is greater than the width of the semiconductor substrate S 1 , as shown in FIG. 1D .
  • the present disclosure is not limited thereto.
  • the semiconductor substrate S 2 is substantially as wide as the semiconductor substrate S 1 .
  • the width of the semiconductor substrate S 2 may be less than the width of the semiconductor substrate S 1 as needed.
  • the interconnect structure IS 2 may be similar to the interconnect structure IS 1 , so the material and configuration thereof may refer to those of the interconnect structure IS 1 .
  • the interconnect structure IS 2 may be disposed over a first side (e.g., front side) of the semiconductor substrate S 2 .
  • the interconnect structure IS 2 is disposed over and electrically connected to the device.
  • the interconnect structure IS 2 includes inter-metal dielectric layers IMD 2 and metal features embedded in the inter-metal dielectric layers IMD 2 .
  • the metal features include pads P 2 configured to bond the second die 200 to the through substrate vias TSV 1 of the first die 100 .
  • the interconnect structure IS 2 is substantially as wide as the interconnect structure IS 1 , as shown in FIG. 1D .
  • the present disclosure is not limited thereto.
  • the interconnect structure IS 2 and the interconnect structure IS 1 may have different widths.
  • the second die 200 is bonded to the first die 100 at a second side (e.g., back side) of the first die 100 .
  • the second die 200 may be referred to as a tier-2 die in some examples.
  • the second die 200 is bonded to the first die 100 through a hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding.
  • the pads P 2 of the second die 200 is bonded to the through substrate vias TSV 1 of the first die 100
  • the inter-metal dielectric layer IMD 2 is bonded to the dielectric layer DL over the first die 100 .
  • the disclosure is not limited thereto, and another bonding technique, such as direct bonding, metal diffusion, anodic bonding, fusion bonding, or the like, may be applied.
  • the second die 200 and the first die 100 are stacked in a face-to-back configuration, as shown in FIG. 1D .
  • the disclosure is not limited thereto, and another back-to-back configuration may be applied.
  • a dielectric encapsulation E is formed around the first die 100 and the second die 200 .
  • the dielectric encapsulation E may be referred to as a gap filling layer in some examples.
  • the dielectric encapsulation E includes a molding compound, a molding underfill, a resin or the like.
  • the dielectric encapsulation E includes a polymer material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), the like, or a combination thereof.
  • the dielectric encapsulation E includes silicon oxide, silicon nitride or a combination thereof.
  • the method of forming the dielectric encapsulation E includes the following operations.
  • An encapsulation material layer is formed over the carrier C 1 covering the first die 100 and second die 200 through a suitable process such as molding process or a deposition process, although any suitable process may be utilized.
  • a planarization process such as a chemical mechanical polishing (CMP) is performed to partially remove the encapsulation material layer, until the surface (e.g., bottom surface) of the semiconductor substrate S 2 is exposed.
  • CMP chemical mechanical polishing
  • a bonding film BF 2 is formed over the second die 200 and the dielectric encapsulation E.
  • the bonding film BF 2 includes silicon oxide, silicon nitride, the like, or a combination thereof.
  • a polymer such as benzocyclobutene (BCB), epoxy, an organic glue, or the like, is utilized as a bonding material of the bonding film BF 2 .
  • a second carrier C 2 is provided.
  • the carrier C 2 has a bonding film BF C2 formed thereon.
  • the carrier C 2 is a glass substrate or a semiconductor substrate, and the bonding film BF C2 includes silicon oxide, silicon nitride, the like, or a combination thereof.
  • the carrier C 2 may be referred to as a cover member in some examples.
  • a polymer such as benzocyclobutene (BCB), epoxy, an organic glue, or the like, is utilized as a bonding material of the bonding film BF C2 .
  • the bonding film BF C2 of the carrier C 2 includes a material the same as that of the bonding film BF 2 over the second die 200 .
  • the bonding film BF C2 of the carrier C 2 and the bonding film BF 2 over the second die 200 may include different materials.
  • the second carrier C 2 is bonded to the second die 200 .
  • the carrier C 2 is bonded to the second die 200 through a fusion bonding.
  • the bonding film BFc 2 of the carrier C 2 is bonded to the bonding film BF 2 of the second die 200 .
  • the disclosure is not limited thereto, and another bonding technique, such as direct bonding, metal diffusion, anodic bonding, hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding, or the like, may be applied.
  • the carrier C 1 is removed.
  • the bonding film BF 1 of the first die 100 and the bonding film BF C1 of the carrier C 1 are simultaneously removed.
  • an insulation layer IL is formed over the first side (e.g., front side) of the first die 100 .
  • the insulating layer IL may include silicon oxide or a suitable dielectric material and may be formed by a suitable deposition process.
  • a plurality of bumps B is formed at the first side (e.g., front side) of the first die 100 .
  • the bumps B are disposed over and electrically connected to the upper pads UP 1 of the interconnect structure IS 1 .
  • the bumps B include copper, solder, nickel or a combination thereof.
  • the bumps B may be solder balls, controlled collapse chip connection (C 4 ) bumps, ball grid array (BGA) balls, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, cupper pillar, hybrid bonding bumps, or the like.
  • C 4 controlled collapse chip connection
  • BGA ball grid array
  • EPIG electroless nickel-electroless palladium-immersion gold technique
  • the dielectric layer DL of the disclosure may be formed to have a multi-layer structure as needed.
  • an integrated circuit package 10 a of the disclosure is formed when the dielectric layer DL in FIG. 1C is formed to have a multi-layer structure including a lower dielectric layer LDL and an upper dielectric layer UDL, as shown in FIG. 2 .
  • the lower dielectric layer LDL and the upper dielectric layer UDL may include different materials and provide different functions.
  • each of the lower dielectric layer LDL and the upper dielectric layer UDL may include silicon oxide, silicon nitride, silicon oxynitride, a low-k material having a dielectric constant less than 3.5 (e.g., carbon doped oxide), the like, or a combination thereof.
  • the integrated circuit package has a first die bonded to a second die
  • a die stack including multiple first dies may be provided and then bonded to a second die.
  • the number of the second dies may be adjusted as needed.
  • FIG. 3A to FIG. 3F are cross-sectional views of a method of forming an integrated circuit package in accordance with some embodiments. It is understood that the disclosure is not limited by the method described below. Additional operations can be provided before, during, and/or after the method and some of the operations described below can be replaced or eliminated, for additional embodiments of the methods.
  • FIG. 3A to FIG. 3F are described in relation to a method, it is appreciated that the structures disclosed in FIG. 3A to FIG. 3F are not limited to such a method, but instead may stand alone as structures independent of the method.
  • a tier-1 first die 100 is bonded to a carrier C 1 at a first side (e.g., front side) of the tier-1 first die 100 .
  • the operation of FIG. 3A is similar to the operation of FIG. 1A , and the details are not iterated herein.
  • the semiconductor substrate S 1 of the tier-1 first die 100 is partially removed to expose portions of the through substrate vias TSV 1 , and a dielectric layer DL 1 is formed over the top and the sidewall of the tier-1 first die 100 and around the exposed portions of the through substrate vias TSV 1 .
  • the operation of FIG. 3B includes the operations similar to those described in FIG. 1B and FIG. 1C , and the details are not iterated herein.
  • the dielectric layer DL further extends laterally away from the tier-1 first die 100 and covers the exposed top surface of the bonding film BF C1 of the carrier C 1 .
  • the dielectric layer DL 1 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k material having a dielectric constant less than 3.5 (e.g., carbon doped oxide), the like, or a combination thereof.
  • a tier-2 first die 100 is bonded to the tier-1 first die 100 at a second side (e.g., back side) of the tier-1 first die 100 .
  • the tier-2 first die 100 is bonded to the tier-1 first die 100 through a hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding.
  • the upper pads UP 1 of the tier-2 first die 100 is bonded to the through substrate vias TSV 1 of the tier-1 first die 100
  • the inter-metal dielectric layer IMD 1 of the tier-2 first die 100 is bonded to the dielectric layer DL 1 over the tier-1 first die 100 .
  • the disclosure is not limited thereto, and another bonding technique, such as direct bonding, metal diffusion, anodic bonding, fusion bonding, or the like, may be applied.
  • the tier-2 first die 100 and the tier-1 first die 100 are stacked in a face-to-back configuration, as shown in FIG. 3C .
  • the disclosure is not limited thereto, and another back-to-back configuration may be applied.
  • the upper pads UP 1 and the lower pads LP 1 of the interconnect structure IS 1 of the tier-2 first die 100 may include the same material, such as Cu; however, the upper pads UP 1 and the lower pads LP 1 of the interconnect structure IS 1 of the tier-1 first die 100 may include the different materials, such as Al and Cu, respectively.
  • the semiconductor substrate S 1 of the tier-2 first die 100 is partially removed to expose portions of the through substrate vias TSV 1 , and a dielectric layer DL 2 is formed over the top and the sidewall of the tier-2 first die 100 and around the exposed portions of the through substrate vias TSV 1 .
  • the dielectric layer DL 2 further covers the dielectric layer DL 1 on the sidewall of the tier-1 first die 100 , and extends laterally away from the first dies 100 .
  • the dielectric layer DL 2 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k material having a dielectric constant less than 3.5 (e.g., carbon doped oxide), the like, or a combination thereof.
  • the dielectric layer DL 2 and the dielectric layer DL 1 include the same material and are formed by the same process, but the disclosure is not limited thereto. In alternative embodiments, the dielectric layer DL 2 and the dielectric layer DL 1 may include different materials as needed.
  • the tier-3 first die 100 is bonded to the tier-2 first die 100 through a hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding. Thereafter, the semiconductor substrate S 1 of the tier-3 first die 100 is partially removed to expose portions of the through substrate vias TSV 1 , and a dielectric layer DL 3 is formed over the top and the sidewall of the tier-3 first die 100 and around the exposed portions of the through substrate vias TSV 1 .
  • the operation of FIG. 3D includes the operations similar to those described in FIG. 3B and FIG. 3C .
  • the dielectric layer DL 3 further covers the dielectric layer DL 2 on the sidewalls of the tier-1 first die 100 and the tier-2 first die 100 , and extends laterally away from the first dies 100 .
  • the dielectric layer DL 3 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k material having a dielectric constant less than 3.5 (e.g., carbon doped oxide), the like, or a combination thereof.
  • the dielectric layer DL 3 and the dielectric layer DL 2 include the same material and are formed by the same process, but the disclosure is not limited thereto. In alternative embodiments, the dielectric layer DL 3 and the dielectric layer DL 2 may include different materials as needed.
  • the tier-4 first die 100 is bonded to the tier-3 first die 100 through a hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding. Thereafter, the semiconductor substrate S 1 of the tier-4 first die 100 is partially removed to expose portions of the through substrate vias TSV 1 , and a dielectric layer DL 4 is formed over the top and the sidewall of the tier-4 first die 100 and around the exposed portions of the through substrate vias TSV 1 .
  • the operation of FIG. 3E includes the operations similar to those described in FIG. 3B and FIG. 3C .
  • the dielectric layer DL 4 further covers the dielectric layer DL 3 on the sidewalls of the tier-1 first die 100 , the tier-2 first die 100 and the tier-3 first die 100 , and extends laterally away from the first dies 100 .
  • the dielectric layer DL 4 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k material having a dielectric constant less than 3.5 (e.g., carbon doped oxide), the like, or a combination thereof.
  • the dielectric layer DL 4 and the dielectric layer DL 3 include the same material and are formed by the same process, but the disclosure is not limited thereto.
  • the dielectric layer DL 4 and the dielectric layer DL 3 may include different materials as needed.
  • the dielectric layers DL 1 to DL 4 constitute a dielectric layer DL.
  • the dielectric layer DL of the disclosure not only functions as a bonding film for bonding the die 100 to the desired component such as another die or a redistribution layer structure, but also functions as an isolation film for isolating the first die 100 from undesired components or materials.
  • the operations described in FIG. 3B and FIG. 3C are performed three times, and a die stack including tier-1 to tier-4 first dies 100 is accordingly formed.
  • the operations described in FIG. 3B and FIG. 3C may be repeated as many times as needed, until the desired number of the first dies 100 is vertically stacked.
  • a second die 200 is bonded to the topmost first die 100 (e.g., tier-4 first die 100 ) of the die stack at a second side (e.g., back side) of the topmost first die 100 .
  • a dielectric encapsulation E is formed around the tier-1 to tier-4 first dies 100 .
  • a bonding film BF 2 is formed over the second die 200 and the dielectric encapsulation E.
  • a second carrier C 2 is then bonded to the second die 200 .
  • the carrier C 1 is removed.
  • a portion of the dielectric layer DL (e.g., the portion of the dielectric layer DL 1 on the carrier C 1 ) is simultaneously removed during the removal of the carrier C 1 .
  • an insulation layer IL is formed over the first side (e.g., front side) of the lowermost first die 100 (e.g., tier-1 first die 100 ).
  • a plurality of bumps B is formed at the first side (e.g., front side) of the lowermost first die 100 (e.g., tier-1 first die 100 ).
  • the operation of FIG. 3F includes the operations similar to those described in FIG. 1D to FIG. 1G , and the details are not iterated herein. An integrated circuit package 10 b of the disclosure is thus completed.
  • FIG. 1G The structures of the disclosure are illustrated below with reference to FIG. 1G , FIG. 2 and FIG. 3F .
  • an integrated circuit package 10 / 10 a / 10 b includes at least one first die 100 , a plurality of bumps B, a second die 200 and a dielectric layer DL.
  • the bumps B are electrically connected to the at least one first die 100 at a first side (e.g., front side) of the at least one first die 100 .
  • the second die 200 is electrically connected to the at least one first die 100 at a second side (e.g., second side) of the at least one first die 100 .
  • the (topmost) first die 100 and the second die 200 are bonded through a hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding.
  • the second side is opposite to the first side of the at least one first die 100 .
  • the first die 100 includes a semiconductor substrate S 1 and an interconnect structure IS 1 , and the interconnect structure IS 1 is wider than the semiconductor substrate S 1 .
  • the second die 200 includes a semiconductor substrate S 2 and an interconnect structure IS 2 , and the interconnect structure IS 2 is substantially as wide as the semiconductor substrate S 2 .
  • the semiconductor substrate S 2 is wider than the semiconductor substrate S 1 .
  • the width of the semiconductor substrate S 2 may be equal to or less than the width of the semiconductor substrate S 1 as needed.
  • the dielectric layer DL of the disclosure is disposed between the at least one first die 100 and the second die 200 and covers the sidewall of the at least one first die 100 .
  • the dielectric layer DL surrounds portions of through substrate vias TSV 1 of the at least one first die 100 .
  • the surface of the dielectric layer DL is substantially coplanar with the surfaces of the through substrate vias TSV 1 .
  • the dielectric layer DL is a single layer. In some embodiments, as shown in FIG. 2 and FIG. 3F , the dielectric layer DL has a multi-layer structure.
  • the dielectric layer DL has a stepped sidewall with multiple turning points. In some embodiments, the dielectric layer DL has a one-step profile, as shown in FIG. 1G and FIG. 2 . In some embodiments, the dielectric layer DL has a multi-step profile, as shown in FIG. 3F . In some embodiments, the dielectric layer DL further extends laterally away from the first dies 100 , as shown in FIG. 3F .
  • the at least one first die 100 includes a plurality of first dies 100 vertically stacked.
  • two adjacent first dies 100 are bonded through a hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding.
  • the dielectric layer DL on the sidewall of the first die 100 (e.g., tier-1 first die 100 ) away from the second die 200 is thicker than the dielectric layer DL on the sidewall of the first die (e.g., tier-4 first die 100 ) close to the second die 200 .
  • the dielectric layer DL is further disposed between two adjacent first dies 100 .
  • the integrated circuit package 10 / 10 a / 10 b further includes a dielectric encapsulation E disposed around the at least one first die 100 and the second die 200 , and a carrier C 2 disposed over and bonded to the second die 200 .
  • the dielectric encapsulation E is separated from the at least one first die 100 by the dielectric layer DL.
  • the dielectric layer of the disclosure is disposed between the adjacent dies and covers the entire sidewalls of the dies.
  • the lateral portion of each dielectric layer over the corresponding die serves as a bonding film for bonding the die to the desired components, and the stepped sidewall portion of the same serves as an isolation film for isolating the die from undesired components or materials.
  • the method of the disclosure is simple and compatible with the existing processes.
  • FIG. 4A to FIG. 4D are cross-sectional views of a method of forming an integrated circuit package in accordance with alternative embodiments. It is understood that the disclosure is not limited by the method described below. Additional operations can be provided before, during, and/or after the method and some of the operations described below can be replaced or eliminated, for additional embodiments of the methods.
  • FIG. 4A to FIG. 4D are described in relation to a method, it is appreciated that the structures disclosed in FIG. 4A to FIG. 4D are not limited to such a method, but instead may stand alone as structures independent of the method.
  • the first die 101 may include one or more active components and/or passive components.
  • the first die 101 may include a logic die, a memory die, a CPU, a GPU, an xPU, a MEMS die, a SoC die, or the like.
  • the first die 101 may be similar to the first die 100 , and the materials and configurations thereof may refer to those of the first die 100 .
  • the first die 101 includes a semiconductor substrate S, a plurality of through substrate vias TSV and an interconnect structure IS.
  • the semiconductor substrate S may be similar to the semiconductor substrate S 1 , so the material and configuration thereof may refer to those of the semiconductor substrate S 1 .
  • the semiconductor substrate S includes isolation structures defining at least one active area, and at least one device is disposed on and/or in the active area.
  • the through substrate vias TSV may be similar to the through substrate vias TSV 1 , so the material and configuration thereof may refer to those of the through substrate vias TSV 1 .
  • the through substrate vias (e.g., through silicon vias) TSV penetrate through the semiconductor substrate S.
  • the top portions of the through substrate vias TSV extend into the interconnect structure IS.
  • the interconnect structure IS may be similar to the interconnect structure IS 1 , so the material and configuration thereof may refer to those of the interconnect structure IS 1 .
  • the interconnect structure IS may be disposed over a first side (e.g., front side) of the semiconductor substrate S. Specifically, the interconnect structure IS may be disposed over and electrically connected to the device.
  • the interconnect structure IS includes inter-metal dielectric layers IMD and metal features embedded in the inter-metal dielectric layers IMD.
  • the metal features include upper pads UP configured to bond the first die 101 to the desired component such as an integrated circuit structure, and lower pads LP configured for the through substrate vias TSV to land thereon.
  • the upper pads UP and the lower pads LP include the same material.
  • the upper pads UP and the lower pads LP may include Cu.
  • the upper pads UP and the lower pads LP may include different materials.
  • the integrated circuit structure IC may include one or more functional devices such as active components and/or passive components.
  • the integrated circuit structure IC may include a logic die, a memory die, a CPU, a GPU, an xPU, a MEMS die, a SoC die, or the like.
  • the function of the integrated circuit structure IC may be different from that of the first die 101 .
  • one of the first die 101 and the integrated circuit structure IC is a logic die
  • the other of the first die 101 and the integrated circuit structure IC is a memory die.
  • the first die 101 and the integrated circuit structure IC may have similar function as needed.
  • the integrated circuit structure IC has a dimension greater than that of the first die 101 , as shown in FIG. 4A .
  • the dimension may be a height, a width, a size, a top-view area or a combination thereof.
  • the present disclosure is not limited thereto.
  • the integrated circuit structure IC may have a dimension substantially the same as that of the first die 101 .
  • the integrated circuit structure IC is a single die structure.
  • the integrated circuit structure IC may be referred to as a bottom wafer in some examples.
  • the integrated circuit structure IC includes a semiconductor substrate Si, an interconnect structure ISi and a bonding structure BSi.
  • the semiconductor substrate Si may be similar to the semiconductor substrate S, the material and configuration thereof may refer to those of the semiconductor substrate S.
  • the interconnect structure ISi may be disposed over a first side (e.g., front side) of the semiconductor substrate S. Specifically, the interconnect structure IS may be disposed over and electrically connected to the device on and/or in the semiconductor substrate S.
  • the interconnect structure ISi includes inter-metal dielectric layers and metal features embedded in the inter-metal dielectric layers.
  • the bonding structure BSi may be disposed over the first side (e.g., front side) of the semiconductor substrate Si. Specifically, the bonding structure BSi may be disposed over and electrically connected to the interconnect structure ISi.
  • the bonding structure BSi includes at least one bonding film BFi and bonding metal features embedded in the bonding dielectric layer BFi.
  • the bonding film BFi includes silicon oxide, silicon nitride, a polymer or a combination thereof.
  • the bonding metal features include bonding pads BPi electrically connected to the first die 101 .
  • the bonding metal features may include Cu, Ti, Ta, W, Ru, Co, Ni, a combination thereof or the like.
  • a seed layer and/or a barrier layer may be disposed between each bonding metal feature and the bonding film BFi.
  • the seed layer may include Ti/Cu.
  • the barrier layer may include Ta, TaN, Ti, TiN, CoW or a combination thereof.
  • the first die 101 is bonded to the integrated circuit structure IS at the first side (e.g., front side) of the first die 101 .
  • the first die 101 is bonded to the integrated circuit structure IC through a hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding.
  • the upper pads UP of the first die 101 is bonded to the bonding pads BPi of the integrated circuit structure IC, and the inter-metal dielectric layer IMD of the first die 101 is bonded to the bonding film BFi of the integrated circuit structure IC.
  • the disclosure is not limited thereto, and another bonding technique, such as direct bonding, metal diffusion, anodic bonding, fusion bonding, or the like, may be applied.
  • the first die 101 and the integrated circuit structure IC are stacked in a face-to-face configuration, as shown in FIG. 4A .
  • the disclosure is not limited thereto, and another face-to-back configuration may be applied.
  • the semiconductor substrate S of the first die 101 is partially removed to expose portions (e.g., bottom portions) of the through substrate vias TSV.
  • the partial removal operation includes performing an isotropic etching, such as a dry etching.
  • the etching gas includes a fluorine-containing gas, such as NF 3 , SF 6 , CF 4 , CHF 3 , CH 2 F 2 , the like or a combination thereof.
  • the interconnect structure IS is wider than the remaining semiconductor substrate S.
  • the partial removal operation not only removes the bottom portion of the semiconductor substrate S to expose the bottom portions of the through substrate vias TSV, but also removes the side portion of the semiconductor substrate S to expose a portion of the inter-metal dielectric layer IMD of the interconnect structure IS.
  • the bonding film BFi of the integrated circuit structure IC is partially removed during the operation of partially removing the semiconductor substrate S. Accordingly, the remaining bonding film BFi is thicker in the central region while thinner in the edge region thereof.
  • a dielectric layer DL is formed over the top and the sidewall of the first die 101 and around the exposed portions (e.g., bottom portions) of the through substrate vias TSV.
  • the dielectric layer DL further extends laterally away from the first die 101 and covers the exposed top surface of the bonding film BFi of the integrated circuit structure IC.
  • the dielectric layer DL of the disclosure not only functions as a bonding film for bonding the first die 101 to the desired component such as a redistribution layer structure, but also functions as an isolation film for isolating the first die 101 from undesired components or materials.
  • the dielectric layer DL may include silicon oxide, silicon nitride, silicon oxynitride, a low-k material having a dielectric constant less than 3.5 (e.g., carbon doped oxide), the like, or a combination thereof.
  • the method of forming the dielectric layer DL includes the following operations.
  • a dielectric material layer is formed over the integrated circuit structure IC covering the first die 100 through a suitable process such as chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD), although any suitable process may be utilized. Thereafter, a planarization process such as a chemical mechanical polishing (CMP) is performed to partially remove the dielectric material layer, until the surfaces (e.g., bottom surfaces) of the through substrate vias TSV 1 are exposed.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced CVD
  • CMP chemical mechanical polishing
  • an dielectric encapsulation E is formed around the first die 101 and over the integrated circuit structure IC.
  • the dielectric encapsulation E is separated from the first die 100 or the integrated circuit structure by the dielectric layer DL.
  • a redistribution layer structure RDL is formed over the first die 101 and the dielectric encapsulation E.
  • the redistribution layer structure RDL is formed over the second side (e.g., back side) of the first die 100 .
  • the redistribution layer structure RDL may be referred to as a back-side redistribution layer structure in some examples.
  • the redistribution layer structure RDL includes at least one polymer layer PL and conductive features embedded by the polymer layer PL.
  • the conductive features include upper metal pads UMP configured to electrically connect to the desired components such as bumps, and lower metal pads LMP configured to electrically connect to the through substrate vias TSV of the first die 101 .
  • the polymer layer PL may include a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like.
  • the polymer layer of the redistribution layer structure RDL may be replaced by a dielectric layer or an insulating layer as needed.
  • the lower metal pads LMP and the upper metal pads UMP may include Cu, Ti, Ta, W, Ru, Co, Ni, a combination thereof or the like.
  • a seed layer and/or a barrier layer may be disposed between each metal pad and the polymer layer PM.
  • the seed layer may include Ti/Cu.
  • the barrier layer may include Ta, TaN, Ti, TiN, CoW or a combination thereof.
  • bumps B are formed to electrically connect to the redistribution layer structure RDL.
  • the bumps B are electrically connected to the first die 101 at a second side (e.g., back side) of the first die 101 .
  • An integrated circuit structure 20 of the disclosure is thus completed.
  • the dielectric layer DL of the disclosure may be formed to have a multi-layer structure as needed.
  • an integrated circuit package 20 a of the disclosure is formed when the dielectric layer DL in FIG. 4C is formed to have a multi-layer structure including a lower dielectric layer LDL and an upper dielectric layer UDL, as shown in FIG. 5 .
  • the lower dielectric layer LDL and the upper dielectric layer UDL may include different materials and provide different functions.
  • each of the lower dielectric layer LDL and the upper dielectric layer UDL may include silicon oxide, silicon nitride, silicon oxynitride, a low-k material having a dielectric constant less than 3.5 (e.g., carbon doped oxide), the like, or a combination thereof.
  • the integrated circuit package has a first die bonded to an integrated circuit structure are provided for illustration purposes, and are not construed as limiting the present disclosure.
  • a die stack including multiple first dies may be provided and then bonded to an integrated circuit structure.
  • the number of dies included in the integrated circuit structure may be adjusted as needed.
  • the operations described in FIG. 4B and FIG. 4C are performed two times, and a die stack including tier-1 to tier-2 first dies 101 is accordingly formed.
  • the operations described in FIG. 4B and FIG. 4C may be repeated as many times as needed, until the desired number of the first dies 101 is vertically stacked.
  • a redistribution layer structure RDL is formed over the second side (e.g., back side) of the topmost first die 101 (e.g., tier-2 first die 101 ), and bumps B are formed to electrically connect to the redistribution layer structure RDL.
  • An integrated circuit structure 20 b of the disclosure is thus completed.
  • FIG. 4D The structures of the disclosure are illustrated below with reference to FIG. 4D , FIG. 5 and FIG. 6 .
  • an integrated circuit package 20 / 20 a / 20 b includes at least one first die 101 , an integrated circuit structure IC, a dielectric layer DL and a plurality of bumps B.
  • the at least one first die 101 is bonded to the integrated circuit structure IC at a first side (e.g., front side) of the at least one first die 101 .
  • the (lowermost) first die 101 and the integrated circuit structure IC are bonded through a hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding.
  • the dielectric layer DL covers the top and the sidewall of the at least one first die 101 .
  • the bumps B are electrically connected to the (topmost) first die 101 at a second side (e.g., back side) of the first die 101 . The second side is opposite to the first side of the at least one first die 101 .
  • the first die 101 includes a semiconductor substrate S and an interconnect structure IS, and the interconnect structure IS is wider than the semiconductor substrate S.
  • the integrated circuit structure IC includes a semiconductor substrate Si and an interconnect structure ISi, and the interconnect structure ISi is substantially as wide as the semiconductor substrate Si.
  • the semiconductor substrate Si is wider than the semiconductor substrate S.
  • the integrated circuit package 20 / 20 a / 20 b further includes a redistribution layer RDL between the second side (e.g., back side) of the topmost first die 101 and the bumps B.
  • the dielectric layer DL of the disclosure is disposed between the topmost first die 101 and the redistribution layer structure RDL and covers the sidewall of the at least one first die 100 .
  • the dielectric layer DL surrounds portions of through substrate vias TSV of the at least one first die 101 .
  • the surface of the dielectric layer DL is substantially coplanar with the surfaces of the through substrate vias TSV.
  • the dielectric layer DL is a single layer. In some embodiments, as shown in FIG. 5 and FIG. 6 , the dielectric layer DL has a multi-layer structure.
  • the dielectric layer DL has a stepped sidewall with multiple turning points. In some embodiments, the dielectric layer DL has a one-step profile, as shown in FIG. 4D and FIG. 5 . In some embodiments, the dielectric layer DL has a multi-step profile, as shown in FIG. 6 . In some embodiments, the dielectric layer DL further extends laterally away from the first dies 101 , as shown in FIG. 4D , FIG. 5 and FIG. 6 .
  • the at least one first die 101 includes a plurality of first dies 101 vertically stacked.
  • two adjacent first dies 101 are bonded through a hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding.
  • the dielectric layer DL on the sidewall of the first die 101 (e.g., tier-1 first die 101 ) close to the integrated circuit structure IC is thicker than the dielectric layer DL on the sidewall of the first die (e.g., tier-2 first die 101 ) away from the integrated circuit structure IC.
  • the dielectric layer DL is further disposed between two adjacent first dies 101 .
  • the integrated circuit package 20 / 20 a / 20 b further includes a dielectric encapsulation E disposed around the at least one first die 101 and over the integrated circuit structure IC.
  • the dielectric encapsulation E is separated from the at least one first die 101 by the dielectric layer DL.
  • the dielectric layer of the disclosure is disposed between the adjacent dies and between the topmost die and the redistribution layer structure, and covers the entire sidewalls of the dies.
  • each dielectric layer over the corresponding die serves as an isolation film for isolating the die from undesired components or materials.
  • the method of the disclosure is simple and compatible with the existing processes.
  • an integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer.
  • the bumps are electrically connected to the at least one first die at a first side of the at least one first die.
  • the second die is electrically connected to the at least one first die at a second side of the at least one first die.
  • the second side is opposite to the first side of the at least one first die.
  • the dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.
  • an integrated circuit package includes at least one first die, an integrated circuit structure, a dielectric layer and a plurality of bumps.
  • the at least one first die is bonded to the integrated circuit structure at a first side of the at least one first die.
  • the dielectric layer covers a top and a sidewall of the at least one first die.
  • the bumps are electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die.
  • a method of forming an integrated circuit package includes the following operations. At least one first die is bonded to a first carrier at a first side of the at least one first die, and the first die includes a first semiconductor substrate, a plurality of first through substrate vias penetrating through the first semiconductor substrate and a first interconnect structure over the first substrate. The first semiconductor substrate is partially removed to expose portions of the first through substrate vias. A dielectric layer is formed over a top and a sidewall of the at least one first die and around the exposed portions of the first through substrate vias. A second die is bonded to the at least one first die at a second side of the at least one first die.
  • testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices.
  • the testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like.
  • the verification testing may be performed on intermediate structures as well as the final structure.
  • the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

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US20230343753A1 (en) 2023-10-26
US20200395338A1 (en) 2020-12-17

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