CN114695272A - 集成电路封装件的形成方法 - Google Patents

集成电路封装件的形成方法 Download PDF

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Publication number
CN114695272A
CN114695272A CN202210348276.3A CN202210348276A CN114695272A CN 114695272 A CN114695272 A CN 114695272A CN 202210348276 A CN202210348276 A CN 202210348276A CN 114695272 A CN114695272 A CN 114695272A
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China
Prior art keywords
insulating layer
integrated circuit
layer
forming
circuit die
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CN202210348276.3A
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English (en)
Inventor
吴逸文
郭宏瑞
何明哲
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US15/946,885 external-priority patent/US10872885B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN114695272A publication Critical patent/CN114695272A/zh
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Abstract

本发明的实施例提供了集成电路封装件的形成方法。该方法包括：在载体上形成第一绝缘层；在所述第一绝缘层上方形成第一再分布层(RDL)；在所述第一绝缘层和所述第一再分布层上方形成第二绝缘层；在所述第二绝缘层上方形成第二再分布层；将集成电路管芯的第一面附接到所述第二绝缘层；在所述集成电路管芯上方和周围形成第三绝缘层；在所述第三绝缘层中同时形成导电通孔和第三再分布层；以及去除所述载体以暴露所述第一绝缘层。

Description

集成电路封装件的形成方法
分案申请
本申请是2018年06月28日提交的标题为“集成电路封装件及其形成方法”、专利申请号为201810688666.9的分案申请。
技术领域
本发明实施例总体涉及半导体领域，更具体地，涉及集成电路封装件的形成方法。
背景技术
半导体器件用于诸如个人电脑、手机、数码相机和其他电子设备的各种电子应用中。通常通过在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体材料层以及使用光刻图案化各个材料层以在各个材料层上形成电路组件和元件来制造半导体器件。通常，在单个半导体晶圆上制造数十或数百个的集成电路。通过沿着划线锯切集成电路来切割单独的管芯。之后，通常以多芯片模式或以其他的封装类型来单独地封装单个管芯。
由于各个电组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进，半导体工业已经经历了快速增长。对于大部分而言，这种集成密度的改进来自于最小部件尺寸的连续减小(例如，将半导体工艺节点缩小至小于20nm节点)，这允许更多的组件集成到给定的区域。随着近来对小型化、更高的速度和更大的带宽以及更低功耗和延迟时间的的需求的增长，对于半导体管芯的更小且更具创造性的封装技术的需求也已增长。
随着半导体技术的进一步发展，已经出现了作为有效替代的堆叠半导体器件(例如，三维集成电路(3DIC))，以进一步减小半导体器件的物理尺寸。在堆叠半导体器件中，在不同的半导体晶圆上制造诸如逻辑电路、存储器电路、处理器电路等的有源电路。两个或多个半导体晶圆可以安装或堆叠在彼此的顶部上以进一步减小半导体器件的形状因数。叠层封装(POP)器件是一种类型的3DIC，其中，封装管芯并且之后将管芯与另一封装的管芯或多个管芯封装在一起。封装件上芯片(CoP)器件是另一种类型的3DIC，其中，封装管芯并且之后将管芯与另一管芯或多个管芯封装在一起。
发明内容
根据本发明的一些实施例，提供了一种形成集成电路封装件的方法，包括：将集成电路管芯的第一侧附接至载体；在所述集成电路管芯上方和周围形成密封剂；图案化所述密封剂以形成与所述集成电路管芯横向间隔开的第一开口以及在所述集成电路管芯上方的第二开口，所述第一开口延伸穿过所述密封剂，所述第二开口暴露所述集成电路管芯的第二侧，所述集成电路管芯的第一侧与所述集成电路管芯的第二侧相对；以及在所述第一开口和所述第二开口中同时沉积导电材料。
根据本发明的另一些实施例，还提供了一种形成集成电路封装件的方法，包括：将集成电路管芯的第一侧附接至载体，所述集成电路管芯的第二侧具有接触焊盘，所述集成电路管芯的第一侧与所述集成电路管芯的第二侧相对；在所述集成电路管芯上方和周围形成密封剂；以及在所述密封剂中同时形成导电通孔和第一再分布层(RDL)，所述导电通孔与所述集成电路管芯的侧壁横向间隔开，所述导电通孔的顶面位于所述密封剂的最上表面之下，所述第一再分布层位于所述集成电路管芯的第二侧上方，所述第一再分布层与所述接触焊盘电接触。
根据本发明的又一些实施例，还提供了一种集成电路封装件结构，包括：集成电路管芯；密封剂，沿着所述集成电路管芯的侧壁和最上表面延伸；导电通孔，位于所述密封剂中，所述导电通孔与所述集成电路管芯的侧壁间隔开；以及绝缘层，位于所述导电通孔上方，其中，所述导电通孔包括：第一部分，沿着所述绝缘层的底面延伸；以及第二部分，沿着所述绝缘层的侧壁延伸，所述第一部分的高度大于所述第二部分的宽度。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图8是根据一些实施例的集成电路管芯的制造期间的各个工艺步骤的截面图。
图9至图16是根据一些实施例的集成电路封装件的制造期间的各个工艺步骤的截面图。
图17和图18是根据一些实施例的集成电路封装件的制造期间的各个工艺步骤的截面图。
图19和图20是根据一些实施例的集成电路封装件的制造期间的各个工艺步骤的截面图。
图21是根据一些实施例的示出形成集成电路封装件的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
将参照特定上下文中的实施例来描述实施例，即诸如集成扇出(InFO)封装件和包括InFO封装件的PoP封装件的集成电路封装件。然而，其他实施例也可以应用于其他电连接的组件，包括但不限于，叠层封装组件、管芯至管芯组件、晶圆至晶圆组件、管芯至衬底组件、组装中封装、处理中衬底、中介层、衬底等或者安装输入组件、板、管芯或其他组件或用于连接封装或安装的任何类型的集成电路或电子部件的组合。本文描述的各个实施例允许在同一处理步骤中形成集成电路封装件的密封剂通孔和再分布线，这允许减少用于形成集成电路封装件的工艺步骤的数量并且减小制造成本。
图1至图8是根据一些实施例的在集成电路管芯的制造期间的各个工艺步骤的截面图。参照图1，示出了由划线103(也称为切割线或切割区)分隔开的具有管芯区域101的工件100的部分。如下面更详细地描述的，工件100将沿着划线103切割以形成单独的集成电路管芯(诸如图8中示出的集成电路管芯801)。在一些实施例中，工件100包括衬底105、位于衬底105上的一个或多个有源和/或无源器件107以及位于衬底105和一个或多个有源和/或无源器件107上方的一个或多个金属化层109。在一些实施例中，衬底105可以由硅形成，但是也可以由诸如硅、锗、镓、砷以及它们的组合的其他III族、IV族和/或V族元素形成。衬底105也可以是绝缘体上硅(SOI)的形式。SOI衬底可以包括形成在绝缘层(例如，埋氧层等)(形成在硅衬底上)上方的半导体材料(例如，硅、锗等)层。此外，可以使用包括多层衬底、梯度衬底、混合取向衬底、它们的任何组合等的其他衬底。
在一些实施例中，一个或多个有源和/或无源器件107可以包括诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等的各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)器件。
一个或多个金属化层109可以包括形成在衬底105和一个或多个有源和/或无源器件107上方的层间介电层(ILD)/金属间介电层(IMD)。可以通过诸如旋涂方法、化学汽相沉积(CVD)、等离子体增强CVD(PECVD)等或它们的组合的本领域内已知的任何合适的方法由诸如磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等的低K介电材料形成ILD/IMD。在一些实施例中，可以使用例如镶嵌工艺、双镶嵌工艺、它们的组合等在ILD/IMD中形成互连结构。在一些实施例中，互连结构可以包括铜、铜合金、银、金、钨、钽、铝等。在一些实施例中，互连结构可以提供形成在衬底105上的一个或多个有源和/或无源器件107之间的电连接。
在一些实施例中，在一个或多个金属化层109上方形成接触焊盘111。接触焊盘111可以通过一个或多个金属化层109电连接至一个或多个有源和/或无源器件107。在一些实施例中，接触焊盘111可以包括导电材料，诸如铝、铜、钨、银、金等或它们的组合。在一些实施例中，例如，可以使用物理汽相沉积(PVD)、原子层沉积(ALD)、电化学镀、化学镀等或它们的组合在一个或多个金属化层109上方形成导电材料。随后，图案化导电材料以形成接触焊盘111。在一些实施例中，可以使用光刻技术图案化导电材料。通常，光刻技术涉及沉积光刻胶材料(未示出)，随后辐照(曝光)和显影光刻胶材料以去除光刻胶材料的部分。剩余的光刻胶材料保护下面的材料(诸如接触焊盘111的导电材料)免受随后的诸如蚀刻的工艺步骤的影响。可以将诸如反应离子蚀刻(RIE)或其他干蚀刻、各向同性或各向异性的湿蚀刻或任何其他合适的蚀刻或图案化工艺的合适的蚀刻工艺应用于导电材料，以去除导电材料的暴露部分并且形成接触焊盘111。在导电材料为铝的一些实施例中，可以使用例如80％磷酸、5％硝酸、5％乙酸和10％去离子水(DI)的混合物蚀刻导电材料。随后，可以使用例如灰化工艺和随后的湿清洗工艺去除光刻胶材料。
进一步参照图1，在衬底105和接触焊盘111上方形成钝化层113。在一些实施例中，钝化层113可以包括诸如氮化硅、氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂磷硅酸盐玻璃(BPSG)、它们的组合等的一层或多层非可光图案化介电材料，并且可以使用化学汽相沉积(CVD)、PVD、ALD、旋涂工艺、它们的组合等形成。在其他实施例中，钝化层113可以包括诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、它们的组合等的一层或多层可光图案化绝缘材料，并且可以使用旋涂工艺等形成。可以使用与光刻胶材料类似的光刻方法图案化这种可光图案化介电材料。
随后，在钝化层113中形成开口115以暴露部分接触焊盘111。在钝化层113包括非可光图案化介电材料的一些实施例中，可以使用合适的光刻和蚀刻方法图案化钝化层113。在一些实施例中，在钝化层113上方形成光刻胶材料(未示出)。随后，辐照(曝光)和显影光刻胶材料以去除光刻胶材料的部分。随后，使用例如合适的蚀刻工艺去除钝化层113的暴露部分以形成开口115。在一些实施例中，使用例如氢氟酸缓冲液(HF)蚀刻由氧化硅形成的钝化层113。在其他实施例中，使用例如热磷酸(H3PO4)蚀刻由氮化硅形成的钝化层113。
参照图2，在钝化层113和接触焊盘111上方形成缓冲层201。在一些实施例中，缓冲层201可以包括诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、它们的组合等的一层或多层可光图案化绝缘材料，并且可以使用旋涂工艺等形成。在一些实施例中，图案化缓冲层201以形成开口203并且暴露接触焊盘111。在一些实施例中，可以使用合适的光刻技术将缓冲层201暴露于光来形成开口203。在曝光之后，显影和/或固化缓冲层201。
参照图3，在缓冲层201上方和在开口203中毯式沉积晶种层301。晶种层301可以包括铜、钛、镍、金、锰、它们的组合等的一层或多层，并且可以通过ALD、PVD、溅射或它们的组合等形成。在一些实施例中，晶种层301包括形成在钛层上方的铜层。
参照图4，在晶种层301上方形成图案化掩模401。在一些实施例中，图案化掩模401可以包括光刻胶材料或任何可光图案化材料。在一些实施例中，沉积、辐照(曝光)和显影图案化掩模401的材料以去除材料的部分并且形成开口403，从而形成图案化掩模401。在示出的实施例中，开口403暴露晶种层301的形成在开口203中的接触焊盘111上方的部分。如下面更详细的讨论的，导电柱(诸如图5中示出的导电柱501)将形成在开口403中以提供至接触焊盘111的电连接。
参照图5，在由开口403和203形成的组合开口(见图4)中形成导电柱501。在一些实施例中，使用电化学镀工艺、化学镀工艺、ALD、PVD、它们的组合等，利用诸如铜、钨、铝、银、金、它们的组合等的导电材料填充组合开口来形成导电柱501。在一些实施例中，导电柱501部分地填充组合开口，并且用焊料材料填充组合开口的剩余部分以在相应导电柱501上方形成焊料层503。在一些实施例中，合适的焊料材料可以是诸如PbSn组分的铅基焊料、包括InSb、锡、银和铜(“SAC”)组分的无铅焊料、以及具有共同熔点并且在电子应用中形成导电焊料连接件的其他共晶材料。例如，对于无铅焊料，可以使用不同组分的SAC焊料，诸如SAC105(Sn 98.5％、Ag 1.0％、Cu 0.5％)、SAC 305和SAC 405。无铅焊料也包括不使用银(Ag)的SnCu化合物和不使用铜(Cu)的SnAg化合物。在一些实施例中，可以使用蒸发、电化学电镀工艺、化学镀工艺、印刷、焊料转印、它们的组合等形成焊料层503。
参照图6，在形成导电柱501和焊料层503之后，去除图案化掩模401(见图5)。在一些实施例中，使用例如灰化工艺和随后的湿清洗工艺去除包括光刻胶材料的图案化掩模401。随后，使用例如合适的蚀刻工艺去除晶种层301的暴露部分。在晶种层301包括形成在钛层上方的铜层的一些实施例中，可以使用例如FeCl3、HCl和H2O的混合物(用于蚀刻铜)以及H2O2、HF和H2O的混合物(用于蚀刻钛)来蚀刻晶种层301。
参照图7，在导电柱501和对应的焊料层503上方并且围绕导电柱501和对应的焊料层503形成保护层701。在一些实施例中，保护层701可以包括诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、它们的组合等的一层或多层可光图案化绝缘材料，并且可使用旋涂工艺等形成。在一些实施例中，在形成保护层701之前，可以测试每个管芯区域101以识别已知良好管芯(KGD)，从而用于进一步处理。
进一步参照图7，在一些实施例中，期望回研磨衬底105，例如以减小工件100的厚度和随后形成的集成电路管芯的厚度。在这种实施例中，实施减薄工艺，其中，将诸如回研磨(BG)带的带703施加至保护层701的顶面，并且通过研磨、蚀刻、CMP工艺、它们的组合等减薄衬底105的背侧。在一些实施例中，带703保护工件100免受由研磨流体和/或碎屑引起的污染。
参照图8，在一些实施例中，在完成上述减薄工艺之后，去除带703并且使用CMP工艺、研磨工艺、蚀刻工艺、它们的组合等平坦化保护层701。在一些实施例中，实施平坦化工艺直至暴露导电柱501。在一些实施例中，平坦化工艺也可以去除导电柱501上方的焊料层503(见图7)。在一些实施例中，导电柱501的顶面与保护层701的顶面基本共面。
进一步参照图8，在一些实施例中，在完成上述平坦化工艺之后，分割工件100以形成单独的管芯801。在一些实施例中，可以使用粘合剂805将工件100附接至框架803以准备用于随后的切割工艺的工件100。在一些实施例中，框架803可以是膜框架或任何合适的载体，以为随后的操作(诸如，切割)提供机械支撑。粘合剂805可以是管芯附接膜、切割膜或任何合适的粘合剂、环氧树脂、紫外(UV)胶(当暴露于UV辐射时失去其粘合性)等，并且可以使用沉积工艺、旋涂、印刷工艺、层压工艺等形成。在一些实施例中，粘合剂805可以具有多层结构并且可以包括释放层(未示出)。在完成切割工艺之后，释放层可以帮助安全地从框架803去除单独的管芯801。在一些实施例中，释放层可以是UV型，其中，当将释放层暴露于UV辐射之后，释放层的粘合强度显著降低。在其他实施例中，释放层可以是热型，其中，当将释放层暴露于合适的热源之后，释放层的粘合强度显著降低。在一些实施例中，可以例如通过锯切、激光烧蚀、它们的组合等将工件100分割成单独的管芯801。
如图8所示，每个集成电路管芯801均包括单个钝化层(诸如钝化层113)、单个缓冲层(诸如缓冲层201)、两个接触焊盘(诸如接触焊盘111)、两个导电柱(诸如导电柱501)以及单个保护层(诸如保护层701)。本领域技术人员将意识到，提供的钝化层、缓冲层、接触焊盘、导电柱和保护层的数量仅用于说明的目的，并且不限制本发明的范围。在其他实施例中，取决于集成电路管芯801的设计要求，每个集成电路管芯801均可以包括适当的数量的钝化层、缓冲层、接触焊盘、导电柱和保护层。
图9至图16是根据一些实施例的使用图1至图8中制造的集成电路管芯801的集成电路封装件的制造期间的各个工艺步骤的截面图。首先参照图9，在一些实施例中，在载体901上方形成释放层903，并且在释放层903上方形成绝缘层905以开始形成集成电路封装件。在一些实施例中，载体901可以由石英、玻璃等形成，并且为随后的操作提供机械支持。在一些实施例中，释放层903可以包括光热转换(LTHC)材料、UV粘合剂、聚合物层等，并且可以使用旋涂工艺、印刷工艺、层压工艺等形成。在释放层903由LTHC材料形成的一些实施例中，当暴露于光时，释放层903部分地或完全地失去其粘合强度，并且可以从随后形成的结构的背侧容易地去除载体901。在一些实施例中，可以使用与以上参照图2描述的缓冲层201类似的材料和方法来形成绝缘层905，并且为了简洁起见，此处不再重复描述。
进一步参照图9，使用粘合层907将集成电路管芯801附接至绝缘层905。在一些实施例中，使用例如拾取和放置装置将集成电路管芯801放置在绝缘层905上。在其他实施例中，手动或使用任何其他合适的方法将集成电路管芯801放置绝缘层905上。在一些实施例中，粘合层907可以包括LTHC材料、UV粘合剂、管芯附接膜等，并且可以使用旋涂工艺、印刷工艺、层压工艺等形成。
参照图10，在绝缘层905上方以及在集成电路管芯801上方并且围绕集成电路管芯801形成密封剂1001。在一些实施例中，密封剂1001可以包括诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、它们的组合等的一层或多层可光图案化绝缘材料，并且可使用旋涂工艺等形成。在一些实施例中，图案化密封剂1001以在密封剂1001中形成开口1003和1005。在一些实施例中，可以使用合适的光刻技术将密封剂1001暴露于光来形成开口1003和1005。在曝光之后，显影和/或固化密封剂1001。在一些实施例中，开口1003穿过密封剂1001延伸并且暴露绝缘层905。在一些实施例中，开口1005暴露集成电路管芯801的导电柱501。如下面更详细地描述的，在开口1003中形成密封剂通孔，并且在开口1005中形成再分布层通孔(见图13)。
参照图11，在密封剂1001上方以及在开口1003和开口1005中形成晶种层1101。在一些实施例中，可以使用与以上参照图3描述的晶种层301类似的材料和方法来形成晶种层1101，并且为了简洁起见，此处不再重复描述。在一些实施例中，晶种层1101可以具有介于约
Figure BDA0003577836130000101
和约1μm之间的厚度。在一些实施例中，晶种层1101可以包括形成在钛层上方的铜层。在一些实施例中，钛层可以具有介于约
Figure BDA0003577836130000102
和约
Figure BDA0003577836130000103
之间的厚度。在一些实施例中，铜层可以具有介于约
Figure BDA0003577836130000104
和约
Figure BDA0003577836130000105
之间的厚度。
参照图12，在密封剂1001上方形成其中具有开口的图案化掩模1201。在一些实施例中，可以使用与以上参照图4描述的图案化掩模401类似的材料和方法来形成图案化掩模1201，并且为了简洁起见，此处不再重复描述。随后，穿过图案化掩模1201中的开口沉积导电材料1203。在一些实施例中，导电材料1203可以包括铜、钨、铝、银、金、它们的组合等，并且可以使用电化学镀工艺、化学镀工艺、ALD、PVD、它们的组合等形成。在一些实施例中，导电材料1203可以完全地填充开口1005(见图11)。在一些实施例中，导电材料1203可以部分地填充开口1003。在一些实施例中，导电材料1203以非共形的方式形成在开口1003中，从而使得导电材料1203的设置在开口1003的底部上的厚度T1大于导电材料1203的设置在开口1003的侧壁上的厚度T2。在一些实施例中，厚度T2介于约2μm和约10μm之间。在一些实施例中，厚度T1介于约12μm和约60μm之间。在一些实施例中，开口1003的未填充部分的底部可以在集成电路管芯801的最上表面之下。在一些实施例中，开口1003的未填充部分的底部可以在集成电路管芯801的最上表面之上。在一些实施例中，开口1003的未填充部分的底部可以与集成电路管芯801的最上表面基本齐平。
参照图13，在形成导电材料1203之后，去除图案化掩模1201(见图12)。在一些实施例中，可以使用与以上参照图6描述的图案化掩模401类似的方法去除图案化掩模1201，并且为了简洁起见，此处不再重复描述。随后，去除晶种层1101的暴露部分。在一些实施例中，晶种层1101的暴露部分可以使用与以上参照图6描述的晶种层301的暴露部分类似的方法去除，并且为了简洁起见，此处不再重复描述。在一些实施例中，晶种层1101和导电材料1203的设置在集成电路管芯801的最上表面之下的开口1003中的部分可以称为导电通孔1301或密封剂导电通孔1301。在一些实施例中，晶种层1101和导电材料1203的位于集成电路管芯801的最上表面之上的部分可以称为再分布层(RDL)1303。通过在同一工艺步骤中形成导电通孔1301和RDL 1303，减少了用于形成产生的封装件的工艺步骤的数量并且减小了制造成本。如下面更详细地描述的，连接件(诸如图16中示出的连接件1603)形成为与导电通孔1301的底面接触。在导电材料1203共形地形成在开口1003的一些实施例中，导电材料1203在开口1003的底部处的厚度可能小于期望的厚度，从而使得设置在开口1003的底部上的整个导电材料1203可以由形成在导电通孔1301和连接件之间的界面处的金属间化合物(IMC)耗尽，这可能增加在导电通孔1301和连接件之间的界面处形成裂缝的可能性。另一方面，通过用导电材料1203完全地填充开口1003以在开口1003的底部处实现期望的厚度，导电材料1203的沉积时间(诸如例如镀时间)可能比期望的更大，这可能增加生产成本并且降低每小时晶圆(WPH)产率。如上所述，通过非共形地形成导电通孔1301以在开口1003的底部具有厚度T1，导电材料1203可以不由形成在导电通孔1301和连接件之间的界面处的IMC耗尽，并且可以减少导电材料1203的沉积时间。因此，可以减少或消除在导电通孔1301和连接件之间的界面处形成裂缝的可能性，可以减小生产成本并且可以增加WPH产率。
参照图14，在集成电路管芯801和密封剂1001上方形成再分布结构1401。在一些实施例中，RDL 1303可以是再分布结构1401的第一RDL层。在一些实施例中，再分布结构1401还可以包括绝缘层14031至14033，以及设置在绝缘层14031至14033内的RDL 14051和14052(包括导线和通孔)。在一些实施例中，绝缘层14031至14033可以使用与以上参照图2描述的缓冲层201类似的材料和方法形成，并且为了简洁起见，此处不再重复描述。在一些实施例中，RDL 14051和14052可以使用与以上参照图13描述的RDL 1303类似的材料和方法形成，并且为了简洁起见，此处不再重复描述。
进一步参照图14，在一些实施例中，用于形成再分布结构1401的工艺步骤可以包括图案化绝缘层14031以使用与例如以上参照图2描述的缓冲层201类似的方法在其中形成开口，并且为了简洁起见，此处不再重复描述。在绝缘层14031上方以及绝缘层14031中的开口中形成RDL 14051以接触RDL 1303。RDL 14051可以包括各个线/迹线(“水平地”延伸横跨绝缘层14031的顶面)和/或通孔(“垂直地”延伸至绝缘层14031内)。在一些实施例中，在绝缘层14031上方和绝缘层14031内的开口中沉积晶种层(未示出)。晶种层可以使用与以上参照图3描述的晶种层301类似的材料和方法形成，并且为了简洁起见，此处不再重复描述。随后，在晶种层上方沉积图案化掩模(未示出)以限定用于RDL 14051的期望的图案。在一些实施例中，其中具有开口的图案化掩模可以使用与以上参照图4描述的图案化掩模401类似的材料和方法形成，并且为了简洁起见，此处不再重复描述。在一些实施例中，通过电化学电镀工艺、化学镀工艺、ALD、PVD、它们的组合等在晶种层上形成导电材料。随后，去除图案化掩模，并且在去除图案化掩模之后，也去除暴露的晶种层的部分。在一些实施例中，图案化掩模可以使用与以上参照图6描述的图案化掩模401类似的方法去除，并且为了简洁起见，此处不再重复描述。在一些实施例中，晶种层的暴露部分可以使用与以上参照图6描述的晶种层301的暴露部分类似的方法去除，并且为了简洁起见，此处不再重复描述。
进一步参照图14，在绝缘层14031和RDL 14051上方形成绝缘层14032、RDL 14052和绝缘层14033，这完成了再分布结构1401的形成。在一些实施例中，可以使用与RDL 14051类似的方法在绝缘层14032上方形成RDL 14052，并且为了简洁起见，此处不再重复描述。在一些实施例中，RDL 14052穿过绝缘层14032延伸并且接触RDL 14051的部分。
如图14所示，再分布结构1401包括三个RDL(诸如RDL 1303、14051和14052)。本领域技术人员将意识到，提供的RDL的数量仅用于说明的目的，并且不限制本发明的范围。在其他实施例中，取决于产生的封装器件的设计要求，再分布结构1401可以包括适当数量的RDL。
进一步参照图14，在再分布结构1401上方形成电连接至再分布结构1401的凸块下金属(UBM)1407。在一些实施例中，可以穿过绝缘层14033形成一组开口以暴露RDL14052的部分。在一些实施例中，UBM 1407可以包括多个导电材料层，诸如钛层、铜层和镍层。然而，本领域技术人员将意识到，存在适合于形成UBM 1407的材料和层的许多合适的布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于UBM 1407的任何合适的材料或材料层均完全旨在包括在本申请的范围内。在一些实施例中，在一些UBM1407上方形成电连接至一些UBM 1407的连接件1409。在一些实施例中，连接件1409可以是焊料球、可控塌陷芯片连接(C4)凸块、球栅阵列(BGA)球、微凸块、化学镀镍化学镀钯浸金技术(ENEPIG)形成的凸块等。在连接件1409由焊料材料形成的一些实施例中，可以实施回流工艺以将材料成形为期望的凸块形状。在其他实施例中，连接件1409可以是可以使用与以上参照图5描述的导电柱501类似的材料和方法形成的导电柱，并且为了简洁起见，此处不再重复描述。在连接件1409包括导电柱的一些实施例中，连接件1409还可以包括可以形成在导电柱的顶部上的覆盖层。在一些实施例中，覆盖层可以包括焊料、镍、锡、锡铅、金、银、钯、铟、镍钯金、镍金等、它们的组合等，并且可以使用电化学镀工艺、化学镀工艺等形成。
进一步参照图14，将集成电路管芯1411安装在再分布结构1401上方并且电连接至再分布结构1401。在一些实施例中，使用连接件1413将集成电路管芯1411附接至UBM 1407。在一些实施例中，连接件1413可以使用与连接件1409类似的材料和方法形成，并且为了简洁起见，此处不再重复描述。在一些实施例中，集成电路管芯1411可以是离散的半导体器件芯片，诸如表面安装器件(SMD)、集成无源器件(IPD)等。
参照图15，在再分布结构1401上方形成连接件1409并且将集成电路管芯1411附接至再分布结构1401之后，将产生的结构附接至由框架1503支撑的带1501，从而使得连接件1409接触带1501。在一些实施例中，带1501可以包括管芯附接膜、切割带等。随后，将载体901(见图14)从产生的结构分离以暴露绝缘层905。随后，可以切割产生的结构以形成单独的集成电路封装件1500。在一些实施例中，可以通过锯切、激光烧蚀方法、它们的组合等切割产生的结构。随后，可以测试每个集成电路封装件1500以识别已知良好封装件(KGP)，从而用于进一步处理。
参照图16，在一些实施例中，通过穿过绝缘层905中的开口延伸的一组连接件1603将工件1601接合至集成电路封装件1500，以形成堆叠半导体器件1600。在一些实施例中，可以使用例如激光烧蚀方法形成绝缘层905中的开口。在绝缘层905由可光图案化材料形成的一些实施例中，可以使用光刻方法形成开口。在一些实施例中，工件1601可以是封装件、一个或多个管芯、印刷电路板(PCB)、封装衬底、中介层等。在工件1601是封装件的一些实施例中，堆叠半导体器件1600是叠层封装(PoP)器件。在工件1601是管芯的其他实施例中，堆叠半导体器件1600是封装件上芯片(CoP)器件。在一些实施例中，连接件1603可以使用与以上参照图14描述的连接件1409类似的材料和方法形成，并且为了简洁起见，此处不再重复描述。在其他实施例中，可以在以上参照图15描述的切割工艺之前将工件1601接合至集成电路封装件1500。
进一步参照图16，底部填充物1605可以注入或以其他方式形成在工件1601和集成电路封装件1500之间的间隔中并且围绕连接件1603。底部填充物1605可以例如是分配在结构之间的液体环氧树脂、可变形凝胶、硅橡胶等，并且之后固化以硬化。该底部填充物1605可以用于减少对连接件1603的损坏并且保护连接件1603。在一些实施例中，底部填充物1605和密封剂1001可以包括相同的材料。在其他实施例中，底部填充物1605和密封剂1001可以包括不同的材料。
参照图17，在一些实施例中，在如以上参照图15描述的分离载体901之后并且在切割过程之前，在绝缘层905上方形成再分布结构1701。在一些实施例中，绝缘层905可以是再分布结构1701的第一绝缘层。在示出的实施例中，再分布结构1701还包括绝缘层17031和17032以及RDL 17051和17052。在一些实施例中，绝缘层17031和17032可以使用与以上参照图2描述的缓冲层201类似的材料和方法形成，并且为了简洁起见，此处不再重复描述。在一些实施例中，RDL 17051和17052可以使用与以上参照图13描述的RDL 1303类似的材料和方法形成，并且为了简洁起见，此处不再重复描述。在一些实施例中，再分布结构1701可以使用与以上参照图14描述的再分布结构1401类似的方法形成，并且为了简洁起见，此处不再重复描述。本领域技术人员将意识到，提供的RDL和绝缘层的数量仅用于说明的目的，并且不限制本发明的范围。在其他实施例中，取决于产生的封装器件的设计要求，再分布结构1701可以包括适当数量的RDL和绝缘层。
进一步参照图17，在一些实施例中，在形成再分布结构1701之后，将产生的结构附接至由框架1503支撑的带1501，从而使得连接件1409接触带1501。随后，可以切割产生的结构以形成单独的集成电路封装件1700。在一些实施例中，可以通过锯切、激光烧蚀方法、它们的组合等切割产生的结构。随后，可以测试每个集成电路封装件1700以识别已知良好封装件(KGP)，从而用于进一步处理。
参照图18，在一些实施例中，通过穿过绝缘层17032中的开口延伸的一组连接件1603将工件1601接合至集成电路封装件1700，以形成堆叠半导体器件1800。在一些实施例中，堆叠半导体器件1800与堆叠半导体器件1600类似，其中，相同的元件使用相同的参考标号标记。在一些实施例中，堆叠半导体器件1800可以使用与以上参照图16描述的堆叠半导体器件1600类似的方法形成，并且为了简洁起见，此处不再重复描述。
参照图19，在一些实施例中，在如以上参照图9描述的在载体901上方形成绝缘层905之后并且在附接集成电路管芯801之前，在载体901上方形成再分布结构1901。在一些实施例中，在形成再分布结构1901之后，可以实施以上参照图9至图14描述的工艺步骤以形成图19中示出的结构。在一些实施例中，绝缘层905可以是再分布结构1901的第一绝缘层。在示出的实施例中，再分布结构1901还包括绝缘层19031和19032以及RDL 19051和19052。在一些实施例中，绝缘层19031和19032可以使用与以上参照图2描述的缓冲层201类似的材料和方法形成，并且为了简洁起见，此处不再重复描述。在一些实施例中，RDL 19051和19052可以使用与以上参照图13描述的RDL 1303类似的材料和方法形成，并且为了简洁起见，此处不再重复描述。在一些实施例中，再分布结构1901可以使用与以上参照图14描述的再分布结构1401类似的方法形成，并且为了简洁起见，此处不再重复描述。本领域技术人员将意识到，提供的RDL和绝缘层的数量仅用于说明的目的，并且不限制本发明的范围。在其他实施例中，取决于产生的封装器件的设计要求，再分布结构1901可以包括适当数量的RDL和绝缘层。随后，可以切割产生的结构以形成单独的集成电路封装件1900。在一些实施例中，可以通过锯切、激光烧蚀方法、它们的组合等切割产生的结构。随后，可以测试每个集成电路封装1900以识别已知良好封装件(KGP)，从而用于进一步处理。
参照图20，在一些实施例中，通过穿过绝缘层905中的开口延伸的一组连接件1603将工件1601接合至集成电路封装件1900，以形成堆叠半导体器件2000。在一些实施例中，堆叠半导体器件2000与堆叠半导体器件1600类似，其中，相同的元件使用相同的参考标号标记。在一些实施例中，堆叠半导体器件2000可以使用与以上参照图16描述的堆叠半导体器件1600类似的方法形成，并且为了简洁起见，此处不再重复描述。
图21是根据一些实施例的示出形成集成电路封装件的方法2100的流程图。在一些实施例中，方法2100从步骤2103开始，其中，将集成电路管芯(诸如图9中示出的集成电路管芯801)附接在载体(诸如图9中示出的载体901)上方，如以上参照图9描述的。在步骤2105中，如以上参照图10描述的，在集成电路管芯上方和周围形成密封剂(诸如图10中示出的密封剂1001)。在步骤2107中，如以上参照图10描述的，图案化密封剂以形成穿过密封剂延伸的第一开口(诸如图10中示出的开口1003)和暴露集成电路管芯的部分的第二开口(诸如图10中示出的开口1005)。在步骤2109中，如以上参照图12描述的，在第一开口和第二开口中同时沉积导电材料(诸如图12中示出的导电材料1203)。在步骤2111中，如以上参照图15描述的，去除载体。在可选实施例中，在实施步骤2103之前，实施步骤2101，其中，如以上参照图19描述的，在载体上方形成再分布结构(诸如图19中示出的再分布结构1901)。在其他可选实施例中，在实施步骤2111之后，实施步骤2113，其中，形成再分布结构(诸如图17中示出的再分布结构1701)，如以上参照图17描述的。
根据实施例，方法包括：将集成电路管芯的第一侧附接至载体；在集成电路管芯上方和周围形成密封剂；图案化密封剂以形成与集成电路管芯横向间隔开的第一开口以及在集成电路管芯上方的第二开口，第一开口延伸穿过密封剂，第二开口暴露集成电路管芯的第二侧，集成电路管芯的第一侧与集成电路管芯的第二侧相对；以及在第一开口和第二开口中同时沉积导电材料。在实施例中，该方法还包括在将集成电路管芯附接至载体之前，在载体上方形成再分布结构。在实施例中，该方法还包括从集成电路管芯的第一侧去除载体；以及在集成电路管芯的第一侧上方形成再分布结构。在实施例中，导电材料部分地填充第一开口。在实施例中，导电材料在第一开口的底部上方的厚度大于导电材料沿着第一开口的侧壁的厚度。在实施例中，导电材料过填充第二开口。在实施例中，该方法还包括：在第一开口和第二开口中同时沉积导电材料之后，在第一开口中沉积绝缘材料，绝缘材料过填充第一开口。
根据另一实施例，方法包括：将集成电路管芯的第一侧附接至载体，集成电路管芯的第二侧具有接触焊盘，集成电路管芯的第一侧与集成电路管芯的第二侧相对；在集成电路管芯上方和周围形成密封剂；以及在密封剂中同时形成导电通孔和第一再分布层(RDL)，导电通孔与集成电路管芯的侧壁横向间隔开，导电通孔的顶面位于密封剂的最上表面之下，第一RDL位于集成电路管芯的第二侧上方，第一RDL与接触焊盘电接触。在实施例中，该方法还包括在将集成电路管芯附接至载体之前，在载体上方形成第二RDL。在实施例中，该方法还包括将载体从集成电路管芯的第一侧分离；以及在集成电路管芯的第一侧上方形成第二RDL。在实施例中，在密封剂中同时形成导电通孔和第一RDL包括图案化密封剂以在密封剂中形成第一开口和第二开口，第一开口穿过密封剂延伸，第二开口暴露集成电路管芯的第二侧；在第一开口和第二开口中同时非共形地沉积导电材料。在实施例中，导电材料在第一开口的底部上方的厚度大于导电材料沿着第一开口的侧壁的厚度。在实施例中，导电材料在第一开口的底部上方的厚度小于集成电路管芯的高度。在实施例中，密封剂包括可光图案化绝缘材料。
根据又另一实施例，结构包括：集成电路管芯；密封剂，沿着集成电路管芯的侧壁和最上表面延伸；位于密封剂中的导电通孔，导电通孔与集成电路管芯的侧壁间隔开；以及位于导电通孔上方的绝缘层。在实施例中，导电通孔包括沿着绝缘层的底面延伸的第一部分；以及沿着绝缘层的侧壁延伸的第二部分，第一部分的高度大于第二部分的宽度。在实施例中，该结构还包括位于密封剂的最上表面上方的再分布层，再分布层的至少部分延伸至密封剂内并且接触导电通孔。在实施例中，导电通孔的最下表面与密封剂的最下表面基本齐平。在实施例中，绝缘层的至少部分位于密封剂的最上表面之下。在实施例中，导电通孔和绝缘层之间的界面位于集成电路管芯的最上表面之下。在实施例中，密封剂包括可光图案化绝缘材料。
也可以包括其他部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘以允许测试3D封装件或3DIC，并且允许使用探针和/或探针卡等。验证测试可以对中间结构以及最终结构实施。此外，本文公开的结构和方法可以与接合已知良好管芯的中间验证的测试方法结合以增加产量和降低成本。
根据本发明的一些实施例，提供了一种形成集成电路封装件的方法，包括：将集成电路管芯的第一侧附接至载体；在所述集成电路管芯上方和周围形成密封剂；图案化所述密封剂以形成与所述集成电路管芯横向间隔开的第一开口以及在所述集成电路管芯上方的第二开口，所述第一开口延伸穿过所述密封剂，所述第二开口暴露所述集成电路管芯的第二侧，所述集成电路管芯的第一侧与所述集成电路管芯的第二侧相对；以及在所述第一开口和所述第二开口中同时沉积导电材料。
在上述方法中，还包括，在将所述集成电路管芯附接至所述载体之前，在所述载体上方形成再分布结构。
在上述方法中，还包括：从所述集成电路管芯的第一侧去除所述载体；以及在所述集成电路管芯的第一侧上方形成再分布结构。
在上述方法中，所述导电材料部分地填充所述第一开口。
在上述方法中，所述导电材料在所述第一开口的底部上方的厚度大于所述导电材料沿着所述第一开口的侧壁的厚度。
在上述方法中，所述导电材料过填充所述第二开口。
在上述方法中，还包括，在所述第一开口和所述第二开口中同时沉积所述导电材料之后，在所述第一开口中沉积绝缘材料，所述绝缘材料过填充所述第一开口。
根据本发明的另一些实施例，还提供了一种形成集成电路封装件的方法，包括：将集成电路管芯的第一侧附接至载体，所述集成电路管芯的第二侧具有接触焊盘，所述集成电路管芯的第一侧与所述集成电路管芯的第二侧相对；在所述集成电路管芯上方和周围形成密封剂；以及在所述密封剂中同时形成导电通孔和第一再分布层(RDL)，所述导电通孔与所述集成电路管芯的侧壁横向间隔开，所述导电通孔的顶面位于所述密封剂的最上表面之下，所述第一再分布层位于所述集成电路管芯的第二侧上方，所述第一再分布层与所述接触焊盘电接触。
在上述方法中，还包括，在将所述集成电路管芯附接至所述载体之前，在所述载体上方形成第二再分布层。
在上述方法中，还包括：将所述载体从所述集成电路管芯的第一侧分离；以及在所述集成电路管芯的第一侧上方形成第二再分布层。
在上述方法中，在所述密封剂中同时形成所述导电通孔和所述第一再分布层包括：图案化所述密封剂以在所述密封剂中形成第一开口和第二开口，所述第一开口延伸穿过所述密封剂，所述第二开口暴露所述集成电路管芯的第二侧；以及在所述第一开口和所述第二开口中同时非共形地沉积导电材料。
在上述方法中，所述导电材料在所述第一开口的底部上方的厚度大于所述导电材料沿着所述第一开口的侧壁的厚度。
在上述方法中，所述导电材料在所述第一开口的底部上方的厚度小于所述集成电路管芯的高度。
在上述方法中，所述密封剂包括可光图案化绝缘材料。
根据本发明的又一些实施例，还提供了一种集成电路封装件结构，包括：集成电路管芯；密封剂，沿着所述集成电路管芯的侧壁和最上表面延伸；导电通孔，位于所述密封剂中，所述导电通孔与所述集成电路管芯的侧壁间隔开；以及绝缘层，位于所述导电通孔上方，其中，所述导电通孔包括：第一部分，沿着所述绝缘层的底面延伸；以及第二部分，沿着所述绝缘层的侧壁延伸，所述第一部分的高度大于所述第二部分的宽度。
在上述集成电路封装件结构中，还包括位于所述密封剂的最上表面上方的再分布层，所述再分布层的至少部分延伸至所述密封剂内并且接触所述导电通孔。
在上述集成电路封装件结构中，所述导电通孔的最下表面与所述密封剂的最下表面齐平。
在上述集成电路封装件结构中，所述绝缘层的至少部分位于所述密封剂的最上表面之下。
在上述集成电路封装件结构中，所述导电通孔和所述绝缘层之间的界面位于所述集成电路管芯的最上表面之下。
在上述集成电路封装件结构中，所述密封剂包括可光图案化绝缘材料。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成集成电路封装件的方法，包括：
在载体上形成第一绝缘层；
在所述第一绝缘层上方形成第一再分布层(RDL)；
在所述第一绝缘层和所述第一再分布层上方形成第二绝缘层；
在所述第二绝缘层上方形成第二再分布层，所述第二再分布层的最上表面在所述第二绝缘层的最上表面之上，所述第二再分布层的部分延伸穿过所述第二绝缘层并且物理接触所述第一再分布层；
将集成电路管芯的第一面附接到所述第二绝缘层，所述集成电路管芯的第二面具有连接件件，所述集成电路管芯的第一面与所述集成电路管芯的第二面相对；
在将所述集成电路管芯的第一面附接到所述第二绝缘层之后，在所述集成电路管芯上方和周围形成第三绝缘层，所述第三绝缘层与所述第二再分布层的最上表面和所述第二绝缘层的最上表面物理接触；
在所述第三绝缘层中同时形成导电通孔和第三再分布层，所述导电通孔的侧壁面对所述集成电路管芯的侧壁，所述导电通孔的顶面低于所述第三绝缘层的最上表面，所述第三再分布层与连接件物理接触，其中在所述第三绝缘层中同时形成所述导电通孔和所述第三再分布层包括：
图案化所述第三绝缘层以在所述第三绝缘层中形成第一凹槽和第二凹槽，所述第一凹槽延伸穿过所述第三绝缘层并且暴露出所述第二再分布层的最上表面，所述第二凹槽暴露出所述连接件的最上表面；
在所述第三绝缘层上方形成图案化掩模，所述图案化掩模暴露出所述第一凹槽和所述第二凹槽；和
通过所述图案化掩模掩模在所述第一凹槽和所述第二凹槽中同时非共形地沉积导电材料；以及
去除所述载体以暴露所述第一绝缘层。
2.根据权利要求1所述的方法，其中，所述导电材料在所述第一凹槽的底部上方的厚度大于所述导电材料沿所述第一凹槽的侧壁的厚度。
3.根据权利要求1所述的方法，其中，所述第三绝缘层包括可光刻图案化的绝缘材料。
4.根据权利要求1所述的方法，其中，在所述第三绝缘层中同时形成所述导电通孔和所述第三再分布层还包括：在通过所述图案化掩模在所述第一凹槽和所述第二凹槽中同时非共形地沉积所述导电材料之后去除图案掩模。
5.一种形成集成电路封装件的方法，包括：
在载体上形成第一绝缘层；
在所述第一绝缘层上方形成第一再分布层(RDL)；
在所述第一绝缘层和所述第一再分布层上方形成第二绝缘层；
在所述第二绝缘层上方形成第二再分布层，所述第二再分布层的第一部分沿所述第二绝缘层的最上表面延伸，所述第二再分布层的第二部分延伸穿过所述第二绝缘层并且物理接触所述第一再分布层；
将集成电路管芯的第一面附接到所述第二绝缘层的最上表面，所述集成电路管芯具有与所述第一面相对的第二面；
在将所述集成电路管芯的第一面附接到所述第二绝缘层的最上表面之后，将所述集成电路管芯封装在第三绝缘层中，所述第三绝缘层与所述第二再分布层的第一部分的侧壁和最上表面物理接触；
在所述第三绝缘层中形成第一凹槽和第二凹槽，所述第一凹槽暴露出所述第二重分布层的第一部分，所述第二凹槽暴露出所述集成电路管芯的第二面；同时在所述第一凹槽和所述第二凹槽中沉积第一导电材料；以及
从所述第一绝缘层处去除所述载体。
6.根据权利要求5所述的方法，还包括：
在所述第一导电材料上方形成图案化掩模，所述图案化掩模暴露出所述第一导电材料在所述第一凹槽中的第一部分和所述第一导电材料在所述第二凹槽中的第二部分；以及
通过所述图案化掩模同时在所述第一凹槽和所述第二凹槽中非共形地沉积第二导电材料。
7.一种形成集成电路封装件的方法，包括：
在载体上方沉积第一绝缘层；
在所述第一绝缘层上方形成第一再分布层(RDL)；
在所述第一绝缘层和所述第一再分布层上方沉积第二绝缘层；
在所述第二绝缘层上方形成第二再分布层，所述第二再分布层的第一部分与所述第二绝缘层的最上表面物理接触，所述第二再分布层的第二部分延伸穿过所述第二绝缘层并且物理接触所述第一再分布层；
将集成电路管芯的第一面附接到第二绝缘层，所述集成电路管芯的第二面具有连接件，所述集成电路管芯的第二面背离所述第二绝缘层；
在将所述集成电路管芯的第一面附着到所述第二绝缘层之后，在所述第二绝缘层上沉积第三绝缘层并且与所述第二绝缘层物理接触，所述第三绝缘层沿着所述集成电路管芯的侧壁延伸且覆盖所述连接件；
同时在所述第三绝缘层中形成导电通孔和第三再分布层，所述导电通孔延伸穿过所述第三绝缘层并且物理接触所述第二再分布层的第一部分，所述第三再分布层的部分延伸到所述第三绝缘层中并且物理接触所述连接件，其中，同时形成所述导电通孔和所述第三再分布层包括：
图案化所述第三绝缘层以在所述第三绝缘层中形成第一凹槽和第二凹槽，所述第一凹槽暴露出所述第二再分布层的第一部分，所述第二凹槽暴露出所述连接件的最上表面；
在所述第一凹槽和所述第二凹槽中沉积第一导电材料；
在所述第一导电材料上方形成图案化掩模，所述图案化掩模暴露所述第一导电材料在所述第一凹槽中的第一部分和所述第一导电材料在所述第二凹槽中的第二部分；和
通过所述图案化掩模，在所述第一凹槽和所述第二凹槽中同时非共形地沉积第二导电材料，所述第二导电材料不同于所述第一导电材料：以及
将所述载体与所述第一绝缘层分离。
8.根据权利要求7所述的方法，还包括：
在所述导电通孔和所述第三再分布层上方沉积第四绝缘层，所述第四绝缘层的最底表面低于所述连接件的最顶表面；以及
在所述第四绝缘层上方形成第四再分布层，所述第四再分布层的部分延伸到所述第四绝缘层中并且物理接触所述第三再分布层。
9.根据权利要求8所述的方法，还包括：将表面贴装器件电连接到所述第四再分布层。
10.根据权利要求7所述的方法，其中，所述第二导电材料部分地填充所述第一凹槽并且过填充所述第二凹槽。
CN202210348276.3A 2017-06-30 2018-06-28 集成电路封装件的形成方法 Pending CN114695272A (zh)

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