CN112652608A - 多芯片封装件及其制造方法 - Google Patents

多芯片封装件及其制造方法 Download PDF

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Publication number
CN112652608A
CN112652608A CN202011061287.0A CN202011061287A CN112652608A CN 112652608 A CN112652608 A CN 112652608A CN 202011061287 A CN202011061287 A CN 202011061287A CN 112652608 A CN112652608 A CN 112652608A
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interposer
chip
chip package
connection conductors
semiconductor chips
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CN202011061287.0A
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Inventor
林昂樱
林育民
黄馨仪
吴昇财
罗元听
倪梓瑄
陈昭蓉
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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Priority claimed from TW109131057A external-priority patent/TWI775145B/zh
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Publication of CN112652608A publication Critical patent/CN112652608A/zh
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Abstract

本发明公开一种多芯片封装件及其制造方法。多芯片封装件包括：中介层，包括布线结构与电连接至布线结构的中介通路；多个半导体芯片，位于中介层的第一表面上且经由中介层而彼此电连接；包封体，位于中介层的第一表面上且包封多个半导体芯片的至少部分；以及重配置线路结构，位于中介层的与第一表面相对的第二表面上，其中所述多个半导体芯片至少经由所述中介层而电连接至所述重配置线路结构。

Description

多芯片封装件及其制造方法
技术领域
本发明涉及一种半导体封装件及其制造方法，且特别是有涉及一种多芯片封装件及其制造方法。
背景技术
为了使半导体封装件同时具有轻薄体积以及高性能，目前的封装技术已尝试将多个半导体芯片整合于单一半导体封装件中而形成多芯片封装件或是以三维堆叠技术堆叠多个半导体封装件而形成堆叠式封装件(Package on package，PoP)或系统级封装件(System in Package)。然而，现有的多芯片封装件中的多个半导体芯片之间的信号沟通速度受限，因此半导体封装件的整体效能仍有待进一步的提升。
发明内容
本发明的目的是提供一种效能良好的多芯片封装件。
本发明提供一种多芯片封装件，包括中介层、多个半导体芯片、包封体及重配置线路结构。所述中介层包括布线结构与电连接至所述布线结构的中介通路。所述多个半导体芯片位于所述中介层的第一表面上且经由所述中介层而彼此电连接。所述包封体位于所述中介层的所述第一表面上且包封所述多个半导体芯片的至少部分。所述重配置线路结构位于所述中介层的第二表面上，所述中介层的所述第二表面与所述中介层的所述第一表面相对。所述多个半导体芯片至少经由所述中介层电连接至所述重配置线路结构。
本发明提供一种多芯片封装件，包括中介层、多个半导体芯片及重配置线路结构。所述中介层包括：布线结构、暴露出所述布线结构的至少部分的开口以及位于所述开口中且电连接至所述布线结构的中介通路。所述多个半导体芯片位于所述中介层的第一表面上且经由所述中介层而彼此电连接。所述重配置线路结构，位于所述中介层的第二表面上且与所述中介通路电连接，所述中介层的所述第二表面与所述中介层的所述第一表面相对。所述多个半导体芯片至少经由所述中介层电连接至所述重配置线路结构。
本发明提供一种制造多芯片封装件的方法，包括以下步骤。于中介层的第一表面上提供多个半导体芯片以使所述中介层的第一导体与所述多个半导体芯片的第二导体彼此接合。从中介层的与第一表面相对的第二表面形成开口，以暴露出所述中介层的布线结构的至少部分。在所述中介层的所述开口中形成中介通路，所述中介通路连接到所述中介层的所述布线结构。在所述中介层的所述第二表面上形成重配置线路结构，所述重配置线路结构电连接至所述中介通路。
基于上述，本发明的多芯片封装件可提升多芯片封装件的整体效能。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1是发明的一实施例的多芯片封装件的剖面示意图；
图2是沿图1的多芯片封装件的剖线I-I’的平面示意图；
图3A至图3H是本发明的一实施例的制造多芯片封装件的制造流程步骤的剖面示意图；
图4A及图4B是本发明的一实施例的接合芯片的方法的剖面示意图；
图5A及图5B是本发明的另一实施例的接合芯片的方法的剖面示意图。
具体实施方式
现将详细地参考本发明的示范性实施例，示范性实施例的实例说明于附图中。只要有可能，相同元件符号在附图和描述中用来表示相同或相似部分。
下文列举实施例并配合所附的附图来进行详细地说明，但所提供的实施例并非用以限制本发明所涵盖的范围。此外，附图仅以说明为目的，并未依照原尺寸作图，且可能放大或缩小不同的膜层或区域来显示于单一附图中。而且，虽然文中使用如“第一”、“第二”等来描述不同的元件、区域及/或构件，但是这些元件、区域及/或构件不应当受限于这些用语。而是，这些用语仅用于区别一元件、区域或构件与另一元件、区域或构件。因此，以下所讨论的第一元件、区域或构件可以被称为第二元件、区域或构件而不违背实施例的教示。相同或相似的参考号码表示相同或相似的元件，以下段落将不再一一赘述。
在本文中，参照附图定义诸如“上”及“下”的空间相对用语。因此，应该理解，用语“上表面”可与术语“下表面”互换使用，并且当诸如层或膜的元件被描述为配置在另一个元件上时，所述元件可直接放置在另一个元件上，或者在这两个元件间可存在中介元件。另一方面，当一个元件被描述为直接配置在另一个元件上时，这两个元件间之间没有中介元件。类似地，当元件被描述为与另一个元件连接或接合时，所述元件可与另一个元件直接连接或直接接合，或者在这两个元件间可存在中介元件。另一方面，当一个元件被描述为与另一个元件直接连接或直接接合时，这两个元件间之间没有中介元件。
图1是绘示根据本发明的一实施例的多芯片封装件的剖面示意图。图2是沿图1的多芯片封装件的剖线I-I’的平面示意图。
参照图1，根据本发明的一实施例的多芯片封装件100包括中介层150、在中介层150的第一表面150A上的半导体芯片120以及在中介层150的与第一表面150A相对的第二表面150B上的重配置线路结构110。
中介层150可用于将并排的半导体芯片120彼此连接以及将半导体芯片120连接至重配置线路结构110。中介层150在中介层150的主体中可包括布线结构150W、暴露出布线结构150W的开口150H以及位于开口150H中且连接至布线结构150W的中介通路153，且在中介层150的第一表面150A上可包括连接至布线结构150W的中介层连接导体150P。布线结构150W可用于在并排的半导体芯片120间传输信号，尤其是高频宽信号。中介通路153可将布线结构150W电连接至重配置线路结构110。
在目前的系统级封装件(System in Package)中，使用重配置线路结构传输并排的半导体芯片间的信号。然而，随着高效能运算应用的增加，对于高频宽信号的传输需求也在不断提高。重配置线路结构受限于线宽线距与有机介电层曝光显影能力，联线用层数并不多，因此仍需要具有更高线路密度的连接结构以满足例如高频宽存储器(HighBandwidth Memory，HBM)的频宽要求。本发明的多芯片封装件通过使用相较于重配置布线结构具有更高线路密度(即更小的线宽线距与更多层数)的布线结构150W来传输半导体芯片120之间的信号以实现更快的信号传输。
举例而言，在根据本发明的多芯片封装件中，布线结构150W的层数可为多层，例如4层或大于4层，且其线宽、线距与通路(via)大小可小于或等于10微米。由于本发明的多芯片封装件中可具有线宽小于或等于10微米的布线结构150W连接半导体芯片120，因此，可在半导体芯片120间进行高频宽的信号传输。
此外，根据本发明的多芯片封装件100可在中介层150的背侧形成中介通路153以将布线结构150W电连接至重配置线路结构110。本发明的多芯片封装件100中的中介通路153无需穿透中介层，也就是说，在中介层150中可不形成例如硅穿孔(through siliconvia)或玻璃穿孔(through glass via)等穿孔结构，因此根据本发明的多芯片封装件的中介层150可省去形成穿孔结构的附图而降低成本并提高良率。但本发明不限于此，视需要，在中介层150中也可形成穿孔结构。
中介层150的主体的材料可例如为硅(Si)、锗(Ge)、砷化镓(GaAs)等无机半导体材料或玻璃。布线结构150W可形成于中介层150的主体中。布线结构150W可用于在半导体芯片120间传输信号，尤其是高频宽信号。布线结构150W的材料可包括例如铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)、铂(Pt)、钨(W)或其合金等导电材料或其他电特性优异的金属或其合金。如上所述，布线结构150W具有高线路密度。在一些实施例中，布线结构150W的层数可为多层，例如4层或多于4层，且其线宽、线距与通路(via)大小可小于或等于10微米。举例而言，布线结构150W的线宽、线距与通路大小可各自为约1微米或小于1微米、约2微米或小于2微米、约3微米或小于3微米、约4微米或小于4微米、约5微米或小于5微米、约6微米或小于6微米、约7微米或小于7微米、约8微米或小于8微米或者约9微米或小于9微米。
参照图2，中介层150可具有多个开口150H。所述多个开口150H可从所述中介层150的第二表面穿透中介层150的至少部分，但不贯穿中介层150。换句话说，所述多个开口150H不直接接触所述中介层150的第一表面150A。所述多个开口150H可具有不同的深度，因此所述多个开口150H可分别暴露出不同层的布线结构。参照图1中的放大图，开口150H的较靠近第二表面150B的一端的宽度WB可大于较靠近第一表面150A的另一端的宽度WA。也就是说，开口150H的倾斜侧壁(tapered sidewalls)与第二表面150B间的夹角α可大于90°。换句话说，开口150H的宽度随着与半导体芯片120的距离增大而增加。开口150H的侧壁上配置有中介通路153。中介通路153的材料可包括铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)、铂(Pt)、钨(W)或其合金等导电材料。中介通路153可用于使中介层150的布线结构150W与重配置线路结构110的重配置布线层116彼此电连接。如图1所示，中介通路153可共形地形成在开口150H的表面上，也就是以薄层的形式形成在开口150H的壁表面上。在其他实施例中，中介通路153也可填充整个开口150H。
在中介层150的第一表面150A上形成有中介层连接导体150P。中介层连接导体150P可用于将中介层150连接至其他装置。中介层连接导体150P的材料可包括例如铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)、铂(Pt)、钨(W)或其合金等导电材料或其他电特性优异的金属或其合金。中介层连接导体150P的形状可包括柱状或图钉状凸块(Stud bump)等各种形状。中介层连接导体150P可具有不同的大小。举例而言，中介层连接导体150P可包括大小较大的第一中介层连接导体150P1与大小较小的第二中介层连接导体150P2。也就是说，第一中介层连接导体150P1的宽度DA大于第二中介层连接导体150P2的宽度DB。在其他的实施例中，中介层连接导体150P可具有相同的大小。
半导体芯片120可为任何合适的集成电路(IC)芯片，例如存储器芯片、逻辑芯片、数字芯片、模拟芯片、传感器芯片(sensor chip)、人工智慧芯片(AI chip)、无线射频芯片(wireless and radio frequency chip)或电压调节器芯片等。其中传感器芯片可为图像传感器芯片，至少包括电荷耦合元件(CCD)或互补金属氧化物半导体图像传感器(CMOSimage sensor)。虽然在图1的多芯片封装件100中包括两个半导体芯片120，但本发明不限于此。举例而言，本发明的多芯片封装件可包括三个或多于三个半导体芯片120。在一些实施例中，各个半导体芯片120之间的横向距离可以维持固定(即半导体芯片120等距地排列于中介层150上)。在其他实施例中，各个半导体芯片120之间的横向距离可以改变(即半导体芯片120非等距地排列于中介层150上)。各个半导体芯片120间可通过下文将描述的包封体180彼此分隔开。
半导体芯片120在主动面上具有芯片连接导体120P。芯片连接导体120P的材料可包括例如铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)、铂(Pt)、钨(W)或其合金等导电材料或其他电特性优异的金属或其合金。芯片连接导体120P的形状可包括柱状或图钉状凸块(Stud bump)等各种形状。芯片连接导体120P可具有不同的大小。举例而言，芯片连接导体120P可包括大小较大的第一芯片连接导体120P1与大小较小的第二芯片连接导体120P2。也就是说，第一芯片连接导体120P1的宽度D1大于第二芯片连接导体120P2的宽度D2。芯片连接导体120P与至少一部分的中介层连接导体150P彼此接合。在一些实施例中，彼此相应地接合的芯片连接导体120P与中介层连接导体150P可具有相应的大小。举例来说，较大的第一芯片连接导体120P1可接合到较大的第一中介层连接导体150P1，较小的第二芯片连接导体120P2可接合到较小的第二中介层连接导体150P2。在这种情况下，较大的第一芯片连接导体120P1与第一中介层连接导体150P1可用于传输大电流(例如接地)，而较小的第二芯片连接导体120P2与第二中介层连接导体150P2可用于传输高频宽信号。芯片连接导体120P与中介层连接导体150P的接合面可为无焊料接合面。由于中介层150与半导体芯片120是经由芯片连接导体120P与中介层连接导体150P而非重配置线路结构彼此连接，因此可缩短中介层150与半导体芯片120之间的电源及/或信号的传递路径，而提高电源及/或信号的传递速度与品质。在一些实施例中，芯片连接导体120P与中介层连接导体150P之间可进一步包括凸块(如图4B所示)。
另外，并排的半导体芯片120可经由中介层150中的布线结构150W而彼此连接。如上所述，芯片间互连的高密度布线结构150W可具有小于或等于10微米的线宽，布线结构150W可在半导体芯片120之间进行高频宽信号的传输。另外，视所欲传输的信号或电流而定，需要较快传输速度或频宽较大的信号可经由第二芯片连接导体120P2与第二中介层连接导体150P2传输，而电源或接地可经由第一芯片连接导体120P1与第一中介层连接导体150P1传输。也就是说，在本发明的多芯片封装件100中，半导体芯片120间的信号传输可视信号的性质而定而经由不同的路径传输。
根据本发明的多芯片封装件100在半导体芯片120与中介层150之间可包括底胶(Underfill)170。底胶170可填充半导体芯片120与中介层150之间的空间并包封中介层连接导体150P与芯片连接导体120P。底胶170具有倾斜侧壁，且底胶170的上部宽度会小于底胶170的下部宽度。在一些实施例中，底胶170的宽度是渐变的，且底胶170的宽度从较靠近中介层150的一端朝着较靠近半导体芯片120的另一端逐渐缩减。底胶170的材料没有特别限制，且例如可为环氧树脂等绝缘材料。在其他实施例中，根据本发明的多芯片封装件100在半导体芯片120与中介层150之间也可以保护层175取代底胶170(参见图5B)。
根据本发明的多芯片封装件100在中介层150上可包括包封体(encapsulant)180以包封半导体芯片120与中介层150。包封体180可配置在半导体芯片120间以将半导体芯片120彼此分隔开。包封体180的材料可包括模塑化合物、模塑底部填料、树脂或环氧模制化合物(epoxy molding compound，EMC)等。视需要，包封体180中可掺杂有无机填料。包封体180的侧壁、中介层150的侧壁与重配置线路结构110的侧壁可彼此对准。
重配置线路结构110位于中介层150的第二表面150B上且可用于将半导体芯片120的输出输入端子重布线。举例而言，重配置线路结构110可用于扇出(fan-out)半导体芯片120的输出输入端子以连接半导体芯片120与印刷线路板(PCB)(未绘示)。重配置线路结构110包括多个介电层114与多个嵌置于介电层114中的重配置布线层116。介电层114的材料可包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、双马来酰亚胺-三氮杂苯树脂(Bismaleimide-trazine resin，BT resin)或任何其他合适的聚合物系介电材料以及氧化硅层、氮化硅层、氮氧化硅层或其他合适的硅介电材料。在一些实施例中，介电层114的材料可包括感光性绝缘树脂。重配置布线层116的材料可包括铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)、铂(Pt)、钨(W)或其合金等导电材料。
重配置线路结构110可还包括重配置通路118，重配置通路118可用于连接位于不同层的重配置布线层116。重配置通路118的材料可包括铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)、铂(Pt)、钨(W)或其合金等导电材料。重配置通路118的上部宽度W1可小于重配置通路118的下部宽度W2。也就是说，重配置通路118的倾斜侧壁与介电层114的下表面间的夹角β可大于90°。
虽然图1中的重配置线路结构110绘示为包括三层介电层114与三层重配置布线层116，但本发明不限于此。根据本发明的多芯片封装件100可包括比图中所示更多或更少层数的介电层114与重配置布线层116。
根据本发明的多芯片封装件100可还包括导电端子190。导电端子190部分地嵌置于最下介电层114中以连接至最下重配置布线层116。导电端子190可用于将多芯片封装件100与例如印刷电路板等外部装置连接。导电端子190可例如为焊球，但本发明不限于此。
在根据本发明的多芯片封装件100中，并排的半导体芯片120可通过具有高密度与高层数的布线结构150W的中介层150彼此连接而实现高效率的信号传递。同时，根据本发明的多芯片封装件100可通过重配置线路结构110对半导体芯片120重布线而实现扇出型封装。
图3A至图3H是根据本发明的一实施例的制造多芯片封装件的制造流程步骤的剖面示意图。图4A及图4B是绘示根据本发明的一实施例的接合芯片的方法的剖面示意图。图5A及图5B是绘示依照本发明的另一实施例的接合芯片的方法的剖面示意图。
参照图3A，提供具有布线结构150W的半导体基底15。半导体基底15可例如为硅基底。虽然在附图中仅绘示使用半导体基底15形成一个多芯片封装件的工艺，但在一些实施例中，可使用具有大尺寸的半导体基底15以同时形成多个多芯片封装件。举例而言，可使用硅晶片或面板级硅基底作为半导体基底15。半导体基底15在第一表面150A上具有中介层连接导体150P，中介层连接导体150P与布线结构150W电连接。中介层连接导体150P包括具有不同大小的第一中介层连接导体150P1与第二中介层连接导体150P2。也就是说，第一中介层连接导体150P1的宽度DA可大于第二中介层连接导体150P2的宽度DB。视需要，第一中介层连接导体150P1的宽度DA与第二中介层连接导体150P2的宽度DB可相同。
参照图3B，提供多个半导体芯片120至半导体基底15上以使芯片连接导体120P与中介层连接导体150P彼此对准并接合。芯片连接导体120P包括具有不同大小的第一芯片连接导体120P1与第二芯片连接导体120P2。也就是说，第一芯片连接导体120P1的宽度D1可大于第二芯片连接导体120P2的宽度D2。在一些实施例中，大小较大的第一芯片连接导体120P1与第一中介层连接导体150P1彼此接合，大小较小的第二芯片连接导体120P2与第二中介层连接导体150P2彼此接合。芯片连接导体120P与中介层连接导体150P的接合方法可例如为通过加热及/或压力而直接接合。在芯片连接导体120P与中介层连接导体150P接合之后，可在半导体基底15上施加底胶170以包封芯片连接导体120P与中介层连接导体150P。
在一些实施例中，芯片连接导体120P与中介层连接导体150P可通过凸块彼此接合。参见图4A，可在中介层连接导体150P上形成第一凸块155并在芯片连接导体120P上形成第二凸块165。接着再利用热能及/或压力将第一凸块155与第二凸块165接合。第一凸块155与第二凸块165的材料可例如为焊锡合金(如Cu/Sn、Cu/Ni/Sn、Cu/Ni/SnBi)、铜、金、银、铟、钯、钛、锰、钴、或其合金(如Ni/Au、Cu/Ni/Au、Cu/Ni/In)等接合金属。第一凸块155与第二凸块165的材料可彼此不同。举例而言，第一凸块155的材料可为经表面处理的纯铜、Ni/Au合金、Cu/Ni/Au合金或Cu/Ni/In合金等且第二凸块165的材料可为Cu/Sn、Cu/Ni/Sn或Cu/Ni/SnBi合金等。在一些实施例中，第一凸块155与第二凸块165的材料不含焊锡成分。在一些实施例中，第一凸块155与第二凸块165的材料可为熔点低于200℃的低温接合金属。举例来说，低温接合金属可包括双晶铜、双晶银或其他纳米双晶材料、铟锡合金、锡铋合金、多孔金或其组合。相对于传统焊球或焊料所需回焊温度多高于或等于250℃，使用低温接合金属可在相对较低的加热温度下(例如，在低于200℃或低于150℃的温度下)使得连接结构达到稳定接合，且满足电连接要求的可靠度要求。在一些实施例中，可仅形成第一凸块155与第二凸块165中的一者。举例来说，可仅在中介层连接导体150P上形成第一凸块155并将第一凸块155与芯片连接导体120P接合。
接着参见图4B，在第一凸块155与第二凸块165接合之后，可在半导体基底15上施加底胶170以包封芯片连接导体120P、中介层连接导体150P、第一凸块155与第二凸块165。底胶170可填充半导体芯片120与半导体基底15之间的空间并包封中介层连接导体150P、芯片连接导体120P、第一凸块155与第二凸块165。
参照图5A及图5B，在一些实施例中，可在半导体芯片120上形成保护层175。保护层175的材料可为例如树脂、非导电性胶膜、介电材料等有机材料。芯片连接导体120P的表面与半导体芯片120之间的保护层175的表面可共面。当芯片连接导体120P与中介层连接导体150P彼此接合时，由于芯片连接导体120P被保护层175包封而只有表面露出进行连接，因此可避免受到外力冲击而受损，如此一来，可提高良率。
返回参照图3C，在半导体基底15上形成包封体180。形成包封体180的方法包括以下步骤。通过合适的工艺(例如模塑工艺或沉积工艺)在半导体基底15之上形成覆盖半导体基底15与半导体芯片120的包封材料层，此后，执行表面研磨抛光工艺(grinding)或者表面平坦化工艺(surface planarization)使得半导体芯片120的上表面暴露出来。
接着共同参照图3C与图3D，将图3C所得的结构上下倒置，并对半导体基底15的背面进行例如研磨工艺或蚀刻工艺等减薄工艺以减小半导体基底15的厚度。使半导体基底15的厚度减小的目的在于使最终多芯片封装件小型化及薄型化。此外，半导体基底15的厚度减小也有助于接下来的开口150H的形成。视需要，可省略此步骤。减薄后的半导体基底15在下文中称为中介层150。
参照图3E，通过例如蚀刻工艺在中介层150中形成暴露出中介层150中的布线结构150W的至少部分的多个开口150H。参照图3E中的放大图，在中介层150中所形成的开口150H靠近第二表面150B处的宽度WB可大于靠近第一表面150A处的宽度WA。也就是说，开口150H的倾斜侧壁(tapered sidewalls)与第二表面150B间的夹角α可大于90°。换句话说，开口150H的宽度随着与半导体芯片120的距离增大而增加。
参照图3F，在中介层150的第二表面150B与开口150H的表面上分别形成重配置布线层116与中介通路153。重配置布线层116与中介通路153可整合地形成。举例而言，形成重配置布线层116与中介通路153的工艺包括以下步骤。首先在中介层150的第二表面150B与开口150H的表面上溅镀或沉积晶种层，其中晶种层的材料可例如为钛/铜等导电材料。接着，在晶种层上形成图案化光致抗蚀剂层以暴露出晶种层。通过电镀工艺于被图案化光致抗蚀剂层所暴露出的晶种层上形成导电材料，所述导电材料可包括铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)、铂(Pt)、钨(W)或其合金。接着，移除光致抗蚀剂层以及未被导电材料所覆盖的部分晶种层而形成重配置布线层116与中介通路153。
参照图3G，可在重配置布线层116上与中介通路153上形成介电层114，从而形成重配置线路结构(redistribution circuit structure)110。形成介电层114的方法可包括旋转涂布、化学气相沉积(chemical vapor deposition，CVD)、等离子体增强型化学气相沉积(plasma-enhanced chemical vapor deposition，PECVD)等。介电层114可填充开口150H中未被中介通路153占据的空间。
重配置线路结构110可包括多层或单层重配置布线层116。当重配置线路结构110包括多层重配置布线层116时，形成上层的重配置布线层116的工艺包括以下步骤。首先，在介电层114中形成通路孔洞以暴露出其下的重配置布线层116，其中于介电层114中形成通路孔洞的方法可取决于介电层114的材料而采用不同的工艺。当介电层114为包括感光性绝缘树脂的感光性绝缘层时，介电层114可通过光刻工艺进行图案化以形成通路孔洞。当介电层114为非感光性绝缘层时，介电层114可通过光刻/蚀刻工艺、激光钻孔工艺或机械钻孔工艺进行图案化以形成通路孔洞。接着以与上述形成重配置布线层116的方法相同的方法形成上层的重配置布线层116与填充通路孔洞的重配置通路118以连接到经由通路孔洞所暴露出的重配置布线层116。虽然在附图中，重配置线路结构110绘示为包括三层介电层114与三层重配置布线层116，但本发明不以此为限，重配置线路结构110可包括较附图更多层或更少层的介电层114与重配置布线层116。
参照图3H，可在重配置线路结构110上形成多个导电端子190而完成本发明的多芯片封装件100。可使用大尺寸的半导体基底15同时形成多个本发明的多芯片封装件100，接着，再通过切割等工艺以分离个别多芯片封装件100。因此本发明的多芯片封装件100中的中介层150的侧壁、包封体180的侧壁可与重配置线路结构110的侧壁对准。
综上所述，本发明提供一种多芯片封装件及其制造方法。本发明的多芯片封装件能够缩短多芯片封装件中的电源及/或信号的传递路径而提升多芯片封装件的整体效能，同时本发明的多芯片封装还具有重布线结构而具有扇出型封装的设计自由度。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (20)

1.一种多芯片封装件，其特征在于，包括：
中介层，包括布线结构与电连接至所述布线结构的中介通路；
多个半导体芯片，位于所述中介层的第一表面上且经由所述中介层而彼此电连接；
包封体，位于所述中介层的所述第一表面上且包封所述多个半导体芯片的至少部分；以及
重配置线路结构，位于所述中介层的第二表面上，所述中介层的所述第二表面与所述中介层的所述第一表面相对，
其中所述多个半导体芯片至少经由所述中介层而电连接至所述重配置线路结构。
2.根据权利要求1所述的多芯片封装件，其中所述中介层的所述第一表面上配置有中介层连接导体，所述多个半导体芯片的每一者的紧邻所述中介层的表面上配置有芯片连接导体，所述中介层连接导体与所述芯片连接导体彼此接合。
3.根据权利要求2所述的多芯片封装件，其中所述中介层连接导体与所述芯片连接导体之间的接合面为无焊料接合面。
4.根据权利要求2所述的多芯片封装件，其中所述中介层连接导体与所述芯片连接导体通过熔点低于200℃的接合金属接合。
5.根据权利要求2所述的多芯片封装件，还包括位于所述中介层连接导体与所述芯片连接导体之间的第一凸块。
6.根据权利要求5所述的多芯片封装件，还包括位于所述第一凸块与所述芯片连接导体之间的第二凸块。
7.根据权利要求2所述的多芯片封装件，还包括:
保护层，配置于所述中介层与所述多个半导体芯片之间且包封所述中介层连接导体与所述芯片连接导体。
8.根据权利要求2所述的多芯片封装件，其中所述中介层连接导体包括第一中介层连接导体与第二中介层连接导体，所述第一中介层连接导体的大小大于所述第二中介层连接导体的大小。
9.根据权利要求8所述的多芯片封装件，其中所述芯片连接导体包括第一芯片连接导体与第二芯片连接导体，所述第一芯片连接导体的大小大于所述第二芯片连接导体的大小。
10.根据权利要求9所述的多芯片封装件，其中所述第一中介层连接导体与所述第一芯片连接导体彼此接合，且所述第二中介层连接导体与所述第二芯片连接导体彼此接合。
11.根据权利要求1所述的多芯片封装件，其中所述中介层包括暴露出所述布线结构的至少部分的开口，所述中介通路配置于所述开口中。
12.根据权利要求11所述的多芯片封装件，其中所述开口的宽度随着与所述多个半导体芯片的距离增大而增加。
13.根据权利要求11所述的多芯片封装件，其中所述重配置线路结构包括介电层与重配置布线层，且所述重配置布线层与所述中介通路电连接。
14.根据权利要求13所述的多芯片封装件，其中部分的所述介电层填充部分的所述开口。
15.根据权利要求1所述的多芯片封装件，其中所述包封体的侧壁、所述中介层的侧壁以及所述重配置线路结构的侧壁彼此对准。
16.根据权利要求1所述的多芯片封装件，其中所述中介层包括硅穿孔。
17.根据权利要求1所述的多芯片封装件，其中所述中介层的主体的材料包括硅、锗、砷化镓或玻璃。
18.根据权利要求1所述的多芯片封装件，还包括:
底胶，配置于所述中介层与所述多个半导体芯片之间，其中所述底胶的宽度随着与所述多个半导体芯片的距离增大而增加。
19.一种多芯片封装件，其特征在于，包括：
中介层，包括布线结构、暴露出所述布线结构的至少部分的开口以及位于所述开口中且电连接至所述布线结构的中介通路；
多个半导体芯片，位于所述中介层的第一表面上且经由所述中介层而彼此电连接；以及
重配置线路结构，位于所述中介层的第二表面上且与所述中介通路电连接，所述中介层的所述第二表面与所述中介层的所述第一表面相对，
其中所述多个半导体芯片至少经由所述中介层电连接至所述重配置线路结构。
20.一种制造多芯片封装件的方法，包括：
在中介层的第一表面上提供多个半导体芯片以使所述中介层的中介层连接导体与所述多个半导体芯片的芯片连接导体彼此接合；
从所述中介层的与所述第一表面相对的第二表面形成开口，以暴露出所述中介层的布线结构的至少部分；
在所述中介层的所述开口中形成中介通路，所述中介通路连接至所述中介层的所述布线结构；以及
在所述中介层的所述第二表面上形成重配置线路结构，所述重配置线路结构电连接至所述中介通路。
CN202011061287.0A 2019-10-09 2020-09-30 多芯片封装件及其制造方法 Pending CN112652608A (zh)

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