CN114464577A - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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Publication number
CN114464577A
CN114464577A CN202210032805.9A CN202210032805A CN114464577A CN 114464577 A CN114464577 A CN 114464577A CN 202210032805 A CN202210032805 A CN 202210032805A CN 114464577 A CN114464577 A CN 114464577A
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semiconductor
semiconductor die
die
bonding
layer
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CN202210032805.9A
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陈明发
陈宪伟
叶松峯
陈洁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN114464577A publication Critical patent/CN114464577A/zh
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Abstract

一种半导体封装件，包括第一半导体管芯、第二半导体管芯、和多个凸块。第一半导体管芯具有彼此相对的正面和背面。第二半导体管芯设置在第一半导体管芯的背面，并且电连接至第一半导体管芯。多个凸块设置在第一半导体管芯的正面，并且物理接触第一半导体管芯的第一管芯焊盘。第一半导体管芯的总宽度小于第二半导体管芯的总宽度。本申请的实施例还提供了半导体封装件的形成方法。

Description

半导体封装件及其形成方法
技术领域
本申请的实施例涉及半导体封装件及其形成方法。
背景技术
由于各种电子组件(例如晶体管、二极管、电阻器、电容器、等等)的集成密度方面的持续改进，半导体工业已经经历了快速增长。在大多数情况下，集成密度方面的改进源于最小特征尺寸的迭代减小，这允许将更多组件集成至给定区域中。随着最近对小型化、更高速度和更大带宽、以及更低功耗和延迟的需求的不断增长，对更小、更具创造性的半导体管芯封装技术的需求也在增长。目前，半导体封装件(例如集成电路上系统(SoIC)组件)因其多功能和紧凑性而变得越来越流行。然而，存在与此类半导体封装件相关的挑战。
发明内容
根据本公开的一些实施例，一种半导体封装件，包括第一半导体管芯、第二半导体管芯、和多个凸块。第一半导体管芯具有彼此相对的正面和背面。第二半导体管芯设置在第一半导体管芯的背面，并且电连接至第一半导体管芯。多个凸块设置在第一半导体管芯的正面，并且物理接触第一半导体管芯的第一管芯焊盘。另外，第一半导体管芯的尺寸小于第二半导体管芯的尺寸。
根据本公开的一些实施例，半导体结构包括两个第一半导体管芯、凸块、第一接合结构、和桥接结构。两个第一半导体管芯并排设置。凸块设置在第一半导体管芯的正面，并且与第一半导体管芯的第一管芯焊盘物理接触。第一接合结构设置在第一半导体管芯的背面，并且横向地延伸超出第一半导体管芯，其中正面与背面相对。桥接结构设置在第一接合结构上方，并且位于第一半导体管芯之间。
根据本公开的一些实施例，一种形成半导体封装件的方法包括以下操作。提供第一半导体管芯，其中第一半导体管芯包括第一半导体衬底、穿透第一半导体衬底的第一贯穿衬底通孔、以及形成在第一半导体衬底上方并且电连接至第一贯穿衬底通孔的第一互连结构。第二半导体管芯接合至第一半导体管芯的第一半导体衬底的背面。多个第一管芯焊盘形成在第一半导体衬底的正面上方和第一半导体管芯的芯片区域内，其中多个第一管芯焊盘物理地连接第一互连结构的顶部金属图案。多个凸块形成在第一管芯焊盘上方。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图10是示意性地示出根据本发明的一些实施例形成半导体封装件的方法的截面图；
图11是示意性地示出根据本发明的一些实施例的半导体封装件的截面图；
图12至图21是示意性地示出根据本发明的其他实施例形成半导体封装件的方法的截面图；
图22至图23是示意性地示出根据本发明的其他实施例的半导体封装件的截面图；
图24至图31是示意性地示出根据本发明的一些实施例的半导体封装件的截面图；
图32示出了根据一些实施例形成半导体封装件的方法；
图33示出了根据其他实施例形成半导体封装件的方法；
图34至图39是示意性地示出根据本发明的一些实施例的半导体封装件的截面图；
图40示出了根据一些实施例形成半导体封装件的方法；
图41示出了根据其他实施例形成半导体封装件的方法。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。另外，本发明可以在各个实例中重复参考数字和/或字母。该重复是出于简化和清楚的目的，其本身并不指示所讨论的各种实施例和/或结构之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以容易地描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
在一些实施例中，当提供具有不同尺寸的两个半导体管芯时，较小的半导体管芯配置成面对球阵列，而较大的半导体管芯配置成背对球阵列。通过这样的配置，半导体封装件的信号传输性能可以显著改善。
图1至图10是示意性地示出根据本发明的一些实施例形成半导体封装件的方法的截面图。应当理解的是，本公开并不限于以下描述的方法。可以在方法之前、期间、和/或之后提供其他的操作，并且对于方法的其他的实施例，可以替换或者取消以下所描述的一些操作。虽然图1至图10是关于一种方法进行描述，但是应当理解的是，图1至图10中所公开的结构并不限于这种方法，而是可以作为独立于该方法的结构而单独地存在。
参考图1，提供多个半导体管芯100(例如逻辑管芯、存储器管芯、等等)。在图1中，仅示出了两个半导体管芯100；然而，本发明并不限制半导体管芯100的数量。在一些实施例中，半导体管芯100中的每一个包括有源正面S1(例如正面)和与正面S1相对的背面S2(例如背面)。在一些实施例中，半导体管芯100包括半导体衬底102、至少一个器件T1、互连结构106、管芯焊盘P1、和钝化层112。贯穿说明书，半导体管芯100的对应于半导体衬底具有器件或者有源层的一面的一面称为正面。
半导体衬底102可以包括诸如硅、锗的元素半导体，和/或诸如硅锗、碳化硅、砷化镓、砷化铟、氮化镓、或者磷化铟的化合物半导体。在一些实施例中，半导体衬底102可以采用平面衬底的形式、具有多个鳍部、纳米线的衬底的形式、或者其他的形式。半导体管芯100可以还包括贯穿衬底通孔(TSV)103，其形成在半导体衬底102中，并且电连接至互连结构106的互连引线或者导线。如图1中所示，贯穿衬底通孔103嵌入在半导体衬底102和互连结构106中，并且在此阶段，贯穿衬底通孔103没有从半导体衬底102的背面露出。贯穿衬底通孔103可以包括Cu、Ti、Ta、W、Ru、Co、Ni、等等、其合金、或其组合。在一些实施例中，贯穿衬底通孔103通过电镀工艺形成，并且可以包括一层或者多层，例如阻挡层、粘附层、填充材料、和/或等等。
器件T1设置在半导体衬底102之上/之中，并且包括一个或者多个功能器件。功能器件可以包括有源组件、无源组件、或其组合。在一些实施例中，功能器件可以包括集成电路器件。功能器件是例如晶体管、电容器、电阻器、二极管、光电二极管、熔断器器件、和/或其他类似器件。在一些实施例中，半导体管芯100可以称为“第一器件管芯”、“第一层半导体管芯”、或者“下部集成电路结构”。
互连结构106形成在半导体衬底102上，并且电连接至器件T1。互连结构106可以包括：一个或者多个介电层，统称为介电层110；以及金属部件108，嵌入在至少一个介电层110中。金属部件108设置在介电层110中，并且彼此电连接。金属部件108的一部分，例如第一顶部金属部件108a，由介电层110暴露。在一些实施例中，介电层110包括位于半导体衬底102上的层间介电(ILD)层，以及位于层间介电层上方的至少一个金属间介电(IMD)层。在一些实施例中，介电层110包括氧化硅、氧氮化硅、氮化硅、低介电常数(低-k)材料、或其组合。介电层110可以是单层或者多层结构。在一些实施例中，金属部件108包括金属插塞和金属导线。插塞可以包括形成在层间介电层中的触点，和形成在金属间介电层中的通孔。触点形成在底部金属导线和下面的器件T1之间，并且与之接触。通孔形成在两个金属导线之间，并且与之接触。金属部件108可以包括Cu、Ti、Ta、W、Ru、Co、Ni、等等、其合金、或其组合。在一些实施例中，阻挡层可以设置在每个金属部件108和介电层110之间，以防止金属部件108的材料迁移至下面的器件T1。例如，阻挡层包括Ta、TaN、Ti、TiN、CoW、等等、或其组合。在一些实施例中，互连结构106通过双镶嵌工艺形成。在其他实施例中，互连结构106通过多个单镶嵌工艺形成。在其他实施例中，互连结构106通过电镀工艺形成。
管芯焊盘P1形成在互连结构106上方，并且电连接至互连结构106。在一些实施例中，管芯焊盘P1与互连结构106的最顶部金属部件108a物理接触。在一些实施例中，管芯焊盘P1是铝焊盘。然而，本公开并不限于此。在其他实施例中，管芯焊盘P1是铜焊盘、镍焊盘、或者由其他合适材料制成的焊盘。管芯焊盘P1中的每一个可以是单层或者多层结构。在一些实施例中，一些管芯焊盘P1在其顶面上具有探针标记。在通过测试之后，半导体管芯100可以称为“已知良好管芯”。在一些实施例中，管芯焊盘P1没有探针标记。在一些实施例中，管芯焊盘P1通过溅射工艺、沉积工艺、电镀工艺、其组合、等等来形成。
钝化层112形成在互连结构106上方，并且覆盖管芯焊盘P1的侧壁和顶面。在一些实施例中，钝化层112包括氧化硅、氮化硅、苯并环丁烯(BCB)聚合物、聚酰亚胺(PI)、聚苯并恶唑(PBO)、其组合、等等，并且通过诸如旋涂、CVD、等等的合适的工艺来形成。
在一些实施例中，半导体管芯100的钝化层112有接合膜F1覆盖。在一些实施例中，接合膜F1包括硅(Si)、氧化硅(SiOx，其中x>0)、氮化硅(SiNx，其中x>0)、氧氮化硅(SiOxNy，其中x>0并且y>0)、或者其他合适的接合材料。
参考图2，提供载体C1，其上包括接合膜FC1。载体C1可以是诸如硅晶圆的半导体晶圆，并且接合膜FC1可以是为熔融接合而准备的接合层。在一些实施例中，接合膜FC1是在载体C1的顶面上方形成的沉积层。在其他实施例中，接合膜FC1是用于熔融接合的载体C1的一部分。在一些实施例中，接合膜FC1包括硅(Si)、氧化硅(SiOx，其中x>0)、氮化硅(SiNx，其中x>0)、氧氮化硅(SiOxNy，其中x>0且y>0)、或者其他合适的接合材料。在一些实施例中，接合膜FC1和接合膜F1包括相同的材料，例如氧化硅。在其他实施例中，接合膜FC1和接合膜F1包括不同的材料。
半导体管芯100进行翻转，并且放置在载体C1上，使得接合膜F1与接合膜FC1接触。具体地，将多个半导体管芯100拾取并且以并排的方式放置在接合膜FC1上，使得半导体管芯100排列布置并且彼此间隔开。在一些实施例中，半导体管芯100放置在接合膜FC1的顶面上，使得半导体管芯100的正面S1面对载体C1的接合膜FC1。
在将半导体管芯100拾取并且放置在接合膜FC1上之后，可以实施芯片至晶圆熔融接合工艺，使得熔融接合界面形成在接合膜FC1和接合膜F1之间。例如，用于接合接合膜FC1和接合膜F1的熔融接合工艺实施为在约100摄氏度至约290摄氏度的温度范围内。接合膜FC1可以直接地接合至接合膜F1。换句话说，没有中间层形成在接合膜FC1和接合膜F1之间。以上所提到的在接合膜FC1和接合膜F1之间形成的熔融接合界面可以是Si-Si熔融接合界面、Si-SiOx熔融接合界面、SiOx-SiOx熔融接合界面、SiOx-SiNx熔融接合界面、或者其他合适的熔融接合界面。
参考图3，在半导体管芯100通过接合膜FC1和接合膜F1接合至载体C1之后，介电密封层E1形成在载体C1上方，并且覆盖半导体管芯100。在一些实施例中，介电密封层E1通过包覆成型工艺或者薄膜沉积工艺形成，使得接合膜FC1的顶面的一部分、接合膜F1的侧面、以及半导体管芯100的背面和侧面由介电密封层E1来密封。在一些实施例中，介电密封层E1包括模制化合物、模制底部填充物、树脂、其组合、等等。在一些实施例中，介电密封层E1包括聚合物材料，例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、其组合、等等。在一些实施例中，介电密封层E1包括绝缘材料，例如氧化硅、氮化硅、或其组合。
参考图4，在实施包覆成型工艺或者薄膜沉积工艺之后，可以实施研磨工艺或者平坦化工艺，以减小密封材料的厚度和半导体管芯100的厚度，直至贯通衬底通孔103暴露。在一些实施例中，研磨工艺包括机械研磨工艺、化学机械抛光(CMP)工艺、或其组合。
如图4所示，在一些实施例中，半导体管芯100的厚度等于介电密封层E1的厚度。在一些实施例中，介电密封层E1与半导体管芯100和接合膜F1的侧面接触，并且半导体衬底102的背面从介电密封层E1可接近地暴露。换句话说，介电密封层E1的顶面在工艺变化范围内与半导体管芯100的暴露表面基本齐平。然而，本公开并不限于此。在一些实施例中，由于研磨工艺的抛光选择性，介电密封层E1的顶面可以略高于或者略低于半导体管芯100的暴露表面。
参考图5，再分布层结构119形成在半导体管芯100的背面S2和介电密封层E1的暴露表面的上方。再分布层结构119包括至少一个聚合物层115，和通过聚合物层115嵌入的导电部件117。导电部件117包括配置成电连接至不同组件的金属焊盘、金属导线、和/或金属通孔。在一些实施例中，聚合物层115包括光敏材料，例如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、其组合、等等。再分布层结构119的聚合物层115可以根据需要由介电层或者绝缘层替代。在一些实施例中，导电部件117包括Cu、Ti、Ta、W、Ru、Co、Ni、等等、其合金、其组合、等等。在一些实施例中，晶种层和/或阻挡层可以设置在每个导电部件117和聚合物层115之间。晶种层可以包括Ti/Cu。阻挡层可以包括Ta、TaN、Ti、TiN、CoW、其组合、等等。
仍然参考图5，接合结构120形成在再分布层结构119上方。在一些示例中，接合结构120称为“覆盖接合结构”，因为接合结构120形成为跨半导体管芯100，并且在半导体管芯100之间和之外延伸。
在一些实施例中，接合结构120包括至少一个接合膜(bonding film)BF1，和在接合膜BF1中嵌入的接合金属部件。在一些实施例中，接合膜BF1包括绝缘材料、介电材料、聚合物材料、或其组合。例如，接合膜BF1包括硅(Si)、氧化硅(SiOx，其中x>0)、氮化硅(SiNx，其中x>0)、氧氮化硅(SiOxNy，其中x>0且y>0)、或者其他合适的接合材料。接合金属部件可以包括Cu、Ti、Ta、W、Ru、Co、Ni、其合金、其组合、等等。在一些实施例中，晶种层和/或阻挡层可以设置在每个接合金属部件和接合膜BF1之间。晶种层可以包括Ti/Cu。阻挡层可以包括Ta、TaN、Ti、TiN、CoW、或其组合。在一些实施例中，接合金属部件包括接合焊盘(bonding pads)BP11和BP12，以及接合通孔BV1。具体地，如图5中所示，接合焊盘BP11和接合通孔BV1配置成接合至并且电连接至下面的半导体管芯100和上面的半导体管芯或者管芯堆叠件。在一些实施例中，接合通孔BV1与贯穿衬底通孔103和接合焊盘BP11物理接触。另外，接合焊盘BP12配置成接合至下面的半导体管芯100和上面的半导体管芯或者管芯堆叠件，但是与下面的半导体管芯100和上面的半导体管芯或者管芯堆叠件电隔离。在一些示例中，接合焊盘BP12称为“伪接合焊盘”或者“浮置接合焊盘”，因为它们提供成仅增强管芯之间的接合强度。在一些实施例中，接合焊盘BP11和BP12的尺寸(例如宽度)不同，如图5中所示。然而，本公开并不限于此。在其他实施例中，接合焊盘BP11和BP12可以具有相同的尺寸。
参考图6，提供多个半导体管芯200(例如存储器管芯、逻辑管芯、或者其他合适的管芯)，并且将其放置在接合结构120上。在图4中，示出了两个半导体管芯200；然而，本公开并不限制半导体管芯200的数量。在一些实施例中，半导体管芯200分别对应于下面的半导体管芯100。半导体管芯200和半导体管芯100可以是相同类型或者不同类型的管芯。
在一些实施例中，半导体管芯200中的每一个包括有源正面(例如正面)和与有源面相对的背面(例如背面)。在一些实施例中，半导体管芯200中的每一个包括半导体衬底202、至少一个器件T2、互连结构206、管芯焊盘P2、和钝化层212。贯穿说明书，半导体管芯200的对应于具有器件或者有源层的半导体衬底的一面的一面称为正面。
半导体衬底202可以包括诸如硅、锗的元素半导体，和/或诸如硅锗、碳化硅、砷化镓、砷化铟、氮化镓、或者磷化铟的化合物半导体。在一些实施例中，半导体衬底202可以采用平面衬底的形式、具有多个鳍部、纳米线的衬底的形式、或者本领域普通技术人员已知的其他形式。如果需要，半导体管芯200还可以包括形成在半导体衬底202中、并且电连接至互连结构206的互连引线或者导线的贯穿衬底通孔(TSV)(未示出)。
器件T2设置在半导体衬底202之上/之中，并且包括一个或者多个功能器件。功能器件可以包括有源组件、无源组件、或其组合。在一些实施例中，功能器件可以包括集成电路器件。功能器件是例如晶体管、电容器、电阻器、二极管、光电二极管、熔断器器件、和/或其他类似器件。在一些实施例中，半导体管芯200称为“第二器件管芯”、“第二层半导体管芯”、或者“上部集成电路结构”。在一些实施例中，上部集成电路结构可以由包括多个管芯的管芯堆叠件替代。
互连结构206形成在半导体衬底202上，并且电连接至器件T2。互连结构206可以包括：一个或者多个介电层，统称为介电层210；以及金属部件208，通过介电层210嵌入。金属部件208设置在介电层210中，并且彼此电连接。金属部件208的一部分，例如顶部金属部件208a，由介电层210暴露。在一些实施例中，介电层210包括位于半导体衬底202上的层间介电(ILD)层，以及位于层间介电层上方的至少一个金属间介电(IMD)层。在一些实施例中，介电层210包括氧化硅、氧氮化硅、氮化硅、低介电常数(低-k)材料、其组合、等等。介电层210可以是单层或者多层结构。在一些实施例中，金属部件208包括金属插塞和金属导线。插塞可以包括形成在层间介电层中的触点，和形成在金属间介电层中的通孔。触点形成在底部金属导线和下面的器件T2之间，并且与之接触。通孔形成在两个金属导线之间，并且与之接触。金属部件208可以包括Cu、Ti、Ta、W、Ru、Co、Ni、其合金、其组合、等等。在一些实施例中，阻挡层可以设置在每个金属部件208和介电层210之间，以防止金属部件208的材料迁移至下面的器件T2。例如，阻挡层包括Ta、TaN、Ti、TiN、CoW、其组合、等等。在一些实施例中，互连结构206通过双镶嵌工艺形成。在其他实施例中，互连结构206通过多个单镶嵌工艺形成。在其他实施例中，互连结构206通过电镀工艺形成。
管芯焊盘P2形成在互连结构206上方，并且电连接至互连结构206。在一些实施例中，管芯焊盘P2与互连结构206的最顶部金属部件208a物理接触。在一些实施例中，管芯焊盘P2是铝焊盘。然而，本公开并不限于此。在其他实施例中，管芯焊盘P2是铜焊盘、镍焊盘、或者由其他合适材料制成的焊盘。管芯焊盘P2中的每一个可以是单层或者多层结构。在一些实施例中，一些管芯焊盘P2在其顶面上具有探针标记。在通过测试之后，半导体管芯200可以称为“已知良好管芯”。在一些实施例中，管芯焊盘P2没有探针标记。
钝化层212形成在互连结构206上方，密封管芯焊盘P2的侧壁，但是暴露管芯焊盘P2的顶面。在一些实施例中，钝化层212包括氧化硅、氮化硅、苯并环丁烯(BCB)聚合物、聚酰亚胺(PI)、聚苯并恶唑(PBO)、或其组合，并且通过诸如旋涂、CVD、等等的合适的工艺来形成。
在一些实施例中，接合结构220还提供在互连结构206上方。在一些实施例中，将接合结构220视为半导体管芯200的一部分。在一些示例中，接合结构220称为“管芯接合结构”，因为接合结构220的边缘与半导体管芯200的边缘对准。
在一些实施例中，接合结构220包括至少一个接合膜BF2，和在接合膜BF2中嵌入的接合金属部件。在一些实施例中，接合膜BF2包括绝缘材料、介电材料、聚合物材料、或其组合。例如，接合膜BF2包括硅(Si)、氧化硅(SiOx，其中x>0)、氮化硅(SiNx，其中x>0)、氧氮化硅(SiOxNy，其中x>0且y>0)、或者其他合适的接合材料。接合金属部件可以包括Cu、Ti、Ta、W、Ru、Co、Ni、其合金、其组合、等等。在一些实施例中，晶种层和/或阻挡层可以设置在每个接合金属部件和接合膜BF2之间。晶种层可以包括Ti/Cu。阻挡层可以包括Ta、TaN、Ti、TiN、CoW、其组合、等等。在一些实施例中，接合金属部件包括接合焊盘BP21和BP22，以及接合通孔BV2。如图6中所示，接合焊盘BP21和接合通孔BV2配置成接合至并且电连接至下面的半导体管芯100。在一些实施例中，接合通孔BV2与管芯焊盘P2和接合焊盘BP21物理接触。接合焊盘BP22配置成接合至下面的半导体管芯100，但是与下面的半导体管芯100和上面的半导体管芯200电隔离。在一些示例中，接合焊盘BP22称为“伪接合焊盘”或者“浮置接合焊盘”，因为它们提供成仅增强管芯之间的接合强度。在一些实施例中，接合焊盘BP21和BP22的尺寸(例如宽度)不同，如图6中所示。然而，本公开并不限于此，并且在一些实施例中，接合焊盘BP21和BP22可以具有相同的尺寸。
在一些实施例中，接合结构220与接合结构120对准，实施芯片至晶圆混合接合，使得半导体管芯200的接合结构220混合接合至接合结构120。在一些实施例中，半导体管芯200和半导体管芯100可以通过面对背混合接合工艺进行接合。然而，本公开并不限于此。在一些实施例中，半导体管芯200和半导体管芯100可以通过面对面混合接合工艺进行接合。
图6示出了其中半导体管芯200和半导体管芯100具有不同尺寸的实施例。半导体管芯200的尺寸不同于(例如大于)半导体管芯100的尺寸。在本文中，术语“尺寸”是指高度、长度、宽度、俯视面积、或其组合。例如，从俯视图观察，半导体管芯100的尺寸或者面积小于半导体管芯200的尺寸或者面积。
在一些实施例中，半导体管芯200和半导体管芯100在管芯高度方面可以有所不同。例如，半导体管芯200的高度不同于(例如大于)半导体管芯100的关键尺寸。例如，半导体管芯200的高度范围从约20um至775um，而半导体管芯100的高度范围从约10um至50um。在一些实施例中，半导体管芯200的高度与半导体管芯100的高度的比值范围从30:1至15:1，例如20:1。
在一些实施例中，半导体管芯200和半导体管芯100在关键尺寸方面可以有所不同。例如，半导体管芯200的关键尺寸不同于(例如大于)半导体管芯100的关键尺寸。在本文中，术语“关键尺寸”是指用于IC部件的最小可实现尺寸。例如，关键尺寸包括金属导线的最小线宽或者开口的最小宽度。
在一些实施例中，为了促进接合结构120和接合结构220之间的芯片至晶圆混合接合，可以实施接合结构120和接合结构220的用于接合表面的表面准备。例如，表面准备可包括表面清洁和活化。表面清洁可以实施在接合结构120和接合结构220的接合表面上，以去除接合焊盘和接合膜的接合表面上的颗粒和/或天然氧化物。例如，接合结构120和接合结构220的接合表面通过湿式清洁进行清洁。
在清洁接合结构120和接合结构220的接合表面之后，可以实施顶面的活化，以实现高接合强度。在一些实施例中，实施等离子体活化，以处理和活化接合膜BF1和BF2的接合表面。当接合膜BF1的活化的接合面与接合膜BF2的活化的接合面接触时，接合膜BF1和BF2预接合。接合结构220和接合结构120通过接合膜BF1和BF2的预接合而预接合。在接合膜BF1和BF2预接合之后，接合焊盘BP11与接合焊盘BP21接触，并且接合焊盘BP12与接合焊盘BP22接触。
在接合膜BF1和BF2的预接合工艺之后，实施半导体管芯200和接合结构120的混合接合。半导体管芯200和接合结构120的混合接合可以包括用于介电接合的处理和用于导体接合的热退火。实施用于介电接合的处理，可以加强接合膜BF1和BF2之间的接合。例如，用于介电接合的处理可以实施在约100摄氏度至约150摄氏度的温度范围内。在实施用于介电接合的处理之后，实施用于导体接合的热退火，以促进接合焊盘BP11和BP21之间、以及接合焊盘BP12和BP22之间的接合。例如，用于导体接合的热退火可以实施在约300摄氏度至约400摄氏度的温度范围内。用于导体接合的热退火的工艺温度高于用于介电接合的处理的工艺温度。由于用于导体接合的热退火在相对较高的温度下实施，因此在接合焊盘BP11和BP21之间、以及接合焊盘BP12和BP22之间的接合界面处，可能发生金属扩散和晶粒生长。导体接合不限于焊盘至焊盘接合。可以根据需要施加通孔至通孔接合，或者通孔至焊盘接合。
参考图7，在半导体管芯200通过接合结构120和接合结构220接合至半导体管芯100之后，形成介电密封层E2，以覆盖接合结构120、接合结构220、和半导体管芯200。在一些实施例中，介电密封层E2通过包覆成型工艺或者薄膜沉积工艺形成，使得接合结构120的顶面的一部分、接合结构220的侧面、半导体管芯200的背面和侧面由介电密封层E2来密封。在一些实施例中，介电密封层E2包括模制化合物、模制底部填充物、树脂、等等。在一些实施例中，介电密封层E2包括聚合物材料(例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、其组合、等等)、绝缘材料(例如氧化硅、氮化硅、其组合、等等)、其组合、等等。
在实施包覆成型工艺或者薄膜沉积工艺之后，可以实施研磨工艺或者平坦化工艺，以减小密封材料的厚度和半导体管芯200的厚度，直至半导体管芯200的背面暴露。在一些实施例中，研磨工艺包括机械研磨工艺、化学机械抛光(CMP)工艺、或其组合。
如图7中所示，在一些实施例中，半导体管芯200的厚度等于介电密封层E2的厚度。在一些实施例中，介电密封层E2与半导体管芯200和接合膜BF2的侧面接触，并且半导体衬底202的背面从介电密封层E2可接近地暴露。例如，介电密封层E2的顶面与半导体管芯200的暴露表面基本齐平(在工艺变化范围内)。然而，本公开并不限于此。在一些实施例中，由于研磨工艺的抛光选择性，介电密封层E2的顶面可以略高于或者略低于半导体管芯200的暴露表面。另外，介电密封层E2通过接合结构120与介电密封层E1间隔开。
参考图8，提供载体C2，其上包括接合膜FC2。载体C2可以是玻璃晶圆，而接合膜FC2可以是粘附材料。接合膜FC2可以包括氧化层、管芯连接胶带(DAF)、或者合适的粘附剂。载体C2通过接合膜FC2接合至半导体管芯200的背面和介电密封层E2的暴露表面。在一些实施例中，覆盖接合膜可以提供在接合膜FC2和半导体衬底202之间、以及在接合膜FC2和介电密封层E2之间，并且接合膜FC2可以通过熔融接合而接合至覆盖接合膜。
之后，可以实施剥离工艺，使得接合膜FC1和下面的载体C1从接合膜F1和介电密封层E1剥离。剥离工艺可以是激光剥离工艺或者其他合适的剥离工艺。在去除接合膜FC1和载体C1之后，可以实施研磨工艺，使得去除接合膜F1，以暴露钝化层112。在接合膜F1的去除期间，介电密封层E1可以进行薄化。在一些实施例中，接合膜F1的去除和介电密封层E1的薄化可以通过相同的研磨工艺(例如CMP工艺)来实施。如图8中所示，在实施研磨工艺之后，半导体管芯100暴露，但是在此阶段，半导体管芯100的管芯焊盘P1并未暴露，而是由钝化层112覆盖。
仍然参考图8，实施对钝化层112进行图案化的工艺，使得多个开口OP形成在钝化层112中，并且暴露管芯焊盘P1。在一些实施例中，形成后钝化层(未示出)，以覆盖介电密封层E1和半导体管芯100的钝化层112，并且开口形成为穿过后钝化层和钝化层112。在一些实施例中，实施光刻和蚀刻工艺，以形成开口OP。然而，本公开并不限于此。在其他实施例中，实施激光钻孔工艺以形成开口OP。
之后，导电端子或者凸块B形成在钝化层112的开口OP内，并且电连接至半导体管芯100的管芯焊盘P1。在一些实施例中，凸块B设置在芯片区域内，并且与管芯焊盘P1物理接触。在一些实施例中，凸块B包括焊料凸块，和/或可以包括金属柱(例如铜柱)、在金属柱上形成的焊帽、和/或等等。凸块B可以通过诸如蒸发、电镀、球滴、或者丝网印刷的合适的工艺形成。
参考图9，载体C2从介电密封层E2剥离。在一些实施例中，剥离工艺是激光剥离工艺或者合适的工艺。然后，粘附层或者接合膜FC2从介电密封层E2去除。在一些实施例中，去除工艺是蚀刻工艺和/或清洁工艺。
之后，晶圆切割工艺沿着切割线CL实施在图9的结构上，以切割穿过介电密封层E2、接合膜BF1、聚合物层115、和介电密封层E1。在晶圆切割工艺或者单个化工艺之后，相邻的半导体封装件10彼此分离，如图10中所示。一些实施例的半导体封装件10由此形成。在一些实施例中，诸如印刷电路板(PCB)的板衬底、和/或诸如硅插件或者有机插件的插件衬底，可以提供在下方，并且通过凸块B接合至半导体封装件10。
图11是示意性地示出根据本发明的一些实施例的半导体封装件的截面图。图11的半导体封装件11类似于图10的半导体封装件10，其中相似的附图标记指代相似的元件。图11的元件的材料和配置可以参考先前的实施例中所描述的类似元件的材料和配置。图11的半导体封装件11有利于降低成本和/或减小尺寸。例如，再分布层结构119可以省略，以降低成本和/或减小尺寸。
图11的半导体封装件11的形成方法类似于图1至图10中所描述的半导体封装件10的形成方法，但是形成如图5中所示的再分布层结构119的操作省略，并且接合结构120的结构可以相应地进行改变。在一些实施例中，如图11中所示，半导体管芯200通过接合结构120和接合结构220接合至半导体管芯100，但是如图10中所示的接合通孔BV1可以可选地从接合结构120省略。具体地，接合焊盘BP11与半导体管芯200的接合焊盘BP21以及半导体管芯100的贯穿衬底通孔103物理接触，而接合焊盘BP12与半导体管芯200的接合焊盘BP22以及介电密封层E1物理接触。
在本公开中，当提供具有不同大小和关键尺寸的两个半导体管芯时，具有较小关键尺寸的较小的半导体管芯(例如半导体管芯100)配置成面向球阵列(例如凸块B)，而具有较大关键尺寸的较大的半导体管芯(例如半导体管芯200)则更远离球阵列(例如凸块B)。通过这样的配置，半导体封装件的信号传输性能可以显著提高。关键管芯和球阵列之间的信号直接地进行传输，无需另外的布线或者引线接合。
在上述实施例中，半导体封装件通过“管芯焊盘优先”工艺来形成，其中，在上部半导体管芯接合至下部半导体管芯之前，形成下部半导体管芯的管芯焊盘。然而，本公开并不限于此。在其他实施例中，半导体封装件通过“管芯焊盘次后”工艺来形成，其中，在上部半导体管芯接合至下部半导体管芯之后，形成下部半导体管芯的管芯焊盘。
图12至图21是示意性地示出根据本发明的其他实施例形成半导体封装件的方法的截面图。应当理解的是，本公开并不限于以下描述的方法。可以在方法之前、期间、和/或之后提供其他的操作，并且对于方法的其他的实施例，可以替换或者取消以下所描述的一些操作。
虽然图12至图21是关于一种方法进行描述，但是应当理解的是，图12至图21中所公开的结构并不限于这种方法，而是可以作为独立于该方法的结构而单独地存在。
图21的半导体封装件20的形成方法类似于图1至图10中所描述的半导体封装件10的形成方法，其中下部半导体管芯的管芯焊盘的形成顺序有所不同。它们之间的区别在下面详细地进行说明，而相似之处在此不再赘述。
参考图12和图13，提供多个半导体管芯100(例如逻辑管芯、存储器管芯、等等)，并且将其接合至载体C1。值得注意的是，在图12和图13的阶段中，半导体管芯100提供成不具有管芯焊盘。具体地，半导体管芯100包括半导体衬底102、设置在半导体衬底102之上/之中的至少一个器件T1、设置在半导体衬底102上并且电连接至器件T1的互连结构106、穿过半导体衬底102并且电连接至互连结构106的贯穿衬底通孔103、以及钝化层112。钝化层112形成在互连结构106上方，并且覆盖顶部金属部件108a和介电层110。图12至图13的元件的操作、材料、和配置可以参考图1至图2中所描述的那些。
参考图14和图15，在半导体管芯100通过接合膜FC1和接合膜F1接合至载体C1之后，介电密封层E1形成在载体C1上方，并且横向地密封半导体管芯100。图14至图15的元件的操作、材料、和配置可以参考图3至图4中所描述的那些。
参考图16，再分布层结构119形成在半导体管芯100的背面S2和介电密封层E1的暴露表面上方。之后，接合结构120形成在再分布层结构119上方。图16的元件的操作、材料、和配置可以参考图5中所描述的那些。
参考图17，提供多个半导体管芯200(例如存储器管芯、逻辑管芯、或者其他合适的管芯)，并且将其放置在接合结构120上。图17的元件的操作、材料、和配置可以参考图6中所描述的那些。
参考图18，在半导体管芯200通过接合结构120和接合结构220接合至半导体管芯100之后，介电密封层E2形成为覆盖接合结构120，并且横向地密封半导体管芯200。图18的元件的操作、材料、和配置可以参考图7中所描述的那些。
参考图19，提供载体C2，并且通过接合膜FC2将其接合至半导体管芯200的背面和介电密封层E2的暴露表面。之后，可以实施剥离工艺，使得接合膜FC1和下面的载体C1从接合膜F1和介电密封层E1剥离。在去除接合膜FC1和载体C1之后，可以实施研磨工艺，使得去除接合膜F1，以暴露钝化层112。在接合膜F1的去除期间，介电密封层E1可以进行薄化。在一些实施例中，接合膜F1的去除和介电密封层E1的薄化可以通过研磨工艺(例如CMP工艺)来实施。如图19中所示，研磨工艺实施为直至半导体管芯100的钝化层112暴露。图19的元件的操作、材料、和配置可以参考图8中所描述的那些。
仍然参考图19，实施对钝化层112进行图案化的工艺，使得多个开口OP1形成在钝化层112中，并且暴露互连结构106的顶部金属部件108a。在一些实施例中，实施光刻和蚀刻工艺，以形成开口OP1。然而，本公开并不限于此。在其他实施例中，实施激光钻孔工艺以形成开口OP1。
之后，管芯焊盘P1形成在钝化层112的开口OP1内，并且电连接至半导体管芯100的互连结构106。在一些实施例中，管芯焊盘P1是铝焊盘、铜焊盘、镍焊盘、其组合、等等。管芯焊盘P1中的每一个可以是单层或者多层结构。在一些实施例中，一些管芯焊盘P1在其顶面上具有探针标记。半导体管芯100和上面的半导体管芯200称为“已知良好管芯”。在一些实施例中，管芯焊盘P1没有探针标记。
在一些实施例中，在形成管芯焊盘P1的操作期间，再分布图案118同时地形成在管芯焊盘P1旁边。例如，再分布图案118形成在邻接管芯焊盘P1的介电密封层E1上方。再分布图案118配置成在半导体管芯100周围扩展接触点，从而可以施加诸如焊球的凸块，并且可以扩展安装的热应力。在一些实施例中，管芯焊盘P1和再分布图案118通过溅射工艺、沉积工艺、电镀工艺、等等来形成。
之后，形成后钝化层122，以覆盖介电密封层E1、半导体管芯100的钝化层112和管芯焊盘P1、以及再分布图案118。在一些实施例中，后钝化层122包括氧化硅、氮化硅、苯并环丁烯(BCB)聚合物、聚酰亚胺(PI)、聚苯并恶唑(PBO)、其组合、等等，并且通过诸如旋涂、CVD、等等的合适的工艺来形成。在一些实施例中，钝化层112和后钝化层122包括相同的材料。在一些实施例中，钝化层112和后钝化层122包括不同的材料。
之后，实施对后钝化层122进行图案化的工艺，使得多个开口OP2形成在后钝化层122中，并且暴露半导体管芯100的管芯焊盘P1。在一些实施例中，实施光刻和蚀刻工艺，以形成开口OP2。然而，本公开并不限于此。在其他实施例中，实施激光钻孔工艺以形成开口OP2。
然后，导电端子或者凸块B形成在开口OP2内，并且电连接至半导体管芯100的管芯焊盘P1和管芯焊盘P1旁边的再分布图案118。在一些实施例中，一些凸块B设置在芯片区域内，并且与管芯焊盘P1物理接触，而一些凸块B设置在芯片区域外，并且与再分布图案118物理接触。在一些实施例中，凸块B包括焊料凸块，和/或可以包括金属柱(例如铜柱)、形成在金属柱上的焊帽、和/或等等。凸块B可以通过诸如蒸发、电镀、球滴、丝网印刷、等等的合适的工艺来形成。
参考图20，载体C2从介电密封层E2剥离。在一些实施例中，剥离工艺是激光剥离工艺或者合适的工艺。然后，粘附层或者接合膜FC2从介电密封层E2去除。在一些实施例中，去除工艺是蚀刻工艺和/或清洁工艺。
之后，晶圆切割工艺沿着切割线CL实施在图20的结构上，以切割穿过介电密封层E2、接合膜BF1、聚合物层115、和介电密封层E1。在晶圆切割工艺或者单个化工艺之后，相邻的半导体封装件20彼此分离，如图21所示。一些实施例的半导体封装件20由此完成。在一些实施例中，诸如印刷电路板(PCB)的板衬底、和/或诸如硅插件或者有机插件的插件衬底，可以提供在下方，并且通过凸块B接合至半导体封装件20。
图22至图23是示意性地示出根据本发明的一些实施例的半导体封装件的截面图。图22和图23的半导体封装件21和22分别类似于图21的半导体封装件20，其中相似的附图标记指代相似的元件。图22和图23的元件的材料和配置可以参考先前的实施例中所描述的类似元件的材料和配置。图22的半导体封装件21可以有利于降低成本和/或减小尺寸。图23的半导体封装件22可以有利于扩展引线和布线，并且因此提高产品的灵活性。
图22的半导体封装件21的形成方法类似于图12至图21中所描述的半导体封装件20的形成方法，其中形成如图16中所示的再分布层结构119的操作省略。在一些实施例中，如图21中所示，半导体管芯200通过接合结构120和接合结构220接合至半导体管芯100，但是如图21所示的接合通孔BV1可以可选地从接合结构120省略。例如，如图21中所示，接合焊盘BP11与半导体管芯200的接合焊盘BP21和半导体管芯100的贯穿衬底通孔103物理接触，而接合焊盘BP12与半导体管芯200的接合焊盘BP22和介电密封层E1物理接触。
图23的半导体封装件22的形成方法类似于图12至图21中所描述的半导体封装件20的形成方法，其中，在形成图14和图15中的介电密封层E1的操作之前，还包括形成贯穿介电通孔(TDV)111的操作。贯穿介电通孔111可以包括Cu、Ti、Ta、W、Ru、Co、Ni、等等、其合金、或其组合。在一些实施例中，贯穿介电通孔111通过电镀工艺形成。在一些实施例中，如图23所示，贯穿介电通孔111电连接至背面再分布层结构119和正面再分布图案118。
下面参考图10、图11、图20、图21、和图22阐释一些实施例的半导体封装件的结构。
在一些实施例中，半导体封装件10/11/20/21/22包括第一半导体管芯100、第二半导体管芯200、和多个凸块B。第一半导体管芯100具有彼此相对的有源正面S1和背面S2。第二半导体管芯200设置在第一半导体管芯100的背面S2，并且电连接至第一半导体管芯100。多个凸块B设置在第一半导体管芯100的正面S1，并且物理地连接第一半导体管芯100的第一管芯焊盘P1。在一些实施例中，第一半导体管芯100的总宽度W1小于第二半导体管芯200的总宽度W2。在一些实施例中，第一管芯焊盘P1包括铝焊盘。在一些实施例中，第一半导体管芯100的关键尺寸小于第二半导体管芯200的关键尺寸。
在一些实施例中，半导体封装件10/11/20/21/22还包括设置在第一半导体管芯100和第二半导体管芯200之间的第一接合结构120，并且第一接合结构120的边缘横向地延伸超出第一半导体管芯100的边缘。在一些实施例中，半导体封装件10/11/20/21/22还包括设置在第一接合结构120和第二半导体管芯200之间的第二接合结构220，其中第二接合结构220的边缘与第二半导体管芯200的边缘对准。在一些实施例中，第一接合结构120通过包括电介质至电介质接合和金属至金属接合的混合接合而接合至第二接合结构220。在一些实施例中，半导体封装件10/11/20/21/22还包括横向地密封第一半导体管芯100的第一介电密封层E1，和设置在第一半导体管芯100上方、并且横向地密封第二半导体管芯200的第二介电密封层E2。
在一些实施例中，半导体封装件10/20/22还包括设置在第一接合结构120和第二接合结构220之间的再分布层结构119。
在一些实施例中，半导体封装件20/21/22还包括设置在第一半导体管芯100的正面S1和第一半导体管芯100的第一管芯焊盘P1旁边的再分布图案118。在一些实施例中，半导体封装件22还包括穿过第一介电密封层E1、并且电连接至再分布层结构119和再分布图案118的贯穿介电通孔111。
上面的其中上部集成电路结构是单个半导体管芯的实施例是出于阐释的目的而提供的，不应解释为对本发明进行限制。在一些实施例中，上部集成电路结构是包括垂直地堆叠的多个管芯的管芯堆叠件。
图24是示意性地示出根据本发明的一些实施例的半导体封装件的截面图。图24的半导体封装件31类似于图11的半导体封装件11，其中相似的附图标记指代相似的元件。图24的元件的材料和配置可以参考先前的实施例中所描述的类似元件的材料和配置。图24的半导体封装件31可以有利于产品的灵活性。
如图24中所示，提供包括半导体管芯200-1和200-2的管芯堆叠件201，并且将其接合至半导体管芯100。在图24中，仅示出了两个半导体管芯200-1和200-2；然而，半导体管芯200-1和200-2的数量不受本公开的限制。在一些实施例中，半导体管芯200-1是面向半导体管芯100的最下部的管芯，而半导体管芯200-2是自半导体管芯100的最上部的管芯。一个或者多个半导体管芯可以介入于半导体管芯200-1和200-2之间。在一些实施例中，半导体管芯200-1包括半导体衬底202、设置在半导体衬底202上方的互连结构206、设置在互连结构206上方的接合结构220、以及穿过半导体衬底202和互连结构206并且电连接至下面的半导体管芯100和上面的半导体管芯200-2的贯穿衬底通孔(TSV)203。最上部的半导体管芯200-2可以具有类似于半导体管芯200-1的结构的结构。在一些实施例中，贯穿衬底通孔203可以根据需要从半导体管芯200-2省略。在一些实施例中，半导体管芯200-2通过以面对背配置的混合接合而接合至半导体管芯200-1。然而，本公开并不限于此。半导体管芯200-2可以通过焊料接头接合至半导体管芯200-1。半导体管芯200-2可以根据需要以面对面配置或者背对背配置而接合至半导体管芯200-1。在一些实施例中，如图10中所示的再分布层结构119可以根据工艺要求也包括在半导体封装件31中。
图25是示意性地示出根据本发明的其他实施例的半导体封装件的截面图。图25的半导体封装件32类似于图22的半导体封装件21，其中相似的附图标记指代相似的元件。图25的元件的材料和配置可以参考先前的实施例中所描述的类似元件的材料和配置。图25的半导体封装件32可以有利于产品的灵活性。
如图25所示，提供包括半导体管芯200-1和200-2的管芯堆叠件201，并且将其接合至半导体管芯100。图25的管芯堆叠件类似于图24的管芯堆叠件，其中相似的附图标记指代相似的元件。在一些实施例中，如图21中所示的再分布层结构119可以根据工艺要求也包括在半导体封装件32中。在一些实施例中，如图23中所示的贯穿介电通孔111可以也包括在半导体封装件32中。
在一些实施例中，支撑构件300也包括在本公开的半导体封装件中，如图26和图27中所示。
图26的半导体封装件41类似于图11的半导体封装件11，其中相似的附图标记指代相似的元件。图26的元件的材料和配置可以参考先前的实施例中所描述的类似元件的材料和配置。图26的半导体封装件41可以有利于产品的刚性。
如图26中所示，在半导体封装件41中，提供半导体管芯200a，并且将其接合至半导体管芯100。半导体管芯200a可以具有类似于图24中所描述的半导体管芯200-2的结构的结构。在一些实施例中，支撑构件300也包括在半导体封装件41中。支撑构件300设置在半导体管芯200a和介电密封层E2上方。在一些实施例中，支撑构件300可以是包括半导体材料、无机材料、绝缘材料、或其组合的衬底。例如，支撑构件300包括硅、陶瓷、石英、等等。在一些实施例中，支撑构件300包括形成在其上的接合膜302。支撑构件300可以是玻璃晶圆，而接合膜302可以是粘附材料。接合膜302可以包括氧化层、管芯连接胶带(DAF)、或者合适的粘附剂。支撑构件300通过接合膜302接合至半导体管芯200a的背面和介电密封层E2的暴露表面。在一些实施例中，覆盖接合膜可以提供在接合膜302和半导体衬底202之间、以及接合膜302和介电密封层E2之间，并且接合膜302可以通过熔融接合而接合至覆盖接合膜。在一些实施例中，半导体管芯200a可以由包括垂直地堆叠的多个管芯的管芯堆叠件来替代，并且支撑构件300接合至管芯堆叠件的最上部的管芯。在一些实施例中，如图10中所示的再分布层结构119可以根据工艺要求也包括在半导体封装件41中。
图27的半导体封装件42类似于图22的半导体封装件21，其中相似的附图标记指代相似的元件。图27的元件的材料和配置可以参考先前的实施例中所描述的类似元件的材料和配置。图27的半导体封装件42可以有利于产品的刚性。
如图27所示，在半导体封装件42中，提供半导体管芯200a，并且将其接合至半导体管芯100。半导体管芯200a可以具有类似于图25中所描述的半导体管芯200-2的结构的结构，其中相似的附图标记指代相似的元件。在一些实施例中，支撑构件300也包括在半导体封装件42中。在一些实施例中，支撑构件300包括形成在其上的接合膜302。支撑构件300和接合膜302的材料和配置可以参考图26中先前的实施例中所描述的材料和配置。
在一些实施例中，散热器400也包括在图28和图29的半导体封装件中。
图28的半导体封装件51类似于图26的半导体封装件41，其中相似的附图标记指代相似的元件。图28的元件的材料和配置可以参考先前的实施例中所描述的类似元件的材料和配置。图28的半导体封装件51有利于产品的刚性和散热效率。
如图28所示，散热器400也包括在半导体封装件51中。散热器400安装在支撑构件300上。在一些实施例中，散热器400可以由具有高导热性的材料形成，例如由钢、不锈钢、铜、其组合、等等形成。在一些实施例中，散热器400涂覆有金属，例如金、镍、等等。在一些实施例中，散热器400是单一连续材料。在一些实施例中，散热器400包括可以是相同或者不同材料的多片。在一些实施例中，散热器400是其中具有多个冷管的冷板。在一些实施例中，冷管可以跨半导体封装件以相等的间隔布置。在一些实施例中，冷管可以布置在半导体封装件的热点附近。在一些实施例中，散热器400通过热界面材料(TIM)402粘附至支撑构件300。在一些实施例中，TIM402可以包括环氧树脂、胶水、等等，并且可以是导热材料。在一些实施例中，TIM402可以是聚合材料、焊膏、铟焊膏、等等。在一些实施例中，支撑构件300和下面的接合膜302可以从图28的半导体封装件51省略，并且TIM402与半导体管芯200a的背面和介电密封层E2物理接触。在一些实施例中，如图10中所示的再分布层结构119可以根据工艺要求也包括在半导体封装件51中。
图29的半导体封装件52类似于图27的半导体封装件42，其中相似的附图标记指代相似的元件。图29的元件的材料和配置可以参考先前的实施例中所描述的类似元件的材料和配置。图29的半导体封装件52有利于产品的刚性和散热效率。
如图29所示，散热器400也包括在半导体封装件52中。在一些实施例中，散热器400通过热界面材料(TIM)402粘附至支撑构件300。散热器400和TIM402的材料和配置可以参考图28中先前的实施例中所描述的材料和配置。在一些实施例中，支撑构件300和下面的接合膜302可以从图29的半导体封装件52省略，并且TIM402与半导体管芯200a的背面和介电密封层E2物理接触。在一些实施例中，如图21中所示的再分布层结构119可以根据工艺要求也包括在半导体封装件52中。在一些实施例中，如图23中所示的贯通介电通孔111可以也包括在半导体封装件52中。
在图26和图27的实施例中，支撑构件300宽于下面的半导体管芯200a。例如，支撑构件300的宽度与下面的SoIC结构的总宽度相同，其等于半导体管芯200a的宽度和介电密封层E2的宽度。在图26和图27的实施例中，支撑构件300的底面与半导体管芯200a的背面和介电密封层E2的顶面物理接触。然而，本公开并不限于此。
在图30和图31的其他实施例中，支撑构件300窄于下面的半导体管芯200a。例如，支撑构件300的宽度小于下面的SoIC结构的总宽度。在图30和图31的半导体封装件61和62中，支撑构件300的底面与半导体管芯200a的背面物理接触，并且介电密封层E2横向地密封半导体管芯200a和支撑构件300的侧壁。
图32示出了根据一些实施例的形成半导体封装件的方法。虽然该方法示出和/或描述为一系列动作或者事件，但是应当理解的是，该方法不限于所示的顺序或者动作。因此，在一些实施例中，动作可以以不同于所示出的顺序执行，和/或可以同时执行。另外，在一些实施例中，所示的动作或者事件可以细分为多个动作或者事件，其可以在间隔开的时间执行，或者与其他动作或者子动作同时执行。在一些实施例中，可以省略一些所示的动作或者事件，并且可以包括其他未示出的动作或者事件。
在动作500处，提供第一半导体管芯，其中第一半导体管芯包括第一半导体衬底、穿过第一半导体衬底的第一贯穿衬底通孔、形成在第一半导体衬底的正面上方并且电连接至第一贯穿衬底通孔的第一互连结构、以及形成在第一互连结构上方并且电连接至第一互连结构的多个第一管芯焊盘。图1至图2示出了对应于动作500的一些实施例的截面图。图11、图24、图26、图28、和图30示出了对应于动作500的一些实施例的截面图。
在动作502处，第一介电密封层形成在第一半导体管芯周围。图3至图4示出了对应于动作502的一些实施例的截面图。图11、图24、图26、图28、和图30示出了对应于动作502的一些实施例的截面图。
在动作504处，再分布层结构形成在第一半导体管芯和第一介电密封层上方。图5示出了对应于动作504的一些实施例的截面图。动作504可以可选地省略，如图11、图24、图26、图28、和图30中所示。
在动作506处，第一接合结构形成在第一半导体管芯和第一介电密封层上方。图5示出了对应于动作506的一些实施例的截面图。图11、图24、图26、图28、和图30示出了对应于动作506的一些实施例的截面图。
在动作508处，第二半导体管芯接合至第一半导体管芯的第一半导体衬底的背面。图6示出了对应于动作508的一些实施例的截面图。图11、图24、图26、图28、和图30示出了对应于动作508的一些实施例的截面图。在一些实施例中，第二半导体管芯通过混合接合而接合至第一半导体管芯。
在动作510处，第三半导体管芯接合至第二半导体管芯。图24示出了对应于动作510的一些实施例的截面图。在一些实施例中，动作510可以根据需要可选地省略。在其他实施例中，动作510可以重复多次，直至期望数量的半导体管芯进行了垂直堆叠。在一些实施例中，第三半导体管芯通过混合接合而接合至第二半导体管芯。在其他实施例中，第三半导体管芯通过焊料接头而接合至第二半导体管芯。
在动作512处，第二介电密封层形成在第二半导体管芯周围。图7示出了对应于动作512的一些实施例的截面图。图11、图24、图26、图28、和图30示出了对应于动作512的一些实施例的截面图。在一些实施例中，第二介电密封层形成在第三半导体管芯周围，如图24中所示。
在动作514处，多个凸块形成在第一半导体管芯的第一管芯焊盘上方。图8至图10、图11、图24、图26、图28、和图30示出了对应于动作514的一些实施例的截面图。
在动作516处，支撑构件形成在第二半导体管芯上方。图26、图28、和图30示出了对应于动作516的一些实施例的截面图。动作516可以可选地省略。
在动作518处，散热器形成在支撑构件上方。图28示出了对应于动作518的一些实施例的截面图。动作518可以可选地省略。
图33示出了根据一些实施例的形成半导体封装件的方法。虽然该方法示出和/或描述为一系列动作或者事件，但是应当理解的是，该方法不限于所示的顺序或者动作。因此，在一些实施例中，动作可以以不同于所示出的顺序执行，和/或可以同时执行。另外，在一些实施例中，所示的动作或者事件可以细分为多个动作或者事件，其可以在间隔开的时间执行，或者与其他动作或者子动作同时执行。在一些实施例中，可以省略一些所示的动作或者事件，并且可以包括其他未示出的动作或者事件。
在动作600处，提供第一半导体管芯，其中第一半导体管芯包括第一半导体衬底、穿过第一半导体衬底的第一贯穿衬底通孔、以及形成在第一半导体衬底上方并且电连接至第一贯穿衬底通孔的第一互连结构。图12至图13示出了对应于动作600的一些实施例的截面图。图22-图23、图25、图27、图29、和图31示出了对应于动作600的一些实施例的截面图。
在动作602处，第一介电密封层形成在第一半导体管芯周围。图14至图15示出了对应于动作602的一些实施例的截面图。图22-图23、图25、图27、图29、和图31示出了对应于动作602的一些实施例的截面图。
在动作604处，再分布层结构形成在第一半导体管芯和第一介电密封层上方。图16示出了对应于动作604的一些实施例的截面图。图23示出了对应于动作604的一些实施例的截面图。动作604可以可选地省略，如图22、图25、图27、图29、和图31中所示。
在动作606处，第一接合结构形成在第一半导体管芯和第一介电密封层上方。图16示出了对应于动作606的一些实施例的截面图。图22-图23、图25、图27、图29、和图31示出了对应于动作606的一些实施例的截面图。
在动作608处，第二半导体管芯接合至第一半导体管芯的第一半导体衬底的背面。图17示出了对应于动作608的一些实施例的截面图。图22-23、图25、图27、图29、和图31示出了对应于动作608的一些实施例的截面图。在一些实施例中，第二半导体管芯通过混合接合而接合至第一半导体管芯。
在动作610处，第三半导体管芯接合至第二半导体管芯。图25示出了对应于动作610的一些实施例的截面图。在一些实施例中，动作610可以可选地省略。在一些实施例中，动作610可以重复多次，直至期望数量的半导体管芯进行了垂直堆叠。在一些实施例中，第三半导体管芯通过混合接合而接合至第二半导体管芯。在一些实施例中，第三半导体管芯通过焊料接头而接合至第二半导体管芯。
在动作612处，第二介电密封层形成在第二半导体管芯周围。图18示出了对应于动作612的一些实施例的截面图。图22-图23、图25、图27、图29、和图31示出了对应于动作612的一些实施例的截面图。在一些实施例中，第二介电密封层形成在第三半导体管芯周围，如图25中所示。
在动作614处，多个第一管芯焊盘形成在第一半导体衬底的正面上方和第一半导体管芯的芯片区域内，其中多个第一管芯焊盘物理地连接第一互连结构的顶部金属图案。图19示出了对应于动作614的一些实施例的截面图。图22-图23、图25、图27、图29、和图31示出了对应于动作614的一些实施例的截面图。
在动作616处，多个再分布图案形成在多个第一管芯焊盘旁边和第一半导体管芯的芯片区域外。图19至图21示出了对应于动作616的一些实施例的截面图。图22-图23、图25、图27、图29、和图31示出了对应于动作616的一些实施例的截面图。在一些实施例中，动作614和动作616同时实施，因此第一管芯焊盘和再分布图案由相同的材料制成。在一些实施例中，动作614和动作616可以分开实施，因此第一管芯焊盘和再分布图案可以包括不同的材料。动作616可以可选地省略。
在动作618处，多个凸块形成在第一半导体管芯的第一管芯焊盘和再分布图案上方。图19至图21示出了对应于动作618的一些实施例的截面图。图22-图23、图25、图27、图29、和图31示出了对应于动作618的一些实施例的截面图。
在动作620处，支撑构件形成在第二半导体管芯上方。图27、图29、和图31示出了对应于动作620的一些实施例的截面图。动作620可以可选地省略。
在动作622处，散热器形成在支撑构件上方。图29示出了对应于动作622的一些实施例的截面图。动作622可以可选地省略。
以上所提到的“管芯焊盘优先”工艺和“管芯焊盘次后”工艺可以施加至其他半导体封装件，从而通过将关键半导体管芯放置成靠近焊球阵列来提高信号传输性能。
图34至图39是示意性地示出根据本发明的一些实施例的半导体封装件的截面图。
图34至图39中的半导体封装件的一些元件类似于以上所描述的那些，其中相似的附图标记指代相似的元件。图34至图39的那些元件的材料和配置可以参考先前的实施例中所描述的类似元件的材料和配置。
如图34中所示，半导体封装件71包括两个半导体管芯100、介电密封层E1、和凸块B。半导体封装件71通过“管芯焊盘优先”工艺形成。
两个半导体管芯100并排设置。在一些实施例中，半导体管芯100中的每一个包括正面S1(例如正面)和与正面S1相对的背面S2(例如背面)。在一些实施例中，半导体管芯100包括半导体衬底102、至少一个器件T1、互连结构106、管芯焊盘P1、和钝化层112。半导体管芯100的元件的材料和配置可以参考图11的先前的实施例。贯穿说明书，半导体管芯100的对应于半导体衬底具有器件或者有源层的一面的一面称为正面。
在一些实施例中，相邻的半导体管芯100可以具有相同的功能。在一些实施例中，相邻的半导体管芯100可以具有不同的功能。另外，半导体管芯100中的一个的尺寸可以与半导体管芯100中的另一个的尺寸相同或者不同。尺寸可以是高度、宽度、大小、俯视面积、或其组合。
介电密封层E1位于半导体管芯100周围和之间。在一些实施例中，介电密封层E1的顶面在工艺变化范围内与半导体管芯100的半导体衬底102暴露表面基本齐平，并且介电密封层E1的底面在工艺变化范围内与半导体管芯100的钝化层112的暴露表面基本齐平。
凸块B设置在半导体管芯100的正面S1，并且与半导体管芯100的管芯焊盘P1物理接触。凸块B、管芯焊盘P1、和钝化层112之间的元件关系可以参考图11的先前的实施例。
在一些实施例中，半导体封装件71还包括设置在半导体管芯100中的一个的上方的半导体管芯200a。半导体管芯200a可以电连接至半导体管芯100中的一个或者多个。在一些实施例中，半导体管芯200a包括有源器件或者功能器件，例如晶体管、电容器、电阻器、二极管、光电二极管、熔断器器件、和/或其他类似器件。在一些示例中，半导体管芯200a称为“包括器件的管芯”。在一些实施例中，半导体管芯200a包括半导体衬底202、设置在半导体衬底202上方的互连结构206、以及设置在互连结构206上方的接合结构220。在一些实施例中，接合结构220包括至少一个接合膜BF2和嵌入在接合膜BF2中的接合金属部件。在一些实施例中，接合金属部件包括接合焊盘BP21和BP22。半导体管芯200a的元件的材料和配置可以参考图26的先前的实施例。
在一些实施例中，半导体封装件71还包括设置在半导体管芯100中的另一个的上方的半导体管芯400。半导体管芯400可以电连接至半导体管芯100中一个或者多个。在一些实施例中，半导体管芯400具有类似于半导体管芯200a的结构的结构。例如，半导体管芯400包括半导体衬底402、设置在半导体衬底402上方的可选的互连结构406、以及设置在互连结构406上方的接合结构420。互连结构406可以省略。在一些实施例中，接合结构420包括至少一个接合膜BF4和嵌入在接合膜BF2中的接合金属部件。在一些实施例中，接合金属部件包括接合焊盘BP41和BP42。
在一些实施例中，半导体管芯400是伪半导体管芯。在本文中，术语“伪半导体管芯”表示非操作管芯、配置为非使用的管芯、其中不具有器件的管芯、或者仅用于将管芯堆叠件中的另外两个管芯电连接在一起的管芯。在一些实施例中，伪半导体管芯基本上没有任何诸如晶体管、电容器、电阻器、二极管、光电二极管、熔断器器件、和/或其他类似器件的有源器件或者功能器件。在一些实施例中，伪半导体管芯可以构造成不具有有源组件、无源组件、或者两者。在一些示例中，半导体管芯400称为“无器件的管芯”。然而，伪半导体管芯可以包括电连接至(一些)相邻管芯的导电部件。在一些实施例中，导电部件包括贯穿衬底通孔、金属导线、金属插塞、金属焊盘、或其组合。具体地，虽然本申请的伪半导体管芯不包括器件，但是其可以用作相邻管芯之间的电连接器。在一些实施例中，伪半导体管芯的施加可以用于加强封装件和保护封装件免于变形。在一些实施例中，本申请的伪半导体管芯可以配置成用以降低热膨胀系数(CTE)失配，并且改善所得封装件的翘曲轮廓。然而，本公开并不限于此。在其他实施例中，半导体管芯400根据工艺要求是“有源半导体管芯”或者“包括器件的管芯”。
在一些实施例中，半导体封装件71还包括桥接结构300。桥接结构300提供不同管芯、管芯堆叠件、或者插件之间的电布线。桥接结构300可以包括设置在诸如硅衬底的半导体衬底之上/之中的布线图案。布线图案包括贯穿衬底通孔、导线、通孔、焊盘、和/或连接器。在一些示例中，桥接结构300称为“连接结构”、“桥芯片”、或者“硅桥”。
在一些实施例中，桥接结构300电连接至在半导体管芯200a和400之间跨介电密封层E1形成的半导体管芯100。换句话说，桥接结构300、半导体管芯200a和400位于同一层级。在一些实施例中，从俯视图观察，桥接结构300与半导体管芯100中的至少一个部分地重叠。在一些实施例中，桥接结构300具有类似于半导体管芯200a的结构。例如，桥接结构300包括半导体衬底302、设置在半导体衬底302上方的可选的互连结构306、和设置在互连结构306上方的接合结构320。互连结构306可以省略。在一些实施例中，接合结构320包括至少一个接合膜BF3和嵌入在接合膜BF32中的接合金属部件。在一些实施例中，接合金属部件包括接合焊盘BP31和BP32。
在一些实施例中，半导体管芯100在同一层级，并且半导体管芯200a和400以及桥接结构300位于同一层级。在一些示例中，半导体管芯100可以认为是“第一层半导体管芯”，而半导体管芯200a和400以及桥接结构300可以认为是“第二层半导体管芯”。
在一些实施例中，半导体封装件71还包括位于第一层半导体管芯和第二层半导体管芯之间的接合结构120。在一些实施例中，接合结构120包括至少一个接合膜BF1和嵌入在接合膜BF1中的接合金属部件。在一些实施例中，接合金属部件包括接合焊盘BP11、BP12、BP13、BP14、BP15、和BP16。
在一些实施例中，半导体管芯200a通过接合结构220和接合结构120接合至对应的半导体管芯100。具体地，接合结构220的接合焊盘BP21和BP22接合至接合结构120的接合焊盘BP11和BP12，并且接合结构220的接合膜BF2接合至接合结构120的接合膜BF1。这种接合可以称为“混合接合”。在一些实施例中，接合焊盘BP11和BP21称为“有源接合焊盘”，因为它们配置成提供相邻管芯之间的接合和电功能两者。接合焊盘BP12和BP22称为“伪接合焊盘”，因为它们配置成仅提供相邻管芯之间的接合功能。
在一些实施例中，桥接结构300通过接合结构320和接合结构120接合至对应的半导体管芯100。具体地，接合结构320的接合焊盘BP31和BP32接合至接合结构120的接合焊盘BP13和BP14，并且接合结构320的接合膜BF3接合至接合结构120的接合膜BF1。这种接合称为“混合接合”。在一些实施例中，接合焊盘BP13和BP31称为“有源接合焊盘”，因为它们配置成提供相邻管芯之间的接合和电功能两者。接合焊盘BP14和BP32称为“伪接合焊盘”，因为它们配置成仅提供相邻管芯之间的接合功能。
在一些实施例中，半导体管芯400通过接合结构420和接合结构120接合至对应的半导体管芯100。例如，接合结构420的接合焊盘BP41和BP42接合至接合结构120的接合焊盘BP15和BP16，并且接合结构420的接合膜BF4接合至接合结构120的接合膜BF1。这种接合称为“混合接合”。在一些实施例中，接合焊盘BP15和BP41称为“有源接合焊盘”，因为它们配置成提供相邻管芯之间的接合和电功能两者。接合焊盘BP16和BP42称为“伪接合焊盘”，因为它们配置成仅提供相邻管芯之间的接合功能。
介电密封层E2也包括在半导体封装件71中。在一些实施例中，介电密封层E2位于半导体管芯200a、桥接结构300、和半导体400周围和之间。在一些实施例中，介电密封层E2的顶面在工艺变化范围内与半导体管芯200a、桥接结构300、和半导体400的半导体衬底的暴露表面基本齐平，并且介电密封层E2的底面在工艺变化范围内与接合结构220、320、和420的接合膜基本齐平。
在一些实施例中，如图10中所示的再分布层结构119可以也包括在半导体封装件71中。在这种情况下，再分布层结构可以设置在接合结构120与介电密封层E1和半导体管芯100中的每一个之间。在一些实施例中，如图26、图28、和图30中所示的支撑构件300和/或散热器400可以可选地包括在半导体封装件71中。
图35的半导体封装件72类似于图34的半导体封装件71，它们之间的区别在于第一层半导体管芯的管芯焊盘的形成顺序。例如，图34的半导体封装件71通过“管芯焊盘优先”工艺形成，而图35的半导体封装件72通过“管芯焊盘次后”工艺形成，因此它们之间的区别在下面进行详细描述，而相似性在此不再赘述。图35的元件的材料和配置可以参考先前的实施例中所描述的类似元件的材料和配置。在图35的实施例中，再分布图案118设置在半导体管芯100的管芯焊盘P1周围和之间，钝化层112形成为跨半导体管芯100和介电密封层E2，凸块B穿透钝化层112并且电连接至管芯焊盘P1和再分布图案118。
在一些实施例中，如图21中所示的再分布层结构119可以根据工艺要求也包括在半导体封装件72中。在这种情况下，再分布层结构可以设置在接合结构120与介电密封层E1和半导体管芯100中的每一个之间。在一些实施例中，如图27、图29、和图31中所示的支撑构件300和/或散热器400可以根据需要可选地包括在半导体封装件72中。在一些实施例中，如图23中所示的贯穿介电通孔111可以根据需要也包括在半导体封装件72中。
图36的半导体封装件81类似于图34的半导体封装件71，其中半导体管芯400和半导体管芯100之间的接合机制有所不同。在图34的半导体封装件71中，半导体管芯400通过接合结构420和接合结构120的混合接合而接合至半导体管芯100。然而，在图36的半导体封装件81中，半导体管芯400是通过接合结构420和接合结构120的熔融接合而接合至半导体管芯100。例如，图34的接合焊盘BP15和BP16从接合结构120省略，以及图34的接合焊盘BP41和BP42从接合结构420省略。
图37的半导体封装件82类似于图35的半导体封装件72，其中半导体管芯400和半导体管芯100之间的接合机制有所不同。在图35的半导体封装件72中，半导体管芯400通过接合结构420和接合结构120的混合接合而接合至半导体管芯100。然而，在图37的半导体封装件82中，半导体管芯400是通过接合结构420和接合结构120的熔融接合而接合至半导体管芯100。例如，图35的接合焊盘BP15和BP16从接合结构120省略，以及图35的接合焊盘BP41和BP42从接合结构420省略。
图38的半导体封装件91类似于图36的半导体封装件81，其中半导体封装件的第二层层级的管芯配置有所不同。例如，图36的半导体封装件81中的半导体管芯200a由管芯堆叠件201替代，并且介电密封层E2形成为覆盖管芯堆叠件201的侧壁和顶部以及半导体管芯400和桥接结构300的侧壁和顶部。管芯堆叠件201的元件的材料和配置可以参考图24的先前的实施例。
图39的半导体封装件92类似于图37的半导体封装件82，其中半导体封装件的第二层层级的管芯配置有所不同。例如，图37的半导体封装件82中的半导体管芯200a由管芯堆叠件201替代，并且介电密封层E2形成为覆盖管芯堆叠件201的侧壁和顶部以及半导体管芯400和桥接结构300的侧壁和顶部。管芯堆叠件201的元件的材料和配置可以参考图25的先前的实施例。
下面参考图34-图39阐释一些实施例的半导体封装件的结构。
在一些实施例中，半导体结构71/72/81/82/91/92包括两个第一半导体管芯100、凸块B、第一接合结构120、和桥接结构300。两个第一半导体管芯100并排设置。凸块B设置在第一半导体管芯100的正面S1，并且与第一半导体管芯100的第一管芯焊盘P1物理接触。第一接合结构120设置在第一半导体管芯100的背面S2，并且横向地延伸超出第一半导体管芯100，其中正面S1和背面S2相对。桥接结构300设置在第一接合结构120上方和第一半导体管芯100之间。
在一些实施例中，半导体封装件71/72/81/82/91/92还包括设置在第一接合结构120上方并且对应于第一半导体管芯100中的一个的第二半导体管芯200a或者管芯堆叠件201。
在一些实施例中，在半导体封装件71/72中，第二半导体管芯200a或者管芯堆叠件201包括第二接合结构220，并且第二接合结构220通过混合接合而接合至第一接合结构120。
在一些实施例中，在半导体封装件71/72/81/82/91/92中，半导体封装件还包括设置在第一接合结构120上方并且对应于第一半导体管芯100中的一个的伪半导体管芯400。
在一些实施例中，在半导体封装件71/72中，伪半导体管芯400包括第三接合结构420，并且第三接合结构420通过混合接合而接合至第一接合结构120。
在一些实施例中，在半导体封装件81/82/91/92中，伪半导体管芯400包括第三接合结构420，并且第三接合结构420通过熔融接合而接合至第一接合结构120。
图40示出了根据一些实施例的形成半导体封装件的方法。虽然该方法示出和/或描述为一系列动作或者事件，但是应当理解的是，该方法不限于所示的顺序或者动作。因此，在一些实施例中，动作可以以不同于所示出的顺序执行，和/或可以同时执行。另外，在一些实施例中，所示的动作或者事件可以细分为多个动作或者事件，其可以在间隔开的时间执行，或者与其他动作或者子动作同时执行。在一些实施例中，可以省略一些所示的动作或者事件，并且可以包括其他未示出的动作或者事件。
图40的工艺流程类似于图32的工艺流程，区别在于在第一层层级和第二层层级的半导体管芯的数量。以下动作的一些组件可能未在图34、图36、和图38中示出，但它们可以根据需要包括在半导体封装件中。
在动作700处，提供第一层管芯，其中第一层管芯包括并排布置的两个第一半导体管芯，并且第一半导体管芯中的每一个包括第一半导体衬底、穿过第一半导体衬底的第一贯穿衬底通孔、形成在第一半导体衬底的正面上方并且电连接至第一贯穿衬底通孔的第一互连结构、以及形成在第一互连结构上方并且电连接至第一互连结构的多个第一管芯焊盘。
在动作702处，第一介电密封层形成在第一半导体管芯周围。
在动作704处，再分布层结构形成在第一半导体管芯和第一介电密封层上方。动作704可以可选地省略。
在动作706处，第一接合结构形成在第一半导体管芯和第一介电密封层上方。
在动作708处，第二层管芯接合至第一接合结构，其中第二层管芯包括第二半导体管芯或者管芯堆叠件、桥接结构、和第三半导体管芯。
在动作710处，第二介电密封层形成在第二层管芯周围。
在动作712处，多个凸块形成在第一半导体管芯的第一管芯焊盘上方。
在动作714处，支撑构件形成在第二层管芯上方。动作714可以可选地省略。
在动作716处，散热器形成在支撑构件上方。动作716可以可选地省略。
图41示出了根据一些实施例的形成半导体封装件的方法。虽然该方法示出和/或描述为一系列动作或者事件，但是应当理解的是，该方法不限于所示的顺序或者动作。因此，在一些实施例中，动作可以以不同于所示出的顺序执行，和/或可以同时执行。另外，在一些实施例中，所示的动作或者事件可以细分为多个动作或者事件，其可以在间隔开的时间执行，或者与其他动作或者子动作同时执行。在一些实施例中，可以省略一些所示的动作或者事件，并且可以包括其他未示出的动作或者事件。
图41的工艺流程类似于图33的工艺流程，其中在第一层层级和第二层层级的半导体管芯的数量有所不同。以下动作的一些组件可能未在图35、图37、和图39中示出，但是它们可以包括在半导体封装件中。
在动作800处，提供第一层管芯，其中第一层管芯包括并排布置的两个第一半导体管芯，并且第一半导体管芯中的每一个包括第一半导体衬底、穿过第一半导体衬底的第一贯穿衬底通孔、以及形成在第一半导体衬底上方并且电连接至第一贯穿衬底通孔的第一互连结构。
在动作802处，第一介电密封层形成在第一半导体管芯周围。
在动作804处，再分布层结构形成在第一半导体管芯和第一介电密封层上方。动作804可以可选地省略。
在动作806处，第一接合结构形成在第一半导体管芯和第一介电密封层上方。
在动作808处，第二层管芯接合至第一接合结构，其中第二层管芯包括第二半导体管芯或者管芯堆叠件、桥接结构、和第三半导体管芯。
在动作810处，第二介电密封层形成在第二层管芯周围。
在动作812处，多个第一管芯焊盘形成在第一半导体衬底的正面上方和第一半导体管芯中的每一个的芯片区域内，其中多个第一管芯焊盘物理地连接第一互连结构的顶部金属图案。
在动作814处，多个再分布图案形成在多个第一管芯焊盘旁边和第一半导体管芯中的每一个的芯片区域外。动作814可以可选地省略。
在动作816处，多个凸块形成在第一半导体管芯的第一管芯焊盘和再分布图案上方。
在动作818处，支撑构件形成在第二层管芯上方。动作818可以可选地省略。
在动作820处，散热器形成在支撑构件上方。动作820可以可选地省略。
还可以包括其他特征和工艺。例如，可以包括测试结构，以辅助3D封装件或者3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或者衬底上的测试焊盘，其允许使用探针和/或探针卡等对3D封装或者3DIC进行测试。验证测试可以实施在中间结构以及最终结构上。另外，本文公开的结构和方法可以与结合了已知良好的管芯的中间验证的测试方法结合使用，以增加产量并且降低成本。
根据本公开的一些实施例，一种半导体封装件，包括第一半导体管芯、第二半导体管芯、和多个凸块。第一半导体管芯具有彼此相对的正面和背面。第二半导体管芯设置在第一半导体管芯的背面，并且电连接至第一半导体管芯。多个凸块设置在第一半导体管芯的正面，并且物理接触第一半导体管芯的第一管芯焊盘。另外，第一半导体管芯的尺寸小于第二半导体管芯的尺寸。
在一些实施例中，所述第一管芯焊盘包括铝焊盘。在一些实施例中，尺寸包括高度、长度、宽度、俯视面积、或其组合。在一些实施例中，半导体封装件还包括：第一接合结构，设置在所述第一半导体管芯和所述第二半导体管芯之间，其中，所述第一接合结构的边缘横向地延伸超出所述第一半导体管芯的边缘。在一些实施例中，半导体封装件还包括：第二接合结构，设置在所述第一接合结构和所述第二半导体管芯之间，其中，所述第二接合结构的边缘与所述第二半导体管芯的边缘对准。在一些实施例中，第一接合结构通过混合接合而接合至所述第二接合结构。在一些实施例中，半导体封装件还包括：再分布图案，设置在所述第一半导体管芯的所述正面和所述第一半导体管芯的所述第一管芯焊盘旁边。在一些实施例中，半导体封装件还包括：第一介电密封层，横向地密封所述第一半导体管芯；第二介电密封层，设置在所述第一半导体管芯上方，并且横向地密封所述第二半导体管芯；以及支撑构件，设置在所述第二半导体管芯和所述第二介电密封层上方。在一些实施例中，半导体封装件还包括：第一介电密封层，横向地密封所述第一半导体管芯；支撑构件，设置在所述第二半导体管芯上方；以及第二介电密封层，设置在所述第一半导体管芯上方，并且横向地密封所述第二半导体管芯和所述支撑构件。在一些实施例中，半导体封装件还包括：第三半导体管芯，设置在所述第二半导体管芯上方，并且通过混合接合而接合至所述第二半导体管芯。
根据本公开的一些实施例，半导体结构包括两个第一半导体管芯、凸块、第一接合结构、和桥接结构。两个第一半导体管芯并排设置。凸块设置在第一半导体管芯的正面，并且与第一半导体管芯的第一管芯焊盘物理接触。第一接合结构设置在第一半导体管芯的背面，并且横向地延伸超出第一半导体管芯，其中正面与背面相对。桥接结构设置在第一接合结构上方，并且位于第一半导体管芯之间。
在一些实施例中，第二半导体管芯或者管芯堆叠件，设置在所述第一半导体管芯中的一个上方的所述第一接合结构上方。在一些实施例中，第二半导体管芯或者所述管芯堆叠件包括第二接合结构，其中，所述第二接合结构通过混合接合而接合至所述第一接合结构。在一些实施例中，半导体结构还包括：伪半导体管芯，设置在所述第一接合结构上方，并且对应于所述第一半导体管芯中的一个。在一些实施例中，伪半导体管芯包括第三接合结构，其中，所述第三接合结构通过熔融接合而接合至所述第一接合结构。在一些实施例中，伪半导体管芯包括第三接合结构，其中，所述第三接合结构通过混合接合而接合至所述第一接合结构。
根据本公开的一些实施例，一种形成半导体封装件的方法包括以下操作。提供第一半导体管芯，其中第一半导体管芯包括第一半导体衬底、穿透第一半导体衬底的第一贯穿衬底通孔、以及形成在第一半导体衬底上方并且电连接至第一贯穿衬底通孔的第一互连结构。第二半导体管芯接合至第一半导体管芯的第一半导体衬底的背面。多个第一管芯焊盘形成在第一半导体衬底的正面上方和第一半导体管芯的芯片区域内，其中多个第一管芯焊盘物理地连接第一互连结构的顶部金属图案。多个凸块形成在第一管芯焊盘上方。
在一些实施例中，形成半导体封装件的方法还包括：在所述多个第一管芯焊盘旁边和所述第一半导体管芯的所述芯片区域外形成多个再分布图案。在一些实施例中，形成半导体封装件的方法还包括：在提供所述第一半导体管芯之后、并且在将所述第二半导体管芯接合至所述第一半导体管芯的所述第一半导体衬底的所述背面之前：在所述第一半导体管芯周围形成第一介电密封层；以及在所述第一半导体管芯和所述第一介电密封层上方形成第一接合结构。在一些实施例中，形成半导体封装件的方法还包括：在形成所述第一介电密封层之后、并且在形成所述第一接合结构之前，在所述第一半导体管芯和所述第一介电密封层上方形成再分布层结构。
前面概述了若干实施例的特征，使得本领域的技术人员可以更好地理解本公开的各个方面。本领域的技术人员应该理解，他们可以容易地使用本公开作为用于设计或修改用于执行与本公开相同或类似的目的和/或实现相同或类似优点的其他工艺和结构的基础。本领域的技术人员还应该意识到，这种等效结构不背离本公开的精神和范围，并且可以进行各种改变、替换和变更而不背离本公开的精神和范围。

Claims (10)

1.一种半导体封装件，包括：
第一半导体管芯，具有正面和与所述正面相对的背面；
第二半导体管芯，设置在所述第一半导体管芯的所述背面，并且电连接至所述第一半导体管芯，所述第二半导体管芯的正面面向所述第一半导体管芯；以及
多个凸块，设置在所述第一半导体管芯的所述正面，并且物理地接触所述第一半导体管芯的第一管芯焊盘，其中，所述第一半导体管芯的尺寸小于所述第二半导体管芯的尺寸。
2.根据权利要求1所述的半导体封装件，其中，所述第一管芯焊盘包括铝焊盘。
3.根据权利要求1所述的半导体封装件，其中，所述尺寸包括高度、长度、宽度、俯视面积、或其组合。
4.根据权利要求1所述的半导体封装件，还包括：第一接合结构，设置在所述第一半导体管芯和所述第二半导体管芯之间，其中，所述第一接合结构的边缘横向地延伸超出所述第一半导体管芯的边缘。
5.根据权利要求4所述的半导体封装件，还包括：第二接合结构，设置在所述第一接合结构和所述第二半导体管芯之间，其中，所述第二接合结构的边缘与所述第二半导体管芯的边缘对准。
6.根据权利要求5所述的半导体封装件，其中，所述第一接合结构通过混合接合而接合至所述第二接合结构。
7.根据权利要求1所述的半导体封装件，还包括：再分布图案，设置在所述第一半导体管芯的所述正面和所述第一半导体管芯的所述第一管芯焊盘旁边。
8.根据权利要求1所述的半导体封装件，还包括：
第一介电密封层，横向地密封所述第一半导体管芯；
第二介电密封层，设置在所述第一半导体管芯上方，并且横向地密封所述第二半导体管芯；以及
支撑构件，设置在所述第二半导体管芯和所述第二介电密封层上方。
9.一种半导体封装件，包括：
两个第一半导体管芯，并排设置；
凸块，设置在所述第一半导体管芯的正面，并且与所述第一半导体管芯的第一管芯焊盘物理接触；
第一接合结构，设置在所述第一半导体管芯的背面，并且横向地延伸超出所述第一半导体管芯，其中，所述正面与所述背面相对；以及
桥接结构，设置在所述第一接合结构上方，并且位于所述第一半导体管芯之间。
10.一种形成半导体封装件的方法，包括：
将第二半导体管芯接合至第一半导体管芯的第一半导体衬底的背面，其中，第一贯穿衬底通孔穿透所述第一半导体衬底，并且第一互连结构位于所述第一半导体衬底上方并且电连接至所述第一贯通衬底通孔；
在所述第一半导体衬底的正面上方和所述第一半导体管芯的芯片区域内形成多个第一管芯焊盘，其中，所述多个第一管芯焊盘物理地连接所述第一互连结构的顶部金属图案；以及
在所述第一管芯焊盘上方形成多个凸块。
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Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8883561B2 (en) 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US8970023B2 (en) * 2013-02-04 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming same
KR20150053088A (ko) * 2013-11-07 2015-05-15 에스케이하이닉스 주식회사 반도체 소자 및 제조 방법
KR102245003B1 (ko) * 2014-06-27 2021-04-28 삼성전자주식회사 오버행을 극복할 수 있는 반도체 패키지 및 그 제조방법
KR102360381B1 (ko) * 2014-12-01 2022-02-11 삼성전자주식회사 적층 구조를 갖는 반도체 소자 및 그 제조방법
US9768145B2 (en) * 2015-08-31 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multi-die package structures including redistribution layers
US9899355B2 (en) 2015-09-30 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional integrated circuit structure
US9893042B2 (en) * 2015-12-14 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9741695B2 (en) * 2016-01-13 2017-08-22 Globalfoundries Inc. Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding
DE102016116083A1 (de) 2016-08-30 2018-03-01 Kwiggle®Bike GmbH Rahmenteil für ein Fahrzeug
US10833052B2 (en) 2016-10-06 2020-11-10 Micron Technology, Inc. Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods
US20220238440A1 (en) * 2016-12-29 2022-07-28 Intel Corporation Bare-die smart bridge connected with copper pillars for system-in-package apparatus
US10199356B2 (en) * 2017-02-24 2019-02-05 Micron Technology, Inc. Semiconductor device assembles with electrically functional heat transfer structures
US10529698B2 (en) * 2017-03-15 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming same
US10879214B2 (en) 2017-11-01 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Die stack structure and method of fabricating the same
US10535636B2 (en) 2017-11-15 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating passive devices in package structures
US10141259B1 (en) * 2017-12-22 2018-11-27 Micron Technology, Inc. Semiconductor devices having electrically and optically conductive vias, and associated systems and methods
US10510629B2 (en) * 2018-05-18 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
US10651131B2 (en) * 2018-06-29 2020-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Supporting InFO packages to reduce warpage
US11114383B2 (en) * 2018-10-23 2021-09-07 Micron Technology, Inc. Semiconductor devices having integrated optical components
KR102593085B1 (ko) * 2018-11-21 2023-10-24 삼성전자주식회사 반도체 장치, 반도체 패키지 및 이의 제조 방법
US10811390B2 (en) * 2019-01-21 2020-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Die stack structure and method of fabricating the same and package
US11121052B2 (en) 2019-01-31 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out device, 3D-IC system, and method
TWI709212B (zh) 2019-03-05 2020-11-01 台灣積體電路製造股份有限公司 晶圓接合結構及其形成方法
US11189599B2 (en) 2019-05-30 2021-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. System formed through package-in-package formation
US20200402942A1 (en) 2019-06-24 2020-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method manufacturing the same
KR20210013429A (ko) * 2019-07-25 2021-02-04 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
KR20210048638A (ko) * 2019-10-23 2021-05-04 삼성전자주식회사 반도체 패키지
US11239203B2 (en) * 2019-11-01 2022-02-01 Xilinx, Inc. Multi-chip stacked devices
KR20210072181A (ko) * 2019-12-06 2021-06-17 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US11239174B2 (en) * 2019-12-27 2022-02-01 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US11605597B2 (en) * 2020-04-17 2023-03-14 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
KR20210151569A (ko) * 2020-06-05 2021-12-14 삼성전자주식회사 반도체 장치 및 이를 포함하는 반도체 패키지
US11545434B2 (en) * 2020-06-05 2023-01-03 Intel Corporation Vertical die-to-die interconnects bridge
US11710688B2 (en) * 2020-07-07 2023-07-25 Mediatek Inc. Semiconductor package structure
US11587894B2 (en) * 2020-07-09 2023-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package and method of fabricating the same
KR20220007443A (ko) * 2020-07-10 2022-01-18 삼성전자주식회사 반도체 패키지
KR20220008093A (ko) * 2020-07-13 2022-01-20 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
KR20220030685A (ko) * 2020-09-03 2022-03-11 삼성전자주식회사 반도체 패키지
KR20220058683A (ko) * 2020-10-29 2022-05-10 삼성전자주식회사 반도체 패키지
KR20220067212A (ko) * 2020-11-17 2022-05-24 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
KR20220081036A (ko) * 2020-12-08 2022-06-15 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US20220199539A1 (en) * 2020-12-18 2022-06-23 Intel Corporation Microelectronic structures including bridges
US20220199575A1 (en) * 2020-12-18 2022-06-23 Intel Corporation Microelectronic structures including bridges
US20220199562A1 (en) * 2020-12-22 2022-06-23 Intel Corporation Assembly of 2xd module using high density interconnect bridges
CN112687619A (zh) * 2020-12-25 2021-04-20 上海易卜半导体有限公司 形成半导体封装件的方法及半导体封装件

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