TW202240840A - 半導體封裝及其形成方法 - Google Patents
半導體封裝及其形成方法 Download PDFInfo
- Publication number
- TW202240840A TW202240840A TW110124364A TW110124364A TW202240840A TW 202240840 A TW202240840 A TW 202240840A TW 110124364 A TW110124364 A TW 110124364A TW 110124364 A TW110124364 A TW 110124364A TW 202240840 A TW202240840 A TW 202240840A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor
- die
- semiconductor die
- bonding
- bonding structure
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05157—Cobalt [Co] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05181—Tantalum [Ta] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05184—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05657—Cobalt [Co] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05676—Ruthenium [Ru] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05681—Tantalum [Ta] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05684—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
- H01L2224/0951—Function
- H01L2224/09515—Bonding areas having different functions
- H01L2224/09517—Bonding areas having different functions including bonding areas providing primarily mechanical support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
- H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
- H01L2224/214—Connecting portions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
- H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
- H01L2224/215—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29301—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29309—Indium [In] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73259—Bump and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8036—Bonding interfaces of the semiconductor or solid state body
- H01L2224/80379—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/80399—Material
- H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/80438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/80447—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/80399—Material
- H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/80438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/80455—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/80399—Material
- H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/80438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/80457—Cobalt [Co] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/80399—Material
- H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/80463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/80466—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/80399—Material
- H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/80463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/80476—Ruthenium [Ru] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/80399—Material
- H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/80463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/80481—Tantalum [Ta] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/80399—Material
- H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/80463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/80484—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/80399—Material
- H01L2224/80486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/80399—Material
- H01L2224/8049—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83444—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83447—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83455—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/8346—Iron [Fe] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/83486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2224/83487—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/83486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2224/83488—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/9202—Forming additional connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
一種半導體封裝包括第一半導體晶粒、第二半導體晶粒及多個凸塊。第一半導體晶粒具有彼此相對的前側與背側。第二半導體晶粒設置於第一半導體晶粒的背側處且電性連接至第一半導體晶粒。所述多個凸塊設置於第一半導體晶粒的前側處且實體連接至第一半導體晶粒的第一晶粒接墊。第一半導體晶粒的總寬度可小於第二半導體晶粒的總寬度。
Description
由於各種電子部件(例如,電晶體、二極體、電阻器、電容器等)的積體密度的持續提高,半導體行業已經歷快速增長。在很大程度上,積體密度的此種提高是源自最小特徵大小(minimum feature size)的連番減小,此使更多的部件能夠整合到給定的面積中。隨著近來對小型化、較高的速度及較大的頻寬、以及較低的功耗及較少的潛時的需求的增加,對更小且更具創造性的半導體晶粒封裝技術的需要有所增加。目前,半導體封裝(例如,系統積體電路(System-on-Integrated-Circuit,SoIC)部件)因其多功能及緊湊性而越來越受歡迎。然而,存在與此種半導體封裝相關的挑戰。
以下揭露內容提供用於實施所提供標的物的不同特徵的諸多不同實施例或實例。以下闡述部件及佈置的具體實例以簡化本揭露。當然,該些僅為實例且不旨在進行限制。舉例而言,以下說明中將第一特徵形成於第二特徵之上或第二特徵上可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外,本揭露可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的,而不是自身指示所論述的各種實施例及/或配置之間的關係。
此外,為易於說明,本文中可使用例如「在…之下(beneath)」、「在…下方(below)」、「下部的(lower)」、「在…上方(above)」、「上部的(upper)」及類似用語等空間相對性用語來闡述圖中所示的一個組件或特徵與另一(其他)組件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括元件在使用或操作中的不同定向。裝置可具有其他定向(旋轉90度或處於其他定向),且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
在一些實施例中,當提供具有不同大小的兩個半導體晶粒時,較小的半導體晶粒被配置成面對球陣列,且較大的半導體晶粒被配置成背對球陣列。藉由此種配置,可顯著提高半導體封裝的訊號傳輸效能。
圖1至圖10是示意性地示出根據本揭露一些實施例的形成半導體封裝的方法的剖視圖。應理解,本揭露不受以下所述方法所限制。對於所述方法的附加實施例,可在所述方法之前、期間及/或之後提供附加操作且可替換或消除以下所述操作中的一些操作。儘管圖1至圖10是關於方法來闡述,然而應領會,圖1至圖10中所揭露的結構不僅限於此種方法,而是可作為獨立於所述方法的結構而獨立存在。
參照圖1,提供多個半導體晶粒100(例如,邏輯晶粒、記憶體晶粒或類似物)。在圖1中,示出僅兩個半導體晶粒100;然而,半導體晶粒100的數目不受本揭露所限制。在一些實施例中,半導體晶粒100中的每一者包括主動前側S1(例如,前表面)及與前側S1相對的背側S2(例如,背表面)。在一些實施例中,半導體晶粒100包括半導體基底102、至少一個元件T1、內連線結構106、晶粒接墊P1及鈍化層112。在說明通篇中,對應於半導體基底的具有元件或主動層的一側的半導體晶粒100的一側被稱為前側。
半導體基底102可包含例如矽、鍺等元素半導體及/或例如矽鍺、碳化矽、鎵砷、砷化銦、氮化鎵或磷化銦等化合物半導體。在一些實施例中,半導體基底102可採取平面基底的形式、具有多個鰭(fin)的基底的形式、奈米線(nanowire)的形式或其他形式。半導體晶粒100可更包括形成於半導體基底102中且電性連接至內連線結構106的內連線配線(interconnect wiring)或內連導線(interconnect line)的基底穿孔(through substrate via,TSV)103。如圖1中所示,將基底穿孔103嵌置於半導體基底102及內連線結構106中,且在此階段處,基底穿孔103未自半導體基底102的背表面顯露出。基底穿孔103可包含Cu、Ti、Ta、W、Ru、Co、Ni、類似物、其合金或其組合。在一些實施例中,藉由電鍍製程來形成基底穿孔103,且基底穿孔103可包括例如障壁層、黏合層、填充材料及/或類似物等一或多個層。
在半導體基底102上/中設置元件T1,且元件T1包括一或多個功能性元件。功能性元件可包括主動部件、被動部件或其組合。在一些實施例中,功能性元件可包括積體電路元件。功能性元件為例如電晶體、電容器、電阻器、二極體、光電二極體、熔絲元件及/或其他相似元件。在一些實施例中,半導體晶粒100可被稱為「第一元件晶粒(first device die)」、「第一層半導體晶粒(first-tier semiconductor die)」或「下部積體電路結構(lower integrated circuit structure)」。
在半導體基底102上形成內連線結構106,且將內連線結構106電性連接至元件T1。內連線結構106可包括統稱為介電層110的一或多個介電層以及嵌置於所述至少一個介電層110中的金屬特徵108。金屬特徵108設置於介電層110中且彼此電性連接。金屬特徵108的部分(例如最頂金屬特徵108a)藉由介電層110暴露出。在一些實施例中,介電層110包括位於半導體基底102上的層間介電(inter-layer dielectric,ILD)層以及位於層間介電層之上的至少一個金屬間介電(inter-metal dielectric,IMD)層。在一些實施例中,介電層110包含氧化矽、氮氧化矽、氮化矽、低介電常數(低k)材料或其組合。介電層110可為單層或多層式結構。在一些實施例中,金屬特徵108包括金屬插塞及金屬線。插塞可包括形成於層間介電層中的接觸件及形成於金屬間介電層中的通孔。接觸件形成於底部金屬線與下伏的元件T1之間且與底部金屬線及下伏的元件T1接觸。通孔形成於兩個金屬線之間且與所述兩個金屬線接觸。金屬特徵108可包含Cu、Ti、Ta、W、Ru、Co、Ni、類似物、其合金或其組合。在一些實施例中,可在每一金屬特徵108與介電層110之間設置障壁層,以防止金屬特徵108的材料遷移至下伏的元件T1。障壁層包含例如Ta、TaN、Ti、TiN、CoW、類似物或其組合。在一些實施例中,藉由雙鑲嵌製程來形成內連線結構106。在其他實施例中,藉由多個單鑲嵌製程來形成內連線結構106。在其他實施例中,藉由電鍍製程來形成內連線結構106。
在內連線結構106之上形成晶粒接墊P1,且將晶粒接墊P1電性連接至內連線結構106。在一些實施例中,晶粒接墊P1與內連線結構106的最頂金屬特徵108a實體接觸。在一些實施例中,晶粒接墊P1是鋁接墊。然而,本揭露不僅限於此。在其他實施例中,晶粒接墊P1是銅接墊、鎳接墊或由其他適合的材料製成的接墊。晶粒接墊P1中的每一者可為單層或多層式結構。在一些實施例中,晶粒接墊P1中的一些晶粒接墊P1在其頂表面上具有探針標記(probe mark)。半導體晶粒100在通過測試之後可被稱為「已知良好晶粒(known good die)」。在一些實施例中,晶粒接墊P1不具有探針標記。在一些實施例中,藉由濺鍍製程、沉積製程、電鍍製程、其組合或類似製程來形成晶粒接墊P1。
在內連線結構106之上形成鈍化層112,且鈍化層112覆蓋晶粒接墊P1的側壁及頂表面。在一些實施例中,鈍化層112包含氧化矽、氮化矽、苯並環丁烯(benzocyclobutene,BCB)聚合物、聚醯亞胺(polyimide,PI)、聚苯並噁唑(polybenzoxazole,PBO)、其組合或類似物,且藉由例如旋轉塗佈、化學氣相沉積(chemical vapor deposition,CVD)或類似製程等適合的製程來形成鈍化層112。
在一些實施例中,藉由接合膜F1來覆蓋半導體晶粒100的鈍化層112。在一些實施例中,接合膜F1包含矽(Si)、氧化矽(SiO
x,其中x>0)、氮化矽(SiN
x,其中x>0)、氮氧化矽(SiO
xN
y,其中x>0且y>0)或其他適合的接合材料。
參照圖2,提供包括位於其上的接合膜F
C1的載體C1。載體C1可為例如矽晶圓等半導體晶圓,且接合膜F
C1可為為熔融接合準備的接合層。在一些實施例中,接合膜F
C1是在載體C1的頂表面之上形成的沉積層。在其他實施例中,接合膜F
C1是載體C1的用於熔融接合的部分。在一些實施例中,接合膜F
C1包含矽(Si)、氧化矽(SiO
x,其中x>0)、氮化矽(SiN
x,其中x>0)、氮氧化矽(SiO
xN
y,其中x>0且y>0)或其他適合的接合材料。在一些實施例中,接合膜F
C1與接合膜F1包含相同的材料(例如氧化矽)。在其他實施例中,接合膜F
C1與接合膜F1包含不同的材料。
將半導體晶粒100翻轉並放置於載體C1上,使得接合膜F1與接合膜F
C1接觸。具體而言,將多個半導體晶粒100以並排的方式拾取並放置於接合膜F
C1上,使得半導體晶粒100被佈置成陣列且彼此間隔開。在一些實施例中,將半導體晶粒100放置於接合膜F
C1的頂表面上,使得半導體晶粒100的前側S1面對載體C1的接合膜F
C1。
在將半導體晶粒100拾取並放置於接合膜F
C1上之後,可執行晶片對晶圓熔融接合製程(chip-to-wafer fusion bonding process),使得在接合膜F
C1與接合膜F1之間形成熔融接合介面。舉例而言,在範圍介於約100攝氏度至約290攝氏度的溫度下執行用於對接合膜F
C1與接合膜F1進行接合的熔融接合製程。可將接合膜F
C1直接接合至接合膜F1。換言之,在接合膜F
C1與接合膜F1之間未形成有中間層。形成於接合膜F
C1與接合膜F1之間的上述熔融接合介面可為Si-Si熔融接合介面、Si-SiO
x熔融接合介面、SiO
x-SiO
x熔融接合介面、SiO
x-SiN
x熔融接合介面或其他適合的熔融接合介面。
參照圖3,在藉由接合膜F
C1及接合膜F1將半導體晶粒100接合至載體C1之後,在載體C1之上形成介電包封層E1,且介電包封層E1覆蓋半導體晶粒100。在一些實施例中,藉由包覆模製製程(over-molding process)或膜沉積製程(film deposition process)來形成介電包封層E1,使得接合膜F
C1的頂表面的部分、接合膜F1的側表面以及半導體晶粒100的背表面及側表面由介電包封層E1包封。在一些實施例中,介電包封層E1包含模製化合物、模製底部填充膠、樹脂、其組合或類似物。在一些實施例中,介電包封層E1包含例如聚苯並噁唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)、其組合或類似物等聚合物材料。在一些實施例中,介電包封層E1包含例如氧化矽、氮化矽或其組合等絕緣材料。
參照圖4,在執行包覆模製製程或膜沉積製程之後,可執行磨制製程(grinding process)或平坦化製程(planarization process)以減小包封材料的厚度及半導體晶粒100的厚度,直至暴露出基底穿孔103為止。在一些實施例中,磨制製程包括機械磨制製程、化學機械研磨(chemical mechanical polishing,CMP)製程或其組合。
如圖4中所示,在一些實施例中,半導體晶粒100的厚度等於介電包封層E1的厚度。在一些實施例中,介電包封層E1與半導體晶粒100及接合膜F1的側表面接觸,且半導體基底102的背表面自介電包封層E1以可觸及的方式顯露出。換言之,在製程變化內,介電包封層E1的頂表面與半導體晶粒100的被暴露出的表面實質上齊平。然而,本揭露不僅限於此。在一些實施例中,由於磨制製程的研磨選擇性,介電包封層E1的頂表面可略微高於或略微低於半導體晶粒100的被暴露出的表面。
參照圖5,在半導體晶粒100的背側S2及介電包封層E1的被暴露出的表面之上形成重佈線層結構119。重佈線層結構119包括至少一個聚合物層115及由聚合物層115嵌置的導電特徵117。導電特徵117包括被配置成電性連接至不同部件的金屬接墊、金屬線及/或金屬通孔。在一些實施例中,聚合物層115包含例如聚苯並噁唑(PBO)、聚醯亞胺(PI)、苯並環丁烯(BCB)、其組合或類似物等感光性材料。根據需要,可用介電層或絕緣層來替換重佈線層結構119的聚合物層115。在一些實施例中,導電特徵117包含Cu、Ti、Ta、W、Ru、Co、Ni、類似物、其合金、其組合或類似形式。在一些實施例中,可在每一導電特徵117與聚合物層115之間設置晶種層及/或障壁層。晶種層可包含Ti/Cu。障壁層可包含Ta、TaN、Ti、TiN、CoW、其組合或類似物。
仍然參照圖5,在重佈線層結構119之上形成接合結構120。在一些實例中,接合結構120被稱為「毯式接合結構(blanket bonding structure)」,此乃因接合結構120橫跨半導體晶粒100形成且在半導體晶粒100之間延伸並延伸超出半導體晶粒100。
在一些實施例中,接合結構120包括至少一個接合膜BF1及嵌置於接合膜BF1中的接合金屬特徵。在一些實施例中,接合膜BF1包含絕緣材料、介電材料、聚合物材料或其組合。舉例而言,接合膜BF1包含矽(Si)、氧化矽(SiO
x,其中x>0)、氮化矽(SiN
x,其中x>0)、氮氧化矽(SiO
xN
y,其中x>0且y>0)或其他適合的接合材料。接合金屬特徵可包含Cu、Ti、Ta、W、Ru、Co、Ni、其合金、其組合或類似物。在一些實施例中,可在每一接合金屬特徵與接合膜BF1之間設置晶種層及/或障壁層。晶種層可包含Ti/Cu。障壁層可包含Ta、TaN、Ti、TiN、CoW或其組合。在一些實施例中,接合金屬特徵包括接合接墊BP11及BP12以及接合通孔BV1。具體而言,如圖5中所示,將接合接墊BP11及接合通孔BV1配置成接合至且電性連接至下伏的半導體晶粒100及上覆的半導體晶粒或晶粒堆疊。在一些實施例中,接合通孔BV1與基底穿孔103及接合接墊BP11實體接觸。此外,將接合接墊BP12配置成接合至下伏的半導體晶粒100及上覆的半導體晶粒或晶粒堆疊,但與下伏的半導體晶粒100及上覆的半導體晶粒或晶粒堆疊電性絕緣。在一些實例中,接合接墊BP12被稱為「虛設接合接墊(dummy bonding pad)」或「浮置接合接墊(floating bonding pad)」,此乃因提供接合接墊BP12僅是為了增強晶粒之間的接合強度。在一些實施例中,如圖5中所示,接合接墊BP11與BP12的大小(例如,寬度)不同。然而,本揭露不僅限於此。在其他實施例中,接合接墊BP11與BP12可具有相同的大小。
參照圖6,在接合結構120上提供並放置多個半導體晶粒200(例如,記憶體晶粒、邏輯晶粒或其他適合的晶粒)。在圖4中,示出兩個半導體晶粒200;然而,半導體晶粒200的數目不受本揭露所限制。在一些實施例中,半導體晶粒200分別對應於下伏的半導體晶粒100。半導體晶粒200與半導體晶粒100可為相同類型或不同類型的晶粒。
在一些實施例中,半導體晶粒200中的每一者包括主動前側(例如,前表面)及與主動側相對的背側(例如,背表面)。在一些實施例中,半導體晶粒200中的每一者包括半導體基底202、至少一個元件T2、內連線結構206、晶粒接墊P2及鈍化層212。在說明通篇中,對應於半導體基底的具有元件或主動層的一側的半導體晶粒200的一側側被稱為前側。
半導體基底202可包含例如矽、鍺等元素半導體及/或例如矽鍺、碳化矽、鎵砷、砷化銦、氮化鎵或磷化銦等化合物半導體。在一些實施例中,半導體基底202可採取平面基底的形式、具有多個鰭的基底的形式、奈米線的形式或此項技術中具有通常知識者已知的其他形式。若需要,則半導體晶粒200可更包括形成於半導體基底202中且電性連接至內連線結構206的內連線配線或內連導線的基底穿孔(TSV)(未示出)。
在半導體基底202上/中設置元件T2,且元件T2包括一或多個功能性元件。功能性元件可包括主動部件、被動部件或其組合。在一些實施例中,功能性元件可包括積體電路元件。功能性元件為例如電晶體、電容器、電阻器、二極體、光電二極體、熔絲元件及/或其他相似元件。在一些實施例中,半導體晶粒200被稱為「第二元件晶粒(second device die)」、「第二層半導體晶粒(second-tier semiconductor die)」或「上部積體電路結構(upper integrated circuit structure)」。在一些實施例中,可用包括多個晶粒的晶粒堆疊來替換上部積體電路結構。
在半導體基底202上形成內連線結構206,且將內連線結構206電性連接至元件T2。內連線結構206可包括統稱為介電層210的一或多個介電層以及由介電層210嵌置的金屬特徵208。金屬特徵208設置於介電層210中且彼此電性連接。金屬特徵208的部分(例如最頂金屬特徵208a)藉由介電層210暴露出。在一些實施例中,介電層210包括位於半導體基底202上的層間介電(ILD)層以及位於層間介電層之上的至少一個金屬間介電(IMD)層。在一些實施例中,介電層210包含氧化矽、氮氧化矽、氮化矽、低介電常數(低k)材料、其組合或類似物。介電層210可為單層或多層式結構。在一些實施例中,金屬特徵208包括金屬插塞及金屬線。插塞可包括形成於層間介電層中的接觸件及形成於金屬間介電層中的通孔。接觸件形成於底部金屬線與下伏的元件T2之間且與底部金屬線及下伏的元件T2接觸。通孔形成於兩個金屬線之間且與所述兩個金屬線接觸。金屬特徵208可包含Cu、Ti、Ta、W、Ru、Co、Ni、其合金、其組合或類似物。在一些實施例中,可在每一金屬特徵208與介電層210之間設置障壁層,以防止金屬特徵208的材料遷移至下伏的元件T2。障壁層包含例如Ta、TaN、Ti、TiN、CoW、其組合或類似物。在一些實施例中,藉由雙鑲嵌製程來形成內連線結構206。在其他實施例中,藉由多個單鑲嵌製程來形成內連線結構206。在其他實施例中,藉由電鍍製程來形成內連線結構206。
在內連線結構206之上形成晶粒接墊P2,且將晶粒接墊P2電性連接至內連線結構206。在一些實施例中,晶粒接墊P2與內連線結構206的最頂金屬特徵208a實體接觸。在一些實施例中,晶粒接墊P2是鋁接墊。然而,本揭露不僅限於此。在其他實施例中,晶粒接墊P2是銅接墊、鎳接墊或由其他適合的材料製成的接墊。晶粒接墊P2中的每一者可為單層或多層式結構。在一些實施例中,晶粒接墊P2中的一些晶粒接墊P2在其頂表面上具有探針標記。在驗收測試(acceptance testing)之後,半導體晶粒200可被稱為「已知良好晶粒」。在一些實施例中,晶粒接墊P2不具有探針標記。
在內連線結構206之上形成鈍化層212,鈍化層212包封晶粒接墊P2的側壁,但暴露出晶粒接墊P2的頂表面。在一些實施例中,鈍化層212包含氧化矽、氮化矽、苯並環丁烯(BCB)聚合物、聚醯亞胺(PI)、聚苯並噁唑(PBO)或其組合,且藉由例如旋轉塗佈、CVD或類似製程等適合的製程來形成鈍化層212。
在一些實施例中,在內連線結構206之上進一步提供接合結構220。在一些實施例中,接合結構220被視為半導體晶粒200的一部分。在一些實例中,接合結構220被稱為「晶粒接合結構」,此乃因接合結構220的邊緣與半導體晶粒200的邊緣對準。
在一些實施例中,接合結構220包括至少一個接合膜BF2及嵌置於接合膜BF2中的接合金屬特徵。在一些實施例中,接合膜BF2包含絕緣材料、介電材料、聚合物材料或其組合。舉例而言,接合膜BF2包含矽(Si)、氧化矽(SiO
x,其中x>0)、氮化矽(SiN
x,其中x>0)、氮氧化矽(SiO
xN
y,其中x>0且y>0)或其他適合的接合材料。接合金屬特徵可包含Cu、Ti、Ta、W、Ru、Co、Ni、其合金、其組合或類似物。在一些實施例中,可在每一接合金屬特徵與接合膜BF2之間設置晶種層及/或障壁層。晶種層可包含Ti/Cu。障壁層可包含Ta、TaN、Ti、TiN、CoW、其組合或類似物。在一些實施例中,接合金屬特徵包括接合接墊BP21及BP22以及接合通孔BV2。如圖6中所示,將接合接墊BP21及接合通孔BV2配置成接合至且電性連接至下伏的半導體晶粒100。在一些實施例中,接合通孔BV2與晶粒接墊P2及接合接墊BP21實體接觸。將接合接墊BP22配置成接合至下伏的半導體晶粒100,但與下伏的半導體晶粒100及上覆的半導體晶粒200電性絕緣。在一些實例中,接合接墊BP22被稱為「虛設接合接墊」或「浮置接合接墊」,此乃因提供接合接墊BP22僅是為了增強晶粒之間的接合強度。在一些實施例中,如圖6中所示,接合接墊BP21與BP22的大小(例如,寬度)不同。然而,本揭露不僅限於此,且在一些實施例中,接合接墊BP21與BP22可具有相同的大小。
在一些實施例中,將接合結構220與接合結構120對準,執行晶片對晶圓混合接合,使得半導體晶粒200的接合結構220混合接合至接合結構120。在一些實施例中,可藉由面對背混合接合製程對半導體晶粒200與半導體晶粒100進行接合。然而,本揭露不僅限於此。在一些實施例中,可藉由面對面混合接合製程對半導體晶粒200與半導體晶粒100進行接合。
圖6示出其中半導體晶粒200與半導體晶粒100為不同大小的實施例。半導體晶粒200的大小不同於(例如,大於)半導體晶粒100的大小。本文中,用語「大小」指代高度、長度、寬度、俯視面積或其組合。舉例而言,自俯視圖來看,半導體晶粒100的大小或面積小於半導體晶粒200的大小或面積。
在一些實施例中,半導體晶粒200與半導體晶粒100可在晶粒高度上不同。舉例而言,半導體晶粒200的高度不同於(例如,大於)半導體晶粒100的臨界尺寸。舉例而言,半導體晶粒200的高度的範圍介於約20微米至775微米,且半導體晶粒100的高度的範圍介於約10微米至50微米。在一些實施例中,半導體晶粒200的高度對半導體晶粒100的高度的比率的範圍介於30:1至15:1,例如為20:1。
在一些實施例中,半導體晶粒200與半導體晶粒100在臨界尺寸上可不同。舉例而言,半導體晶粒200的臨界尺寸不同於(例如,大於)半導體晶粒100的臨界尺寸。在本文中,用語「臨界尺寸」指代IC特徵的最小可達成尺寸。舉例而言,臨界尺寸包括金屬線的最小線寬或開口的最小寬度。
在一些實施例中,為促進接合結構120與接合結構220之間的晶片對晶圓混合接合,執行用於接合結構120及接合結構220的接合表面的表面準備。表面準備可包括例如表面清潔及活化。可對接合結構120及接合結構220的接合表面執行表面清潔,以移除接合接墊及接合膜的接合表面上的微粒及/或天然氧化物。藉由例如濕法清潔(wet cleaning)來清潔接合結構120及接合結構220的接合表面。
在清潔接合結構120及接合結構220的接合表面之後,可執行對頂表面的活化以增進高接合強度。在一些實施例中,執行電漿活化以處置及活化接合膜BF1及BF2的接合表面。當接合膜BF1的經活化接合表面與接合膜BF2的經活化接合表面接觸時,接合膜BF1與BF2被預接合。接合結構220與接合結構120藉由接合膜BF1與BF2的預接合而被預接合。在接合膜BF1與BF2的預接合之後,接合接墊BP11與接合接墊BP21接觸,且接合接墊BP12與接合接墊BP22接觸。
在對接合膜BF1與BF2的預接合製程之後,執行對半導體晶粒200與接合結構120的混合接合。半導體晶粒200與接合結構120的混合接合可包括用於介電接合的處置及用於導體接合的熱退火。執行用於介電接合的處置以加強接合膜BF1與BF2之間的接合。可在範圍介於例如約100攝氏度至約150攝氏度的溫度下執行用於介電接合的處置。在執行用於介電接合的處置之後,執行用於導體接合的熱退火以促進接合接墊BP11與BP21之間以及接合接墊BP12與BP22之間的接合。可在範圍介於例如約300攝氏度至約400攝氏度的溫度下執行用於導體接合的熱退火。用於導體接合的熱退火的製程溫度高於用於介電接合的處置的製程溫度。由於用於導體接合的熱退火是在相對較高的溫度下執行,因此在接合接墊BP11與BP21之間以及接合接墊BP12與BP22之間的接合介面處可能發生金屬擴散(metal diffusion)及顆粒生長(grain growth)。導體接合不僅限於接墊對接墊接合。根據需要,可應用通孔對通孔接合或通孔對接墊接合。
參照圖7,在藉由接合結構120及接合結構220將半導體晶粒200接合至半導體晶粒100之後,形成介電包封層E2以覆蓋接合結構120、接合結構220及半導體晶粒200。在一些實施例中,藉由包覆模製製程或膜沉積製程來形成介電包封層E2,使得接合結構120的頂表面的部分、接合結構220的側表面以及半導體晶粒200的背表面及側表面由介電包封層E2包封。在一些實施例中,介電包封層E2包含模製化合物、模製底部填充膠、樹脂或類似物。在一些實施例中,介電包封層E2包含聚合物材料(例如聚苯並噁唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)、其組合或類似物)、絕緣材料(例如氧化矽、氮化矽、其組合或類似物)、其組合或類似物。
在執行包覆模製製程或膜沉積製程之後,可執行磨制製程或平坦化製程以減小包封材料的厚度及半導體晶粒200的厚度,直至暴露出半導體晶粒200的背表面為止。在一些實施例中,磨制製程包括機械磨制製程、化學機械研磨(CMP)製程或其組合。
如圖7中所示,在一些實施例中,半導體晶粒200的厚度等於介電包封層E2的厚度。在一些實施例中,介電包封層E2與半導體晶粒200及接合膜BF2的側表面接觸,且半導體基底202的背表面自介電包封層E2以可觸及的方式顯露出。舉例而言,介電包封層E2的頂表面與半導體晶粒200的被暴露出的表面實質上齊平(在製程變化內)。然而,本揭露不僅限於此。在一些實施例中,由於磨制製程的研磨選擇性,介電包封層E2的頂表面可略微高於或略微低於半導體晶粒200的被暴露出的表面。此外,介電包封層E2藉由接合結構120與介電包封層E1間隔開。
參照圖8,提供包括位於其上的接合膜F
C2的載體C2。載體C2可為玻璃晶圓,且接合膜F
C2可為黏合材料。接合膜F
C2可包括氧化物層、晶粒貼合膜(die attach film,DAF)或適合的黏合劑。藉由接合膜F
C2將載體C2接合至半導體晶粒200的背表面及介電包封層E2的被暴露出的表面。在一些實施例中,可在接合膜F
C2與半導體基底202之間以及接合膜F
C2與介電包封層E2之間提供毯式接合膜,且可藉由熔融接合將接合膜F
C2接合至毯式接合膜。
此後,可執行剝離製程,使得接合膜F
C1及下伏的載體C1自接合膜F1及介電包封層E1剝離。剝離製程可為雷射提離製程(laser lift-off process)或其他適合的剝離製程。在移除接合膜F
C1及載體C1之後,可執行磨制製程,使得接合膜F1被移除以暴露出鈍化層112。在對接合膜F1的移除期間,可對介電包封層E1進行薄化。在一些實施例中,可藉由相同的磨制製程(例如,CMP製程)來執行對接合膜F1的移除與對介電包封層E1的薄化。如圖8中所示,在執行磨制製程之後,半導體晶粒100被顯露出,但在此階段處,半導體晶粒100的晶粒接墊P1未被顯露出且被鈍化層112覆蓋。
仍然參照圖8,執行鈍化層112的圖案化製程,使得在鈍化層112中形成多個開口OP且暴露出晶粒接墊P1。在一些實施例中,形成後鈍化層(post passivation layer)(未示出)以覆蓋介電包封層E1以及半導體晶粒100的鈍化層112,且穿過後鈍化層及鈍化層112形成開口。在一些實施例中,執行微影及蝕刻製程以形成開口OP。然而,本揭露不僅限於此。在其他實施例中,執行雷射鑽孔製程(laser drilling process)以形成開口OP。
此後,在鈍化層112的開口OP內形成導電端子或凸塊B,且將導電端子或凸塊B電性連接至半導體晶粒100的晶粒接墊P1。在一些實施例中,凸塊B設置於晶片區內且與晶粒接墊P1實體接觸。在一些實施例中,凸塊B包括焊料凸塊,及/或可包括金屬柱(例如,銅柱)、形成於金屬柱上的焊料頂蓋及/或類似物。可藉由例如蒸鍍、電鍍、落球(ball drop)或網版印刷(screen printing)等適合的製程來形成凸塊B。
參照圖9,將載體C2自介電包封層E2剝離。在一些實施例中,剝離製程是雷射剝離製程或適合的製程。然後自介電包封層E2移除黏合層或接合膜F
C2。在一些實施例中,移除製程是蝕刻製程及/或清潔製程。
此後,沿切割線CL對圖9所示結構執行晶圓切割製程,以便切割穿過介電包封層E2、接合膜BF1、聚合物層115及介電包封層E1。如圖10中所示,在晶圓切割製程或單體化製程之後,相鄰的半導體封裝10彼此分隔開。因此形成一些實施例的半導體封裝10。在一些實施例中,可在半導體封裝10下面設置例如印刷電路板(printed circuit board,PCB)等板基底及/或例如矽中介層或有機中介層等中介層基底,且藉由凸塊B將板基底及/或中介層基底接合至半導體封裝10。
圖11是示意性地示出根據本揭露一些實施例的半導體封裝的剖視圖。圖11所示半導體封裝11相似於圖10所示半導體封裝10,其中相同的參考編號指代相同的組件。圖11所示組件的材料及配置可參考在先前實施例中所述的相似組件的材料及配置。圖11所示半導體封裝11有益於成本降低及/或大小減小。舉例而言,為達成成本降低及/或大小減小,可省略重佈線層結構119。
形成圖11所示半導體封裝11的方法相似於圖1至圖10中所述的形成半導體封裝10的方法,但省略了如圖5中所示的形成重佈線層結構119的操作,且接合結構120的結構可相應地改變。在一些實施例中,如圖11中所示,半導體晶粒200藉由接合結構120及接合結構220接合至半導體晶粒100,但如圖10中所示的接合通孔BV1可可選地自接合結構120省略。具體而言,接合接墊BP11與半導體晶粒200的接合接墊BP21及半導體晶粒100的基底穿孔103實體接觸,且接合接墊BP12與半導體晶粒200的接合接墊BP22以及介電包封層E1實體接觸。
在本揭露中,當提供具有不同大小及臨界尺寸的兩個半導體晶粒時,具有較小臨界尺寸的較小的半導體晶粒(例如,半導體晶粒100)被配置成面對球陣列(例如,凸塊B),且具有較大臨界尺寸的較大的半導體晶粒(例如,半導體晶粒200)距球陣列(例如,凸塊B)更遠。藉由此種配置,可顯著提高半導體封裝的訊號傳輸效能。關鍵晶粒與球陣列之間的訊號被直接傳輸,而無需附加的佈線(routing)或打線接合(wire bonding)。
在以上實施例中,半導體封裝是利用其中在將上部半導體晶粒接合至下部半導體晶粒之前形成下部半導體晶粒的晶粒接墊的「晶粒接墊優先(die pad first)」製程形成。然而,本揭露不僅限於此。在其他實施例中,半導體封裝是利用其中在將上部半導體晶粒接合至下部半導體晶粒之後形成下部半導體晶粒的晶粒接墊的「晶粒接墊最末(die pad last)」製程形成。
圖12至圖21是示意性地示出根據本揭露其他實施例的形成半導體封裝的方法的剖視圖。應理解,本揭露不受以下所述方法所限制。對於所述方法的附加實施例,可在所述方法之前、期間及/或之後提供附加操作且可替換或消除以下所述操作中的一些操作。
儘管圖12至圖21是對於方法來闡述,然而應領會,圖12至圖21中所揭露的結構不僅限於此種方法,而是可作為獨立於所述方法的結構而獨立存在。
形成圖21所示半導體封裝20的方法相似於圖1至圖10中所述的形成半導體封裝10的方法,其中下部半導體晶粒的晶粒接墊的形成順序不同。以下詳細闡述其間的不同之處,且在本文中不再贅述相似之處。
參照圖12及圖13,提供多個半導體晶粒100(例如,邏輯晶粒、記憶體晶粒或類似物),且將所述多個半導體晶粒100接合至載體C1。應注意,在圖12及圖13所示階段中,提供不具有晶粒接墊的半導體晶粒100。具體而言,半導體晶粒100包括半導體基底102、設置於半導體基底102上/中的至少一個元件T1、設置於半導體基底102上且電性連接至元件T1的內連線結構106、穿透過半導體基底102且電性連接至內連線結構106的基底穿孔103以及鈍化層112。鈍化層112形成於內連線結構106之上且覆蓋最頂金屬特徵108a及介電層110。圖12至圖13所示組件的操作、材料及配置可參考圖1至圖2中所述者。
參照圖14及圖15,在藉由接合膜F
C1及接合膜F1將半導體晶粒100接合至載體C1之後,在載體C1之上形成介電包封層E1且在側向上包封半導體晶粒100。圖14至圖15所示組件的操作、材料及配置可參考圖3至圖4中所述者。
參照圖16,在半導體晶粒100的背側S2及介電包封層E1的被暴露出的表面之上形成重佈線層結構119。此後,在重佈線層結構119之上形成接合結構120。圖16所示組件的操作、材料及配置可參考圖5中所述者。
參照圖17,提供多個半導體晶粒200(例如,記憶體晶粒、邏輯晶粒或其他適合的晶粒),且將所述多個半導體晶粒200放置於接合結構120上。圖17所示組件的操作、材料及配置可參考圖6中所述者。
參照圖18,在藉由接合結構120及接合結構220將半導體晶粒200接合至半導體晶粒100之後,形成介電包封層E2以覆蓋接合結構120且在側向上包封半導體晶粒200。圖18所示組件的操作、材料及配置可參考圖7中所述者。
參照圖19,提供載體C2,且藉由接合膜F
C2將載體C2接合至半導體晶粒200的背表面及介電包封層E2的被暴露出的表面。此後,可執行剝離製程,使得接合膜F
C1及下伏的載體C1自接合膜F1及介電包封層E1剝離。在移除接合膜F
C1及載體C1之後,可執行磨制製程,使得接合膜F1被移除以暴露出鈍化層112。在對接合膜F1的移除期間,可對介電包封層E1進行薄化。在一些實施例中,可藉由磨制製程(例如,CMP製程)執行對接合膜F1的移除及對介電包封層E1的薄化。如圖19中所示,執行磨制製程,直至暴露出半導體晶粒100的鈍化層112為止。圖19所示組件的操作、材料及配置可參考圖8中所述者。
仍然參照圖19,執行鈍化層112的圖案化製程,使得在鈍化層112中形成多個開口OP1且暴露出內連線結構106的最頂金屬特徵108a。在一些實施例中,執行微影及蝕刻製程以形成開口OP1。然而,本揭露不經限於此。在其他實施例中,執行雷射鑽孔製程以形成開口OP1。
此後,在鈍化層112的開口OP1內形成晶粒接墊P1,且將晶粒接墊P1電性連接至半導體晶粒100的內連線結構106。在一些實施例中,晶粒接墊P1是鋁接墊、銅接墊、鎳接墊、其組合或類似物。晶粒接墊P1中的每一者可為單層或多層式結構。在一些實施例中,晶粒接墊P1中的一些晶粒接墊P1在其頂表面上具有探針標記。半導體晶粒100及上覆的半導體晶粒200被稱為「已知良好晶粒」。在一些實施例中,晶粒接墊P1不具有探針標記。
在一些實施例中,在形成晶粒接墊P1的操作期間,在晶粒接墊P1旁邊同時形成重佈線圖案118。舉例而言,在介電包封層E1之上與晶粒接墊P1相鄰地形成重佈線圖案118。將重佈線圖案118配置成在半導體晶粒100周圍散佈接觸點,以使得可施加例如焊料球等凸塊,且可散佈裝設的熱應力。在一些實施例中,藉由濺鍍製程、沉積製程、電鍍製程或類似製程來形成晶粒接墊P1及重佈線圖案118。
此後,形成後鈍化層122以覆蓋介電包封層E1、半導體晶粒100的鈍化層112及晶粒接墊P1以及重佈線圖案118。在一些實施例中,後鈍化層122包含氧化矽、氮化矽、苯並環丁烯(BCB)聚合物、聚醯亞胺(PI)、聚苯並噁唑(PBO)、其組合或類似物,且藉由例如旋轉塗佈、CVD或類似物等適合的製程形成後鈍化層122。在一些實施例中,鈍化層112與後鈍化層122包含相同的材料。在一些實施例中,鈍化層112與後鈍化層122包含不同的材料。
之後,執行後鈍化層122的圖案化製程,使得在後鈍化層122中形成多個開口OP2且暴露出半導體晶粒100的晶粒接墊P1。在一些實施例中,執行微影及蝕刻製程以形成開口OP2。然而,本揭露不僅限於此。在其他實施例中,執行雷射鑽孔製程以形成開口OP2。
然後,在開口OP2內形成導電端子或凸塊B,且將導電端子或凸塊B電性連接至半導體晶粒100的晶粒接墊P1及位於晶粒接墊P1旁邊的重佈線圖案118。在一些實施例中,凸塊B中的一些凸塊B設置於晶片區內且與晶粒接墊P1實體接觸,且凸塊B中的一些凸塊B設置於晶片區之外且與重佈線圖案118實體接觸。在一些實施例中,凸塊B包括焊料凸塊,及/或可包括金屬柱(例如,銅柱)、形成於金屬柱上的焊料頂蓋及/或類似物。可藉由例如蒸鍍、電鍍、落球、網版印刷或類似製程等適合的製程來形成凸塊B。
參照圖20,將載體C2自介電包封層E2剝離。在一些實施例中,剝離製程是雷射剝離製程或適合的製程。然後,自介電包封層E2移除黏合層或接合膜F
C2。在一些實施例中,移除製程是蝕刻製程及/或清潔製程。
此後,沿切割線CL對圖20所示結構執行晶圓切割製程,以便切割穿過介電包封層E2、接合膜BF1、聚合物層115及介電包封層E1。如圖21中所示,在晶圓切割製程或單體化製程之後,相鄰的半導體封裝20彼此分隔開。因此完成一些實施例的半導體封裝20。在一些實施例中,可在半導體封裝20下面設置例如印刷電路板(PCB)等板基底及/或例如矽中介層或有機中介層等中介層基底,且藉由凸塊B將板基底及/或中介層基底接合至半導體封裝20。
圖22至圖23是示意性地示出根據本揭露一些實施例的半導體封裝的剖視圖。圖22及圖23所示半導體封裝21及22分別相似於圖21所示半導體封裝20,其中相同的參考編號指代相同的組件。圖22及圖23所示組件的材料及配置可參考在先前實施例中所述的相似組件的材料及配置。圖22所示半導體封裝21可有益於成本降低及/或大小減小。圖23所示半導體封裝22可有益於散佈配線及佈線,且因此增加產品可撓性(product flexibility)。
形成圖22所示半導體封裝21的方法相似於圖12至圖21中所述的形成半導體封裝20的方法,其中省略了如圖16中所示的形成重佈線層結構119的操作。在一些實施例中,如圖21中所示,半導體晶粒200藉由接合結構120及接合結構220接合至半導體晶粒100,但如圖21中所示的接合通孔BV1可可選地自接合結構120省略。舉例而言,如圖21中所示,接合接墊BP11與半導體晶粒200的接合接墊BP21及半導體晶粒100的基底穿孔103實體接觸,且接合接墊BP12與半導體晶粒200的接合接墊BP22以及介電包封層E1實體接觸。
形成圖23所示半導體封裝22的方法相似於圖12至圖21中所述的形成半導體封裝20的方法,其中在圖14及圖15中的形成介電包封層E1的操作之前,更包括形成介電穿孔(through dielectric via,TDV)111的操作。介電穿孔111可包含Cu、Ti、Ta、W、Ru、Co、Ni、類似物、其合金或其組合。在一些實施例中,介電穿孔111是藉由電鍍製程形成。在一些實施例中,如圖23中所示,介電穿孔111電性連接至背側重佈線層結構119及前側重佈線圖案118。
以下參照圖10、圖11、圖20、圖21及圖22示出一些實施例的半導體封裝的結構。
在一些實施例中,半導體封裝10/11/20/21/22包括第一半導體晶粒100、第二半導體晶粒200及多個凸塊B。第一半導體晶粒100具有彼此相對的主動前側S1與背側S2。第二半導體晶粒200設置於第一半導體晶粒100的背側S2處,且電性連接至第一半導體晶粒100。所述多個凸塊B設置於第一半導體晶粒100的前側S1處,且實體連接至第一半導體晶粒100的第一晶粒接墊P1。在一些實施例中,第一半導體晶粒100的總寬度W1小於第二半導體晶粒200的總寬度W2。在一些實施例中,第一晶粒接墊P1包括鋁接墊。在一些實施例中,第一半導體晶粒100的臨界尺寸小於第二半導體晶粒200的臨界尺寸。
在一些實施例中,半導體封裝10/11/20/21/22更包括設置於第一半導體晶粒100與第二半導體晶粒200之間的第一接合結構120,且第一接合結構120的邊緣在側向上延伸超過第一半導體晶粒100的邊緣。在一些實施例中,半導體封裝10/11/20/21/22更包括設置於第一接合結構120與第二半導體晶粒200之間的第二接合結構220,其中第二接合結構220的邊緣與第二半導體晶粒200的邊緣對準。在一些實施例中,第一接合結構120藉由包括介電質對介電質接合及金屬對金屬接合的混合接合接合至第二接合結構220。在一些實施例中,半導體封裝10/11/20/21/22更包括在側向上包封第一半導體晶粒100的第一介電包封層E1以及設置於第一半導體晶粒100之上且在側向上包封第二半導體晶粒200的第二介電包封層E2。
在一些實施例中,半導體封裝10/20/22更包括設置於第一接合結構120與第二接合結構220之間的重佈線層結構119。
在一些實施例中,半導體封裝20/21/22更包括設置於第一半導體晶粒100的前側S1處及第一半導體晶粒100的第一晶粒接墊P1旁邊的重佈線圖案118。在一些實施例中,半導體封裝22更包括穿透過第一介電包封層E1且電性連接至重佈線層結構119及重佈線圖案118的介電穿孔111。
其中上部積體電路結構是單一半導體晶粒的以上實施例是出於例示目的而提供,且不應被解釋為限制本揭露。在一些實施例中,上部積體電路結構是包括垂直堆疊的多個晶粒的晶粒堆疊。
圖24是示意性地示出根據本揭露一些實施例的半導體封裝的剖視圖。圖24所示半導體封裝31相似於圖11所示半導體封裝11,其中相同的參考編號指代相同的組件。圖24所示組件的材料及配置可參考在先前實施例中所述的相似組件的材料及配置。圖24所示半導體封裝31可有益於產品可撓性。
如圖24中所示,提供包括半導體晶粒200-1及200-2的晶粒堆疊201,且將晶粒堆疊201接合至半導體晶粒100。在圖24中,僅示出兩個半導體晶粒200-1及200-2;然而,半導體晶粒200-1及200-2的數目不受本揭露所限制。在一些實施例中,半導體晶粒200-1是面對半導體晶粒100的最下晶粒,且半導體晶粒200-2是背對半導體晶粒100的最上晶粒。半導體晶粒200-1與200-2之間可夾置有一或多個半導體晶粒。在一些實施例中,半導體晶粒200-1包括半導體基底202、設置於半導體基底202之上的內連線結構206、設置於內連線結構206之上的接合結構220以及穿透過半導體基底202及內連線結構206且電性連接至下伏的半導體晶粒100及上覆的半導體晶粒200-2的基底穿孔(TSV)203。最上半導體晶粒200-2可具有與半導體晶粒200-1的結構相似的結構。在一些實施例中,根據需要,基底穿孔203可自半導體晶粒200-2省略。在一些實施例中,半導體晶粒200-2以面對背配置藉由混合接合接合至半導體晶粒200-1。然而,本揭露不僅限於此。半導體晶粒200-2可利用焊接(solder joint)接合至半導體晶粒200-1。根據需要,半導體晶粒200-2可以面對面配置或背對背配置接合至半導體晶粒200-1。在一些實施例中,基於製程要求,半導體封裝31中可更包括如圖10中所示的重佈線層結構119。
圖25是示意性地示出根據本揭露其他實施例的半導體封裝的剖視圖。圖25所示半導體封裝32相似於圖22所示半導體封裝21,其中相同的參考編號指代相同的組件。圖25所示組件的材料及配置可參考在先前實施例中所述的相似組件的材料及配置。圖25所示半導體封裝32可有益於產品可撓性。
如圖25中所示,提供包括半導體晶粒200-1及200-2的晶粒堆疊201,且將晶粒堆疊201接合至半導體晶粒100。圖25所示晶粒堆疊相似於圖24所示晶粒堆疊,其中相同的參考編號指代相同的組件。在一些實施例中,基於製程要求,半導體封裝32中可更包括如圖21中所示的重佈線層結構119。在一些實施例中,半導體封裝32中可更包括如圖23中所示的介電穿孔111。
在一些實施例中,如圖26及圖27中所示,本揭露的半導體封裝中更包括支撐構件300。
圖26所示半導體封裝41相似於圖11所示半導體封裝11,其中相同的參考編號指代相同的組件。圖26所示組件的材料及配置可參考在先前實施例中所述的相似組件的材料及配置。圖26所示半導體封裝41可有益於產品剛性(product rigidity)。
如圖26中所示,在半導體封裝41中,提供半導體晶粒200a,且將半導體晶粒200a接合至半導體晶粒100。半導體晶粒200a可具有與圖24中所述的半導體晶粒200-2的結構相似的結構。在一些實施例中,半導體封裝41中更包括支撐構件300。支撐構件300設置於半導體晶粒200a及介電包封層E2之上。在一些實施例中,支撐構件300可為包含半導體材料、無機材料、絕緣材料或其組合的基底。舉例而言,支撐構件300包含矽、陶瓷、石英或類似物。在一些實施例中,支撐構件300包括形成於其上的接合膜302。支撐構件300可為玻璃晶圓,且接合膜302可為黏合材料。接合膜302可包括氧化物層、晶粒貼合膜(DAF)或適合的黏合劑。支撐構件300藉由接合膜302接合至半導體晶粒200a的背表面及介電包封層E2的被暴露出的表面。在一些實施例中,接合膜302與半導體基底202之間以及接合膜302與介電包封層E2之間可設置有毯式接合膜,且接合膜302可藉由熔融接合接合至毯式接合膜。在一些實施例中,半導體晶粒200a可用包括垂直堆疊的多個晶粒的晶粒堆疊替換,且支撐構件300被接合至晶粒堆疊的最上晶粒。在一些實施例中,基於製程要求,半導體封裝41中可更包括如圖10中所示的重佈線層結構119。
圖27所示半導體封裝42相似於圖22所示半導體封裝21,其中相同的參考編號指代相同的組件。圖27所示組件的材料及配置可參考在先前實施例中所述的相似組件的材料及配置。圖27所示半導體封裝42可有益於產品剛性。
如圖27中所示,在半導體封裝42中,提供半導體晶粒200a,且將半導體晶粒200a接合至半導體晶粒100。半導體晶粒200a可具有與圖25中所述的半導體晶粒200-2的結構相似的結構,其中相同的參考編號指代相同的組件。在一些實施例中,半導體封裝42中更包括支撐構件300。在一些實施例中,支撐構件300包括形成於其上的接合膜302。支撐構件300及接合膜302的材料及配置可參考圖26中的先前實施例中所述者。
在一些實施例中,圖28及圖29所示半導體封裝中更包括散熱器400。
圖28所示半導體封裝51相似於圖26所示半導體封裝41,其中相同的參考編號指代相同的組件。圖28所示組件的材料及配置可參考在先前實施例中所述的相似組件的材料及配置。圖28所示半導體封裝51有益於產品剛性及散熱效率。
如圖28中所示,半導體封裝51中更包括散熱器400。散熱器400裝設於支撐構件300上。在一些實施例中,散熱器400可由例如鋼、不銹鋼、銅、其組合或類似物等具有高導熱性的材料形成。在一些實施例中,散熱器400塗佈有例如金、鎳或類似物等金屬。在一些實施例中,散熱器400是單一的連續材料。在一些實施例中,散熱器400包括可為相同或不同材料的多個片件。在一些實施例中,散熱器400是其中具有多個冷管(cold pipe)的冷板。在一些實施例中,冷管可以相等的間隔橫跨半導體封裝進行佈置。在一些實施例中,冷管可佈置於半導體封裝的熱點(hot spot)附近。在一些實施例中,散熱器400藉由熱介面材料(thermal interface material,TIM)402黏合至支撐構件300。在一些實施例中,TIM 402可包含環氧樹脂、膠水或類似物,且可為導熱材料。在一些實施例中,TIM 402可為聚合材料、焊料膏、銦焊料膏或類似物。在一些實施例中,支撐構件300及下伏的接合膜302可自圖28所示半導體封裝51省略,且TIM 402與半導體晶粒200a的背側及介電包封層E2實體接觸。在一些實施例中,基於製程要求,半導體封裝51中可更包括如圖10中所示的重佈線層結構119。
圖29所示半導體封裝52相似於圖27所示半導體封裝42,其中相同的參考編號指代相同的組件。圖29所示組件的材料及配置可參考在先前實施例中所述的相似組件的材料及配置。圖29所示半導體封裝52有益於產品剛性及散熱效率。
如圖29中所示,半導體封裝52中更包括散熱器400。在一些實施例中,散熱器400藉由熱介面材料(TIM)402黏合至支撐構件300。散熱器400及TIM 402的材料及配置可參考圖28中的先前實施例中所述者。在一些實施例中,支撐構件300及下伏的接合膜302可自圖29所示半導體封裝52省略,且TIM 402與半導體晶粒200a的背側及介電包封層E2實體接觸。在一些實施例中,基於製程要求,半導體封裝52中可更包括如圖21中所示的重佈線層結構119。在一些實施例中,半導體封裝52中可更包括如圖23中所示的介電穿孔111。
在圖26及圖27所示實施例中,支撐構件300寬於下伏的半導體晶粒200a。舉例而言,支撐構件300的寬度與下伏的SoIC結構的總寬度相同,所述總寬度等於半導體晶粒200a的寬度和介電包封層E2的寬度。在圖26及圖27所示實施例中,支撐構件300的底表面與半導體晶粒200a的背側及介電包封層E2的頂表面實體接觸。然而,本揭露不僅限於此。
在圖30及圖31所示其他實施例中,支撐構件300窄於下伏的半導體晶粒200a。舉例而言,支撐構件300的寬度小於下伏的SoIC結構的總寬度。在圖30及圖31所示半導體封裝61及62中,支撐構件300的底表面與半導體晶粒200a的背側實體接觸,且介電包封層E2在側向上包封半導體晶粒200a及支撐構件300的側壁。
圖32示出根據一些實施例的形成半導體封裝的方法。儘管將方法示出及/或闡述為一系列動作或事件,然而應領會,所述方法不僅限於所示出的次序或動作。因此,在一些實施例中,動作可按照與所示出的次序不同的次序施行及/或可同時施行。此外,在一些實施例中,所示出的動作或事件可被細分成多個動作或事件,所述多個動作或事件可在單獨的時間施行或與其他動作或子動作同時施行。在一些實施例中,可省略一些所示出的動作或事件,且可包括其他未示出的動作或事件。
在動作500處,提供第一半導體晶粒,其中第一半導體晶粒包括第一半導體基底、穿透過第一半導體基底的第一基底穿孔、形成於第一半導體基底的前表面之上且電性連接至第一基底穿孔的第一內連線結構以及形成於第一內連線結構之上且電性連接至第一內連線結構的多個第一晶粒接墊。圖1至圖2示出對應於動作500的一些實施例的剖視圖。圖11、圖24、圖26、圖28及圖30示出對應於動作500的一些實施例的剖視圖。
在動作502處,在第一半導體晶粒周圍形成第一介電包封層。圖3至圖4示出對應於動作502的一些實施例的剖視圖。圖11、圖24、圖26、圖28及圖30示出對應於動作502的一些實施例的剖視圖。
在動作504處,在第一半導體晶粒及第一介電包封層之上形成重佈線層結構。圖5示出對應於動作504的一些實施例的剖視圖。如圖11、圖24、圖26、圖28及圖30中所示,可可選地省略動作504。
在動作506處,在第一半導體晶粒及第一介電包封層之上形成第一接合結構。圖5示出對應於動作506的一些實施例的剖視圖。圖11、圖24、圖26、圖28及圖30示出對應於動作506的一些實施例的剖視圖。
在動作508處,將第二半導體晶粒接合至第一半導體晶粒的第一半導體基底的背表面。圖6示出對應於動作508的一些實施例的剖視圖。圖11、圖24、圖26、圖28及圖30示出對應於動作508的一些實施例的剖視圖。在一些實施例中,藉由混合接合將第二半導體晶粒接合至第一半導體晶粒。
在動作510處,將第三半導體晶粒接合至第二半導體晶粒。圖24示出對應於動作510的一些實施例的剖視圖。在一些實施例中,根據需要,可可選地省略動作510。在其他實施例中,動作510可重複進行多次,直至垂直堆疊了所期望數目的半導體晶粒為止。在一些實施例中,藉由混合接合將第三半導體晶粒接合至第二半導體晶粒。在其他實施例中,藉由焊接將第三半導體晶粒接合至第二半導體晶粒。
在動作512處,在第二半導體晶粒周圍形成第二介電包封層。圖7示出對應於動作512的一些實施例的剖視圖。圖11、圖24、圖26、圖28及圖30示出對應於動作512的一些實施例的剖視圖。在一些實施例中,如圖24中所示,在第三半導體晶粒周圍形成第二介電包封層。
在動作514處,在第一半導體晶粒的第一晶粒接墊之上形成多個凸塊。圖8至圖10、圖11、圖24、圖26、圖28及圖30示出對應於動作514的一些實施例的剖視圖。
在動作516處,在第二半導體晶粒之上形成支撐構件。圖26、圖28及圖30示出對應於動作516的一些實施例的剖視圖。可可選地省略動作516。
在動作518處,在支撐構件之上形成散熱器。圖28示出對應於動作518的一些實施例的剖視圖。可可選地省略動作518。
圖33示出根據一些實施例的形成半導體封裝的方法。儘管將方法示出及/或闡述為一系列動作或事件,然而應領會,所述方法不僅限於所示出的次序或動作。因此,在一些實施例中,動作可按照與所示出的次序不同的次序施行及/或可同時施行。此外,在一些實施例中,所示出的動作或事件可被細分成多個動作或事件,所述多個動作或事件可在單獨的時間施行或與其他動作或子動作同時施行。在一些實施例中,可省略一些所示出的動作或事件,且可包括其他未示出的動作或事件。
在動作600處,提供第一半導體晶粒,其中第一半導體晶粒包括第一半導體基底、穿透過第一半導體基底的第一基底穿孔以及形成於第一半導體基底之上且電性連接至第一基底穿孔的第一內連線結構。圖12至圖13示出對應於動作600的一些實施例的剖視圖。圖22至圖23、圖25、圖27、圖29及圖31示出對應於動作600的一些實施例的剖視圖。
在動作602處,在第一半導體晶粒周圍形成第一介電包封層。圖14至圖15示出對應於動作602的一些實施例的剖視圖。圖22至圖23、圖25、圖27、圖29及圖31示出對應於動作602的一些實施例的剖視圖。
在動作604處,在第一半導體晶粒及第一介電包封層之上形成重佈線層結構。圖16示出對應於動作604的一些實施例的剖視圖。圖23示出對應於動作604的一些實施例的剖視圖。如圖22、圖25、圖27、圖29及圖31中所示,可可選地省略動作604。
在動作606處,在第一半導體晶粒及第一介電包封層之上形成第一接合結構。圖16示出對應於動作606的一些實施例的剖視圖。圖22至圖23、圖25、圖27、圖29及圖31示出對應於動作606的一些實施例的剖視圖。
在動作608處,將第二半導體晶粒接合至第一半導體晶粒的第一半導體基底的背表面。圖17示出對應於動作608的一些實施例的剖視圖。圖22至圖23、圖25、圖27、圖29及圖31示出對應於動作608的一些實施例的剖視圖。在一些實施例中,藉由混合接合將第二半導體晶粒接合至第一半導體晶粒。
在動作610處,將第三半導體晶粒接合至第二半導體晶粒。圖25示出對應於動作610的一些實施例的剖視圖。在一些實施例中,可可選地省略動作610。在一些實施例中,動作610可重複進行多次,直至垂直堆疊了所期望數目的半導體晶粒為止。在一些實施例中,藉由混合接合將第三半導體晶粒接合至第二半導體晶粒。在一些實施例中,藉由焊接將第三半導體晶粒接合至第二半導體晶粒。
在動作612處,在第二半導體晶粒周圍形成第二介電包封層。圖18示出對應於動作612的一些實施例的剖視圖。圖22至圖23、圖25、圖27、圖29及圖31示出對應於動作612的一些實施例的剖視圖。在一些實施例中,如圖25中所示,在第三半導體晶粒周圍形成第二介電包封層。
在動作614處,在第一半導體基底的前表面之上及第一半導體晶粒的晶片區內形成多個第一晶粒接墊,其中所述多個第一晶粒接墊實體連接至第一內連線結構的頂部金屬圖案。圖19示出對應於動作614的一些實施例的剖視圖。圖22至圖23、圖25、圖27、圖29及圖31示出對應於動作614的一些實施例的剖視圖。
在動作616處,在所述多個第一晶粒接墊旁邊及第一半導體晶粒的晶片區之外形成多個重佈線圖案。圖19至圖21示出對應於動作616的一些實施例的剖視圖。圖22至圖23、圖25、圖27、圖29及圖31示出對應於動作616的一些實施例的剖視圖。在一些實施例中,動作614與動作616同時執行,因此第一晶粒接墊與重佈線圖案由相同的材料製成。在一些實施例中,動作614與動作616可單獨地執行,因此第一晶粒接墊與重佈線圖案可包含不同的材料。可可選地省略動作616。
在動作618處,在第一半導體晶粒的第一晶粒接墊以及重佈線圖案之上形成多個凸塊。圖19至圖21示出對應於動作618的一些實施例的剖視圖。圖22至圖23、圖25、圖27、圖29及圖31示出對應於動作618的一些實施例的剖視圖。
在動作620處,在第二半導體晶粒之上形成支撐構件。圖27、圖29及圖31示出對應於動作620的一些實施例的剖視圖。可可選地省略動作620。
在動作622處,在支撐構件之上形成散熱器。圖29示出對應於動作622的一些實施例的剖視圖。可可選地省略動作622。
上述「晶粒接墊優先」製程及「晶粒接墊最末」製程可應用於其他半導體封裝,以便藉由靠近於球陣列放置關鍵半導體晶粒來增強訊號傳輸效能。
圖34至圖39是示意性地示出根據本揭露一些實施例的半導體封裝的剖視圖。
圖34至圖39中的半導體封裝的一些組件相似於上述組件,其中相同的參考編號指代相同的組件。圖34至圖39所示的該些組件的材料及配置可參考在先前實施例中所述的相似組件的材料及配置。
如圖34中所示,半導體封裝71包括兩個半導體晶粒100、介電包封層E1及凸塊B。半導體封裝71是藉由「晶粒接墊優先」製程形成。
所述兩個半導體晶粒100並排地設置。在一些實施例中,半導體晶粒100中的每一者包括前側S1(例如,前表面)及與前側S1相對的背側S2(例如,背表面)。在一些實施例中,半導體晶粒100包括半導體基底102、至少一個元件T1、內連線結構106、晶粒接墊P1及鈍化層112。半導體晶粒100的組件的材料及配置可參考圖11所示先前實施例。在說明通篇中,對應於半導體基底的具有元件或主動層的一側的半導體晶粒100的一側被稱為前側。
在一些實施例中,相鄰的半導體晶粒100可具有相同的功能。在一些實施例中,相鄰的半導體晶粒100可具有不同的功能。另外,半導體晶粒100中的一者的尺寸可與半導體晶粒100中的另一者的尺寸相似或不同。所述尺寸可為高度、寬度、大小、俯視面積或其組合。
介電包封層E1位於半導體晶粒100周圍及之間。在一些實施例中,在製程變化內,介電包封層E1的頂表面與半導體晶粒100的半導體基底102的被暴露出的表面實質上齊平,且在製程變化內,介電包封層E1的底表面與半導體晶粒100的鈍化層112的被暴露出的表面實質上齊平。
凸塊B設置於半導體晶粒100的前側S1處且與半導體晶粒100的晶粒接墊P1實體接觸。凸塊B、晶粒接墊P1及鈍化層112之間的組件關係可參考圖11所示先前實施例。
在一些實施例中,半導體封裝71更包括設置於半導體晶粒100中的一者之上的半導體晶粒200a。半導體晶粒200a可電性耦合至半導體晶粒100中的一或多者。在一些實施例中,半導體晶粒200a包含主動元件或功能性元件,例如電晶體、電容器、電阻器、二極體、光電二極體、熔絲元件及/或其他相似元件。在一些實例中,半導體晶粒200a被稱為「含元件晶粒(device-containing die)」。在一些實施例中,半導體晶粒200a包括半導體基底202、設置於半導體基底202之上的內連線結構206以及設置於內連線結構206之上的接合結構220。在一些實施例中,接合結構220包括至少一個接合膜BF2及嵌置於接合膜BF2中的接合金屬特徵。在一些實施例中,接合金屬特徵包括接合接墊BP21及BP22。半導體晶粒200a的組件的材料及配置可參考圖26所示先前實施例。
在一些實施例中,半導體封裝71更包括設置於半導體晶粒100中的另一者之上的半導體晶粒401。半導體晶粒401可電性耦合至半導體晶粒100中的一或多者。在一些實施例中,半導體晶粒401具有與半導體晶粒200a相似的結構。舉例而言,半導體晶粒401包括半導體基底403、設置於半導體基底403之上的可選內連線結構406以及設置於內連線結構406之上的接合結構420。可省略內連線結構406。在一些實施例中,接合結構420包括至少一個接合膜BF4及嵌置於接合膜BF2中的接合金屬特徵。在一些實施例中,接合金屬特徵包括接合接墊BP41及BP42。
在一些實施例中,半導體晶粒401是虛設半導體晶粒。在本文中,用語「虛設半導體晶粒」指示非操作晶粒、被配置成非使用的晶粒、其中不具有元件的晶粒或者僅用於將晶粒堆疊中的兩個其他晶粒電性耦合於一起的晶粒。在一些實施例中,虛設半導體晶粒實質上不具有任何主動元件或功能性元件,例如電晶體、電容器、電阻器、二極體、光電二極體、熔絲元件及/或其他相似元件。在一些實施例中,可構造不具有主動部件、被動部件或兩者的虛設半導體晶粒。在一些實例中,半導體晶粒401被稱為「無元件晶粒(device-free die)」。然而,虛設半導體晶粒可包括電性連接至相鄰晶粒的導電特徵。在一些實施例中,導電特徵包括基底穿孔、金屬線、金屬插塞、金屬接墊或其組合。具體而言,儘管本申請案的虛設半導體晶粒不包括元件,然而其可用作相鄰晶粒之間的電性連接件。在一些實施例中,本申請案的虛設半導體晶粒可用於使封裝變硬並保護封裝免於變形。在一些實施例中,本申請案的虛設半導體晶粒可被配置成降低熱膨脹係數(coefficient of thermal expansion,CTE)失配並改善所得封裝的翹曲輪廓。然而,本揭露不僅限於此。在其他實施例中,基於製程要求,半導體晶粒401是「主動半導體晶粒(active semiconductor die)」或「含元件晶粒」。
在一些實施例中,半導體封裝71更包括橋結構301。橋結構301在不同晶粒、晶粒堆疊或中介層之間提供電性佈線。橋結構301可包括設置於半導體基底(例如矽基底)上/中的佈線圖案。佈線圖案包括基底穿孔、線、通孔、接墊及/或連接件。在一些實例中,橋結構301被稱為「連接結構(connection structure)」、「橋晶粒(bridge die)」或「矽橋(silicon bridge)」。
在一些實施例中,橋結構301電性連接至橫跨介電包封層E1在半導體晶粒200a與401之間形成的半導體晶粒100。換言之,橋結構301、半導體晶粒200a及401位於同一層級處。在一些實施例中,自俯視圖來看,橋結構301與半導體晶粒100中的至少一者部分地交疊。在一些實施例中,橋結構301具有與半導體晶粒200a相似的結構。舉例而言,橋結構301包括半導體基底303、設置於半導體基底303之上的可選的內連線結構306以及設置於內連線結構306之上的接合結構320。可省略內連線結構306。在一些實施例中,接合結構320包括至少一個接合膜BF3及嵌置於接合膜BF32中的接合金屬特徵。在一些實施例中,接合金屬特徵包括接合接墊BP31及BP32。
在一些實施例中,半導體晶粒100處於同一層級處,且半導體晶粒200a及401以及橋結構301位於同一層級處。在一些實例中,半導體晶粒100被視為「第一層半導體晶粒」,且半導體晶粒200a及401以及橋結構301被視為「第二層半導體晶粒」。
在一些實施例中,半導體封裝71更包括位於第一層半導體晶粒與第二層半導體晶粒之間的接合結構120。在一些實施例中,接合結構120包括至少一個接合膜BF1及嵌置於接合膜BF1中的接合金屬特徵。在一些實施例中,接合金屬特徵包括接合接墊BP11、BP12、BP13、BP14、BP15及BP16。
在一些實施例中,半導體晶粒200a藉由接合結構220及接合結構120接合至對應的半導體晶粒100。具體而言,接合結構220的接合接墊BP21及BP22接合至接合結構120的接合接墊BP11及BP12,且接合結構220的接合膜BF2接合至接合結構120的接合膜BF1。此種接合可被稱為「混合接合」。在一些實施例中,接合接墊BP11及BP21被稱為「主動接合接墊(active bonding pad)」,此乃因其被配置成在相鄰晶粒之間提供接合功能與電性功能二者。接合接墊BP12及BP22被稱為「虛設接合接墊(dummy bonding pad)」,此乃因其被配置成僅在相鄰晶粒之間提供接合功能。
在一些實施例中,橋結構301藉由接合結構320及接合結構120接合至對應的半導體晶粒100。具體而言,接合結構320的接合接墊BP31及BP32接合至接合結構120的接合接墊BP13及BP14,且接合結構420的接合膜BF3接合至接合結構120的接合膜BF1。此種接合被稱為「混合接合」。在一些實施例中,接合接墊BP13及BP31被稱為「主動接合接墊」,此乃因其被配置成在相鄰晶粒之間提供接合功能與電性功能二者。接合接墊BP14及BP32被稱為「虛設接合接墊」,此乃因其被配置成僅在相鄰晶粒之間提供接合功能。
在一些實施例中,半導體晶粒401藉由接合結構420及接合結構120接合至對應的半導體晶粒100。舉例而言,接合結構420的接合接墊BP41及BP42接合至接合結構120的接合接墊BP15及BP16,且接合結構420的接合膜BF4接合至接合結構120的接合膜BF1。此種接合被稱為「混合接合」。在一些實施例中,接合接墊BP15及BP41被稱為「主動接合接墊」,此乃因其被配置成在相鄰晶粒之間提供接合功能與電性功能二者。接合接墊BP16及BP42被稱為「虛設接合接墊」,此乃因其被配置成僅在相鄰晶粒之間提供接合功能。
半導體封裝71中更包括介電包封層E2。在一些實施例中,介電包封層E2位於半導體晶粒200a、橋結構301及半導體晶粒401周圍及之間。在一些實施例中,在製程變化內,介電包封層E2的頂表面與半導體晶粒200a、橋結構301及半導體晶粒401的半導體基底的被暴露出的表面實質上齊平,且在製程變化內,介電包封層E2的底表面與接合結構220、320及420的接合膜實質上齊平。
在一些實施例中,半導體封裝71中可更包括如圖10中所示的重佈線層結構119。在此種情形中,重佈線層結構可設置於接合結構120與介電包封層E1及半導體晶粒100中的每一者之間。在一些實施例中,半導體封裝71中可可選地包括如圖26、圖28及圖30中所示的支撐構件300及/或散熱器400。
圖35所示半導體封裝72相似於圖34所示半導體封裝71,且其間的不同之處在於第一層半導體晶粒的晶粒接墊的形成順序。舉例而言,圖34所示半導體封裝71是利用「晶粒接墊優先」製程形成,而圖35所示半導體封裝72是利用「晶粒接墊最末」製程形成,因此以下詳細闡述其間的不同之處,且本文中不再贅述相似之處。圖35所示組件的材料及配置可參考在先前實施例中所述的相似組件的材料及配置。在圖35所示實施例中,重佈線圖案118設置於半導體晶粒100的晶粒接墊P1周圍及之間,後鈍化層122橫跨半導體晶粒100及介電包封層E2形成,且凸塊B穿透過後鈍化層122且電性連接至晶粒接墊P1及重佈線圖案118。
在一些實施例中,基於製程要求,半導體封裝72中可更包括如圖21中所示的重佈線層結構119。在此種情形中,重佈線層結構可設置於接合結構120與介電包封層E1及半導體晶粒100中的每一者之間。在一些實施例中,根據需要,半導體封裝72中可可選地包括如圖27、圖29及圖31中所示的支撐構件300及/或散熱器400。在一些實施例中,根據需要,半導體封裝72中可更包括如圖23中所示的介電穿孔111。
圖36所示半導體封裝81相似於圖34所示半導體封裝71,其中半導體晶粒401與半導體晶粒100之間的接合機制不同。在圖34所示半導體封裝71中,半導體晶粒401藉由接合結構420與接合結構120的混合接合接合至半導體晶粒100。然而,在圖36所示半導體封裝81中,半導體晶粒401藉由接合結構420與接合結構120的熔融接合接合至半導體晶粒100。舉例而言,圖34所示接合接墊BP15及BP16被自接合結構120省略,且圖34所示接合接墊BP41及BP42被自接合結構420省略。
圖37所示半導體封裝82相似於圖35所示半導體封裝72,其中半導體晶粒401與半導體晶粒100之間的接合機制不同。在圖35所示半導體封裝72中,半導體晶粒401藉由接合結構420與接合結構120的混合接合接合至半導體晶粒100。然而,在圖37所示半導體封裝82中,半導體晶粒401藉由接合結構420與接合結構120的熔融接合接合至半導體晶粒100。舉例而言,圖35所示接合接墊BP15及BP16被自接合結構120省略,且圖35所示接合接墊BP41及BP42被自接合結構420省略。
圖38所示半導體封裝91相似於圖36所示半導體封裝81,其中半導體封裝的第二層層級處的晶粒配置不同。舉例而言,圖36所示半導體封裝81中的半導體晶粒200a被用晶粒堆疊201替換,且介電包封層E2被形成為覆蓋晶粒堆疊201的側壁及頂部以及半導體晶粒401及橋結構301的側壁及頂部。晶粒堆疊201的組件的材料及配置可參考圖24所示先前實施例。
圖39所示半導體封裝92相似於圖37所示半導體封裝82,其中半導體封裝的第二層層級處的晶粒配置不同。舉例而言,圖37所示半導體封裝82中的半導體晶粒200a被用晶粒堆疊201替換,且介電包封層E2被形成為覆蓋晶粒堆疊201的側壁及頂部以及半導體晶粒401及橋結構301的側壁及頂部。晶粒堆疊201的組件的材料及配置可參考圖25所示先前實施例。
以下參照圖34至圖39示出一些實施例的半導體封裝的結構。
在一些實施例中,半導體封裝71/72/81/82/91/92包括兩個第一半導體晶粒100、凸塊B、第一接合結構120及橋結構301。所述兩個第一半導體晶粒100並排地設置。凸塊B設置於第一半導體晶粒100的前側S1處且與第一半導體晶粒100的第一晶粒接墊P1實體接觸。第一接合結構120設置於第一半導體晶粒100的背側S2處且在側向上延伸超過第一半導體晶粒100,其中前側S1與背側S2相對。橋結構301設置於第一接合結構120之上及第一半導體晶粒100之間。
在一些實施例中,半導體封裝71/72/81/82/91/92更包括設置於第一接合結構120之上且對應於第一半導體晶粒100中的一者的第二半導體晶粒200a或晶粒堆疊201。
在一些實施例中,在半導體封裝71/72中,第二半導體晶粒200a或晶粒堆疊201包括第二接合結構220,且第二接合結構220藉由混合接合接合至第一接合結構120。
在一些實施例中,在半導體封裝71/72/81/82/91/92中,半導體封裝更包括設置於第一接合結構120之上且對應於第一半導體晶粒100中的一者的虛設半導體晶粒401。
在一些實施例中,在半導體封裝71/72中,虛設半導體晶粒401包括第三接合結構420,且第三接合結構420藉由混合接合接合至第一接合結構120。
在一些實施例中,在半導體封裝81/82/91/92中,虛設半導體晶粒401包括第三接合結構420,且第三接合結構420藉由熔融接合接合至第一接合結構120。
圖40示出根據一些實施例的形成半導體封裝的方法。儘管將方法示出及/或闡述為一系列動作或事件,然而應領會,所述方法不僅限於所示出的次序或動作。因此,在一些實施例中,動作可按照與所示出的次序不同的次序施行及/或可同時施行。此外,在一些實施例中,所示出的動作或事件可被細分成多個動作或事件,所述多個動作或事件可在單獨的時間施行或與其他動作或子動作同時施行。在一些實施例中,可省略一些所示出的動作或事件,且可包括其他未示出的動作或事件。
圖40所示製程流程與圖32所示製程流程相似,且不同之處在於第一層層級與第二層層級處的半導體晶粒的數目。圖34、圖36及圖38中可能未示出以下動作的一些部件,但其可根據需要包括於半導體封裝中。
在動作700處,提供第一層晶粒,其中第一層晶粒包括並排地佈置的兩個第一半導體晶粒,且第一半導體晶粒中的每一者包括第一半導體基底、穿透過第一半導體基底的第一基底穿孔、形成於第一半導體基底的前表面之上且電性連接至第一基底穿孔的第一內連線結構以及形成於第一內連線結構之上且電性連接至第一內連線結構的多個第一晶粒接墊。
在動作702處,在第一半導體晶粒周圍形成第一介電包封層。
在動作704處,在第一半導體晶粒及第一介電包封層之上形成重佈線層結構。可可選地省略動作704。
在動作706處,在第一半導體晶粒及第一介電包封層之上形成第一接合結構。
在動作708處,將第二層晶粒接合至第一接合結構,其中第二層晶粒包括第二半導體晶粒或晶粒堆疊、橋結構及第三半導體晶粒。
在動作710處,在第二層晶粒周圍形成第二介電包封層。
在動作712處,在第一半導體晶粒的第一晶粒接墊之上形成多個凸塊。
在動作714處,在第二層晶粒之上形成支撐構件。可可選地省略動作714。
在動作716處,在支撐構件之上形成散熱器。可可選地省略動作716。
圖41示出根據一些實施例的形成半導體封裝的方法。儘管將方法示出及/或闡述為一系列動作或事件,然而應領會,所述方法不僅限於所示出的次序或動作。因此,在一些實施例中,動作可按照與所示出的次序不同的次序施行及/或可同時施行。此外,在一些實施例中,所示出的動作或事件可被細分成多個動作或事件,所述多個動作或事件可在單獨的時間施行或與其他動作或子動作同時施行。在一些實施例中,可省略一些所示出的動作或事件,且可包括其他未示出的動作或事件。
圖41所示製程流程與圖33所示製程流程相似,其中第一層層級與第二層層級處的半導體晶粒的數目不同。圖35、圖37及圖39中可能未示出以下動作的一些部件,但其可包括於半導體封裝中。
在動作800處,提供第一層晶粒,其中第一層晶粒包括並排地佈置的兩個第一半導體晶粒,且第一半導體晶粒中的每一者包括第一半導體基底、穿透過第一半導體基底的第一基底穿孔以及形成於第一半導體基底之上且電性連接至第一基底穿孔的第一內連線結構。
在動作802處,在第一半導體晶粒周圍形成第一介電包封層。
在動作804處,在第一半導體晶粒及第一介電包封層之上形成重佈線層結構。可可選地省略動作804。
在動作806處,在第一半導體晶粒及第一介電包封層之上形成第一接合結構。
在動作808處,將第二層晶粒接合至第一接合結構,其中第二層晶粒包括第二半導體晶粒或晶粒堆疊、橋結構及第三半導體晶粒。
在動作810處,在第二層晶粒周圍形成第二介電包封層。
在動作812處,在第一半導體基底的前表面之上及第一半導體晶粒中的每一者的晶片區內形成多個第一晶粒接墊,其中所述多個第一晶粒接墊實體連接至第一內連線結構的頂部金屬圖案。
在動作814處,在所述多個第一晶粒接墊旁邊及第一半導體晶粒中的每一者的晶片區之外形成多個重佈線圖案。可可選地省略動作814。
在動作816處,在第一半導體晶粒的第一晶粒接墊以及重佈線圖案之上形成多個凸塊。
在動作818處,在第二層晶粒之上形成支撐構件。可可選地省略動作818。
在動作820處,在支撐構件之上形成散熱器。可可選地省略動作820。
亦可包括其他特徵及製程。舉例而言,可包括測試結構以幫助對三維(three-dimensional,3D)封裝或三維積體電路(three-dimensional integrated circuit,3DIC)元件進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試接墊(test pad),以便能夠對3D封裝或3DIC進行測試、對探針及/或探針卡(probe card)進行使用及進行類似操作。可對中間結構以及最終結構執行驗證測試。另外,可將本文中所揭露的結構及方法與包括對已知良好晶粒進行中間驗證的測試方法結合使用,以提高良率(yield)並降低成本。
根據本揭露的一些實施例,一種半導體封裝包括第一半導體晶粒、第二半導體晶粒及多個凸塊。第一半導體晶粒具有彼此相對的前側與背側。第二半導體晶粒設置於所述第一半導體晶粒的所述背側處且電性連接至所述第一半導體晶粒。所述多個凸塊設置於所述第一半導體晶粒的所述前側處且實體地接觸所述第一半導體晶粒的第一晶粒接墊。此外,所述第一半導體晶粒的大小小於所述第二半導體晶粒的大小。
根據本揭露的一些實施例,一種半導體結構包括兩個第一半導體晶粒、凸塊、第一接合結構及橋結構。所述兩個第一半導體晶粒並排地設置。所述凸塊設置於所述兩個第一半導體晶粒的前側處且與所述第一半導體晶粒的第一晶粒接墊實體接觸。所述第一接合結構設置於所述第一半導體晶粒的背側處且在側向上延伸超過所述第一半導體晶粒,其中所述前側與所述背側相對。所述橋結構設置於所述第一接合結構之上及所述第一半導體晶粒之間。
在本揭露的一些實施例中,一種形成半導體封裝的方法包括以下操作。提供第一半導體晶粒,其中所述第一半導體晶粒包括第一半導體基底、穿透過所述第一半導體基底的第一基底穿孔以及形成於所述第一半導體基底之上且電性連接至所述第一基底穿孔的第一重佈線結構。將所述第二半導體晶粒接合至所述第一半導體晶粒的所述第一半導體基底的背表面。在所述第一半導體基底的前表面之上及所述第一半導體晶粒的晶片區內形成多個第一晶粒接墊,其中所述多個第一晶粒接墊實體連接至所述第一內連線結構的頂部金屬圖案。在所述第一晶粒接墊之上形成多個凸塊。
以上概述了若干實施例的特徵,以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應領會,他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到,此種等效構造並不背離本揭露的精神及範圍,而且他們可在不背離本揭露的精神及範圍的條件下在本文中作出各種改變、代替及變更。
10、11、20、21、22、31、32、41、42、51、52、61、62、71、72、81、82、91、92:半導體封裝
100:半導體晶粒
102、202:半導體基底
103、203:基底穿孔(TSV)
106、206、306、406:內連線結構
108、208:金屬特徵
108a:最頂金屬特徵
110、210:介電層
112、212:鈍化層
115:聚合物層
117:導電特徵
118:重佈線圖案
119:重佈線層結構
120:接合結構
122:後鈍化層
200、200a:半導體晶粒
200-1:半導體晶粒
200-2:半導體晶粒
201:晶粒堆疊
208a:最頂金屬特徵
220:接合結構
300:支撐構件
301:橋結構
302:接合膜
303:半導體基底
320:接合結構
400:散熱器
401:半導體晶粒
402:熱介面材料(TIM)
403:半導體基底
420:接合結構
500、502、504、506、508、510、512、514、516、518、600、602、604、606、608、610、612、614、616、618、620、622、700、702、704、706、708、710、712、714、716、800、802、804、806、808、810、812、814、816、818、820:動作
B:凸塊
BF1、BF2、BF3、BF4、F1、F
C1、F
C2:接合膜
BP11、BP12、BP13、BP14、BP15、BP16、BP21、BP22、BP31、BP32、BP41、BP42:接合接墊
BV1、BV2:接合通孔
C1、C2:載體
CL:切割線
E1:介電包封層
E2:介電包封層
OP、OP1、OP2:開口
P1:晶粒接墊
P2:晶粒接墊
S1:前側
S2:背側
T1、T2:元件
W1、W2:總寬度
結合附圖閱讀以下詳細說明,會最佳地理解本揭露的各個態樣。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為使論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1至圖10是示意性地示出根據本揭露一些實施例的形成半導體封裝的方法的剖視圖。
圖11是示意性地示出根據本揭露一些實施例的半導體封裝的剖視圖。
圖12至圖21是示意性地示出根據本揭露其他實施例的形成半導體封裝的方法的剖視圖。
圖22至圖23是示意性地示出根據本揭露其他實施例的半導體封裝的剖視圖。
圖24至圖31是示意性地示出根據本揭露一些實施例的半導體封裝的剖視圖。
圖32示出根據一些實施例的形成半導體封裝的方法。
圖33示出根據其他實施例的形成半導體封裝的方法。
圖34至圖39是示意性地示出根據本揭露一些實施例的半導體封裝的剖視圖。
圖40示出根據一些實施例的形成半導體封裝的方法。
圖41示出根據其他實施例的形成半導體封裝的方法。
11:半導體封裝
100:半導體晶粒
102、202:半導體基底
103:基底穿孔(TSV)
106、206:內連線結構
108、208:金屬特徵
108a:最頂金屬特徵
110、210:介電層
112、212:鈍化層
120:接合結構
200:半導體晶粒
208a:最頂金屬特徵
220:接合結構
B:凸塊
BF1、BF2:接合膜
BP11、BP12、BP21、BP22:接合接墊
BV2:接合通孔
E1:介電包封層
E2:介電包封層
P1:晶粒接墊
P2:晶粒接墊
S1:前側
S2:背側
T1、T2:元件
Claims (20)
- 一種半導體封裝,包括: 第一半導體晶粒,具有前側及與所述前側相對的背側; 第二半導體晶粒,設置於所述第一半導體晶粒的所述背側處且電性連接至所述第一半導體晶粒,所述第二半導體晶粒的前側面對所述第一半導體晶粒;以及 多個凸塊,設置於所述第一半導體晶粒的所述前側處,且實體地接觸所述第一半導體晶粒的第一晶粒接墊,其中所述第一半導體晶粒的大小小於所述第二半導體晶粒的大小。
- 如請求項1所述的半導體封裝,其中所述第一晶粒接墊包括鋁接墊。
- 如請求項1所述的半導體封裝,其中所述大小包括高度、長度、寬度、俯視面積或其組合。
- 如請求項1所述的半導體封裝,更包括設置於所述第一半導體晶粒與所述第二半導體晶粒之間的第一接合結構,其中所述第一接合結構的邊緣在側向上延伸超過所述第一半導體晶粒的邊緣。
- 如請求項4所述的半導體封裝,更包括設置於所述第一接合結構與所述第二半導體晶粒之間的第二接合結構,其中所述第二接合結構的邊緣與所述第二半導體晶粒的邊緣對準。
- 如請求項5所述的半導體封裝,其中所述第一接合結構藉由混合接合接合至所述第二接合結構。
- 如請求項1所述的半導體封裝,更包括設置於所述第一半導體晶粒的所述前側處及所述第一半導體晶粒的所述第一晶粒接墊旁邊的重佈線圖案。
- 如請求項1所述的半導體封裝,更包括: 第一介電包封層,在側向上包封所述第一半導體晶粒; 第二介電包封層,設置於所述第一半導體晶粒之上且在側向上包封所述第二半導體晶粒;以及 支撐構件,設置於所述第二半導體晶粒及所述第二介電包封層之上。
- 如請求項1所述的半導體封裝,更包括: 第一介電包封層,在側向上包封所述第一半導體晶粒; 支撐構件,設置於所述第二半導體晶粒之上;以及 第二介電包封層,設置於所述第一半導體晶粒之上且在側向上包封所述第二半導體晶粒及所述支撐構件。
- 如請求項1所述的半導體封裝,更包括設置於所述第二半導體晶粒之上且藉由混合接合接合至所述第二半導體晶粒的第三半導體晶粒。
- 一種半導體封裝,包括: 兩個第一半導體晶粒,並排地設置; 凸塊,設置於所述兩個第一半導體晶粒的前側處且與所述第一半導體晶粒的第一晶粒接墊實體接觸; 第一接合結構,設置於所述第一半導體晶粒的背側處且在側向上延伸超過所述第一半導體晶粒,其中所述前側與所述背側相對;以及 橋結構,設置於所述第一接合結構之上及所述第一半導體晶粒之間。
- 如請求項11所述的半導體封裝,更包括在所述第一半導體晶粒中的一者之上設置於所述第一接合結構之上的第二半導體晶粒或晶粒堆疊。
- 如請求項12所述的半導體封裝,其中所述第二半導體晶粒或所述晶粒堆疊包括第二接合結構,其中所述第二接合結構藉由混合接合接合至所述第一接合結構。
- 如請求項11所述的半導體封裝,更包括設置於所述第一接合結構之上且對應於所述第一半導體晶粒中的一者的虛設半導體晶粒。
- 如請求項14所述的半導體封裝,其中所述虛設半導體晶粒包括第三接合結構,其中所述第三接合結構藉由熔融接合接合至所述第一接合結構。
- 如請求項14所述的半導體封裝,其中所述虛設半導體晶粒包括第三接合結構,其中所述第三接合結構藉由混合接合接合至所述第一接合結構。
- 一種形成半導體封裝的方法,包括: 將第二半導體晶粒接合至第一半導體晶粒的第一半導體基底的背表面,其中第一基底穿孔穿透過所述第一半導體基底,且第一內連線結構位於所述第一半導體基底之上且電性連接至所述第一基底穿孔; 在所述第一半導體基底的前表面之上及所述第一半導體晶粒的晶片區內形成多個第一晶粒接墊,其中所述多個第一晶粒接墊實體連接至所述第一內連線結構的頂部金屬圖案;以及 在所述第一晶粒接墊之上形成多個凸塊。
- 如請求項17所述的形成半導體封裝的方法,更包括在所述多個第一晶粒接墊旁邊及所述第一半導體晶粒的所述晶片區之外形成多個重佈線圖案。
- 如請求項17所述的形成半導體封裝的方法,更包括在提供所述第一半導體晶粒之後且在將所述第二半導體晶粒接合至所述第一半導體晶粒的所述第一半導體基底的所述背表面之前: 在所述第一半導體晶粒周圍形成第一介電包封層;以及 在所述第一半導體晶粒及所述第一介電包封層之上形成第一接合結構。
- 如請求項19所述的形成半導體封裝的方法,更包括在形成所述第一介電包封層之後且在形成所述第一接合結構之前,在所述第一半導體晶粒及所述第一介電包封層之上形成重佈線層結構。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202163136752P | 2021-01-13 | 2021-01-13 | |
US63/136,752 | 2021-01-13 | ||
US17/315,487 US11735544B2 (en) | 2021-01-13 | 2021-05-10 | Semiconductor packages with stacked dies and methods of forming the same |
US17/315,487 | 2021-05-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW202240840A true TW202240840A (zh) | 2022-10-16 |
Family
ID=81409268
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW110124364A TW202240840A (zh) | 2021-01-13 | 2021-07-02 | 半導體封裝及其形成方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US11735544B2 (zh) |
KR (1) | KR102628146B1 (zh) |
CN (1) | CN114464577A (zh) |
DE (1) | DE102021112660A1 (zh) |
TW (1) | TW202240840A (zh) |
Family Cites Families (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8883561B2 (en) | 2011-04-30 | 2014-11-11 | Stats Chippac, Ltd. | Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP |
US8970023B2 (en) * | 2013-02-04 | 2015-03-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and methods of forming same |
KR20150053088A (ko) * | 2013-11-07 | 2015-05-15 | 에스케이하이닉스 주식회사 | 반도체 소자 및 제조 방법 |
KR102245003B1 (ko) * | 2014-06-27 | 2021-04-28 | 삼성전자주식회사 | 오버행을 극복할 수 있는 반도체 패키지 및 그 제조방법 |
KR102360381B1 (ko) * | 2014-12-01 | 2022-02-11 | 삼성전자주식회사 | 적층 구조를 갖는 반도체 소자 및 그 제조방법 |
US9768145B2 (en) | 2015-08-31 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming multi-die package structures including redistribution layers |
US9899355B2 (en) | 2015-09-30 | 2018-02-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional integrated circuit structure |
US9893042B2 (en) * | 2015-12-14 | 2018-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US9741695B2 (en) * | 2016-01-13 | 2017-08-22 | Globalfoundries Inc. | Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding |
DE102016116083A1 (de) | 2016-08-30 | 2018-03-01 | Kwiggle®Bike GmbH | Rahmenteil für ein Fahrzeug |
US10833052B2 (en) | 2016-10-06 | 2020-11-10 | Micron Technology, Inc. | Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods |
US20220238440A1 (en) * | 2016-12-29 | 2022-07-28 | Intel Corporation | Bare-die smart bridge connected with copper pillars for system-in-package apparatus |
US10199356B2 (en) * | 2017-02-24 | 2019-02-05 | Micron Technology, Inc. | Semiconductor device assembles with electrically functional heat transfer structures |
US10529698B2 (en) * | 2017-03-15 | 2020-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of forming same |
US10879214B2 (en) | 2017-11-01 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die stack structure and method of fabricating the same |
US10535636B2 (en) | 2017-11-15 | 2020-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrating passive devices in package structures |
US10141259B1 (en) * | 2017-12-22 | 2018-11-27 | Micron Technology, Inc. | Semiconductor devices having electrically and optically conductive vias, and associated systems and methods |
US10510629B2 (en) * | 2018-05-18 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method of forming same |
US10651131B2 (en) * | 2018-06-29 | 2020-05-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Supporting InFO packages to reduce warpage |
US11114383B2 (en) * | 2018-10-23 | 2021-09-07 | Micron Technology, Inc. | Semiconductor devices having integrated optical components |
KR102593085B1 (ko) * | 2018-11-21 | 2023-10-24 | 삼성전자주식회사 | 반도체 장치, 반도체 패키지 및 이의 제조 방법 |
US10811390B2 (en) * | 2019-01-21 | 2020-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die stack structure and method of fabricating the same and package |
US11121052B2 (en) | 2019-01-31 | 2021-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out device, 3D-IC system, and method |
TWI709212B (zh) | 2019-03-05 | 2020-11-01 | 台灣積體電路製造股份有限公司 | 晶圓接合結構及其形成方法 |
US11189599B2 (en) | 2019-05-30 | 2021-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | System formed through package-in-package formation |
US20200402942A1 (en) | 2019-06-24 | 2020-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and method manufacturing the same |
KR20210013429A (ko) * | 2019-07-25 | 2021-02-04 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
KR20210048638A (ko) * | 2019-10-23 | 2021-05-04 | 삼성전자주식회사 | 반도체 패키지 |
US11239203B2 (en) * | 2019-11-01 | 2022-02-01 | Xilinx, Inc. | Multi-chip stacked devices |
KR20210072181A (ko) * | 2019-12-06 | 2021-06-17 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
US11239174B2 (en) * | 2019-12-27 | 2022-02-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
US11605597B2 (en) * | 2020-04-17 | 2023-03-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
US11545434B2 (en) * | 2020-06-05 | 2023-01-03 | Intel Corporation | Vertical die-to-die interconnects bridge |
KR20210151569A (ko) * | 2020-06-05 | 2021-12-14 | 삼성전자주식회사 | 반도체 장치 및 이를 포함하는 반도체 패키지 |
US11710688B2 (en) * | 2020-07-07 | 2023-07-25 | Mediatek Inc. | Semiconductor package structure |
US11587894B2 (en) * | 2020-07-09 | 2023-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package and method of fabricating the same |
KR20220007443A (ko) * | 2020-07-10 | 2022-01-18 | 삼성전자주식회사 | 반도체 패키지 |
KR20220008093A (ko) * | 2020-07-13 | 2022-01-20 | 삼성전자주식회사 | 반도체 패키지 및 반도체 패키지의 제조 방법 |
KR20220030685A (ko) * | 2020-09-03 | 2022-03-11 | 삼성전자주식회사 | 반도체 패키지 |
KR20220058683A (ko) * | 2020-10-29 | 2022-05-10 | 삼성전자주식회사 | 반도체 패키지 |
KR20220067212A (ko) * | 2020-11-17 | 2022-05-24 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
KR20220081036A (ko) * | 2020-12-08 | 2022-06-15 | 삼성전자주식회사 | 반도체 패키지 및 반도체 패키지의 제조 방법 |
US20220199575A1 (en) * | 2020-12-18 | 2022-06-23 | Intel Corporation | Microelectronic structures including bridges |
US20220199539A1 (en) * | 2020-12-18 | 2022-06-23 | Intel Corporation | Microelectronic structures including bridges |
US20220199562A1 (en) * | 2020-12-22 | 2022-06-23 | Intel Corporation | Assembly of 2xd module using high density interconnect bridges |
CN112687619A (zh) * | 2020-12-25 | 2021-04-20 | 上海易卜半导体有限公司 | 形成半导体封装件的方法及半导体封装件 |
-
2021
- 2021-05-10 US US17/315,487 patent/US11735544B2/en active Active
- 2021-05-17 DE DE102021112660.6A patent/DE102021112660A1/de active Pending
- 2021-06-30 KR KR1020210085869A patent/KR102628146B1/ko active IP Right Grant
- 2021-07-02 TW TW110124364A patent/TW202240840A/zh unknown
-
2022
- 2022-01-12 CN CN202210032805.9A patent/CN114464577A/zh active Pending
-
2023
- 2023-07-03 US US18/346,550 patent/US20230343737A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
US20220223553A1 (en) | 2022-07-14 |
CN114464577A (zh) | 2022-05-10 |
KR102628146B1 (ko) | 2024-01-23 |
KR20220102541A (ko) | 2022-07-20 |
DE102021112660A1 (de) | 2022-07-14 |
US20230343737A1 (en) | 2023-10-26 |
US11735544B2 (en) | 2023-08-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11443995B2 (en) | Integrated circuit package and method | |
TWI708355B (zh) | 半導體封裝 | |
TWI681466B (zh) | 半導體結構及積體電路封裝的形成方法 | |
US11854921B2 (en) | Integrated circuit package and method | |
TW202029449A (zh) | 封裝結構及其製造方法 | |
TWI790503B (zh) | 積體電路封裝及其形成方法 | |
TWI803310B (zh) | 積體電路元件和其形成方法 | |
TW202038343A (zh) | 半導體裝置及其形成方法 | |
KR20240005646A (ko) | 집적 회로 패키지 및 방법 | |
US20230369274A1 (en) | Integrated circuit package and method of forming same | |
US20230260941A1 (en) | Semiconductor Device and Method | |
TWI776646B (zh) | 積體電路封裝體及其形成方法 | |
KR20230147495A (ko) | 혼합 본드 타입을 포함하는 반도체 패키지 및 이의 형성 방법 | |
KR102628146B1 (ko) | 반도체 패키지 및 이를 형성하는 방법 | |
CN220692015U (zh) | 半导体装置 | |
US11664315B2 (en) | Structure with interconnection die and method of making same | |
US11652037B2 (en) | Semiconductor package and method of manufacture | |
US20230387063A1 (en) | Integrated circuit package and method of forming same | |
TW202341399A (zh) | 積體電路封裝及其形成方法 | |
TW202407821A (zh) | 積體電路封裝及其形成方法 |