CN112687619A - 形成半导体封装件的方法及半导体封装件 - Google Patents

形成半导体封装件的方法及半导体封装件 Download PDF

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Publication number
CN112687619A
CN112687619A CN202011559083.XA CN202011559083A CN112687619A CN 112687619 A CN112687619 A CN 112687619A CN 202011559083 A CN202011559083 A CN 202011559083A CN 112687619 A CN112687619 A CN 112687619A
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conductive bump
layer
semiconductor substrate
over
semiconductor
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CN202011559083.XA
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李维平
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Shanghai Yibu Semiconductor Co ltd
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Shanghai Yibu Semiconductor Co ltd
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Priority to CN202011559083.XA priority Critical patent/CN112687619A/zh
Publication of CN112687619A publication Critical patent/CN112687619A/zh
Priority to KR1020210171515A priority patent/KR20220092785A/ko
Priority to TW110148251A priority patent/TWI797904B/zh
Priority to US17/562,936 priority patent/US20220208669A1/en
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Abstract

本发明提供了形成半导体封装件的方法及半导体封装件，方法包括：提供半导体衬底，在半导体衬底上方附接互连器件；形成至少两个芯片，其中，每个芯片的一侧表面形成有至少一个第一导电凸块和至少一个第二导电凸块，第二导电凸块的高度高于第一导电凸块；将至少两个芯片附接至半导体衬底和互连器件的上方表面，使每个芯片的第二导电凸块接合至半导体衬底的上方表面，且每个芯片的第一导电凸块接合至互连器件的上方表面。利用上述方法，能够实现封装件内部的高密度互联布线，封装工艺简单且成本低廉。

Description

形成半导体封装件的方法及半导体封装件
技术领域
本发明属于半导体领域，具体涉及形成半导体封装件的方法及半导体封装件。
背景技术
本部分旨在为权利要求书中陈述的本发明的实施方式提供背景或上下文。此处的描述不因为包括在本部分中就承认是现有技术。
随着半导体行业的快速发展，电子产品的微型化与复杂化需求日益增高，对于半导体封装件内部的高密度互联的需求随之提升。
现有技术中，为了能够实现封装件的高密度布线功能，采用EMIB(EmbeddedMulti-Die Interconnect Bridge,嵌入式多核心互联桥接)封装技术，其通过将互连桥嵌入BGA层压基板内，利用互连桥顶部的多个RDL层来互连多个管芯以实现了封装件的高密度布线功能，然而这种封装工艺要求必须在常规的BGA层压基板中形成用于容纳各种尺寸大小互连桥的空腔，制造成本较高。
发明内容
针对上述现有技术中存在的问题，提出了形成半导体封装件的方法及半导体封装件，利用这种方法及封装件，能够解决上述问题。
本发明提供了以下方案。
第一方面，提供一种形成半导体封装件的方法，包括：提供半导体衬底，在半导体衬底上方附接互连器件；形成至少两个芯片，其中，每个芯片的一侧表面形成有至少一个第一导电凸块和至少一个第二导电凸块，第二导电凸块的高度高于第一导电凸块；将至少两个芯片附接至半导体衬底和互连器件的上方表面，使每个芯片的第二导电凸块接合至半导体衬底的上方表面，且每个芯片的第一导电凸块接合至互连器件的上方表面。
在一些实施方式中，在半导体衬底上方附接互连器件之前，还包括：提供硅晶圆，硅晶圆具有相对的第一侧面和第二侧面；在硅晶圆的第一侧面形成重布线结构；在重布线结构的表面形成多个第一接合焊盘；根据第一导电凸块和第二导电凸块之间的高度差，对硅晶圆的第二侧面进行减薄；对减薄后的硅晶圆进行划片，以形成互连器件。
在一些实施方式中，在硅晶圆的第一侧面和第二侧面之间形成有垂直TSV通孔。
在一些实施方式中，方法还包括：利用混合键合工艺将互连器件附接至半导体衬底上方。
在一些实施方式中，对硅晶圆的第二侧面进行减薄，还包括：使用支撑晶片临时粘合在硅晶圆的第一侧面，以在进行减薄时支撑硅晶圆；其中，支撑晶片为硅晶片或玻璃。
在一些实施方式中，方法还包括形成芯片的步骤，包括：提供半导体器件，半导体器件至少包括：半导体晶圆和位于半导体晶圆上方的至少两种金属焊盘；在半导体器件的上方形成晶种层，晶种层与每个金属焊盘电连接；在晶种层的上方形成第一光刻胶层；在第一光刻胶层中形成第一开口以暴露晶种层，其中，第一开口位于至少两种金属焊盘中的至少一个第一金属焊盘的至少一部分的正上方；在第一开口中形成第一高度的第一导电凸块；去除第一光刻胶层；去除第一光刻胶层之后，在晶种层之上形成第二光刻胶层；在第二光刻胶层中形成第二开口以暴露晶种层，其中，第二开口位于至少两种金属焊盘中的至少一个第二金属焊盘的至少一部分的正上方；在第二开口中形成第二高度的第二导电凸块，第二高度高于第一高度；去除第二光刻胶层，形成芯片。
在一些实施方式中，方法还包括：在半导体晶圆和至少两种金属焊盘的上方形成图案化的钝化层，钝化层将每个金属焊盘的至少一部分暴露出来；晶种层至少覆盖在每个金属焊盘的暴露表面。
在一些实施方式中，形成图案化的钝化层之后，方法还包括：在钝化层的表面形成聚合物层。
在一些实施方式中，方法还包括：在聚合物层和至少两种金属焊盘的暴露表面上溅射金属材料以形成晶种层；以及，在去除第二光刻胶层之后，蚀刻去除晶种层的曝光部分。
在一些实施方式中，方法还包括：在晶种层上方沉淀第一厚度的第一光刻胶层，在第一光刻胶层上方放置用于图案化第一光刻胶层的第一掩模层以形成第一开口；以及，去除第一光刻胶层之后，在晶种层上方沉淀第二厚度的第二光刻胶层，在第二光刻胶层上方放置用于图案化第二光刻胶层的第二掩模层以形成第二开口。
在一些实施方式中，还包括：在去除第一光刻胶层之后，在晶种层的上方形成完全覆盖第一导电凸块的第二光刻胶层。
在一些实施方式中，第一导电凸块和第二导电凸块的粗细度不同。
在一些实施方式中，互连器件的上方表面形成有多个第一接合焊盘，半导体衬底上方形成有多个第二接合焊盘，将至少两个芯片附接至半导体衬底和互连器件的上方表面，还包括：将至少两个芯片倒装安装在半导体衬底和互连器件的上方，使得每个芯片的多个第一导电凸块对应接合至互连器件的多个第一接合焊盘，同时使每个芯片的多个第二导电凸块接合至半导体衬底的上方表面暴露的多个第二接合焊盘。
在一些实施方式中，第一导电凸块和第二导电凸块包括凸块下金属。
在一些实施方式中，将至少两个芯片附接至半导体衬底和互连器件的上方表面之后，方法还包括：在半导体衬底的上方附接一罩体，罩体将互连器件和至少两个芯片容纳在其中；在半导体衬底的下方形成栅格阵列，以用于将封装件接合至PCB板。
在一些实施方式中，所述互连器件的材料为硅晶片或玻璃。第二方面，提供一种半导体封装件，包括：半导体衬底；互连器件，附接在半导体衬底的上方表面；至少两个芯片，每个芯片的一侧表面形成有至少一个第一导电凸块和至少一个第二导电凸块，其中第二导电凸块的高度高于第一导电凸块；至少两个芯片附接于半导体衬底和互连器件的上方表面，其中每个芯片的第二导电凸块接合至半导体衬底的上方表面，且每个芯片的第一导电凸块接合至互连器件的上方表面。
在一些实施方式中，互连器件包括：硅晶圆层，硅晶圆层具有相对的第一侧面和第二侧面；重布线结构，附接在硅晶圆的第一侧面；多个第一接合焊盘，形成于重布线结构的表面；其中，互连器件的厚度根据第一导电凸块和第二导电凸块之间的高度差确定。
在一些实施方式中，硅晶圆的第一侧面和第二侧面之间形成有垂直TSV通孔。
在一些实施方式中，互连器件利用混合键合工艺附接至半导体衬底上方。
在一些实施方式中，芯片包括：半导体器件，其至少包括：半导体晶圆和位于半导体晶圆上方的至少两种金属焊盘；晶种层，形成在半导体器件的上方表面且与每个金属焊盘电连接；至少一个第一导电凸块，其具有第一高度，形成在晶种层的上方且位于至少两种金属焊盘中的至少一个第一金属焊盘的至少一部分的正上方；至少一个第二导电凸块，其具有第二高度，形成在晶种层的上方且位于至少两种金属焊盘中的至少一个第二金属焊盘的至少一部分的正上方。
在一些实施方式中，还包括：钝化层，形成在半导体晶圆和至少两种金属焊盘的上方，其中，钝化层中的图案化开口将每个金属焊盘的至少一部分暴露出来；晶种层至少覆盖在每个金属焊盘的暴露表面。
在一些实施方式中，还包括：形成在钝化层的表面的聚合物层。
在一些实施方式中，第一导电凸块和第二导电凸块的粗细度不同。
在一些实施方式中，半导体衬底上方形成有多个第二接合焊盘，其中，每个芯片的多个第一导电凸块对应接合至互连器件的多个第一接合焊盘，且每个芯片的多个第二导电凸块对应接合至半导体衬底的上方表面暴露的多个第二接合焊盘。
在一些实施方式中，第一导电凸块和第二导电凸块包括凸块下金属。
在一些实施方式中，封装件还包括：罩体，附接在半导体衬底的上方，罩体将互连器件和至少两个芯片容纳在其中；栅格阵列，形成在半导体衬底的下方，用于将封装件接合至PCB 板。
在一些实施方式中，所述互连器件的材料为硅晶片或玻璃。
本申请实施例采用的上述至少一个技术方案能够达到以下有益效果：通过上述封装方法，无需采用复杂的封装技术就能够实现封装件内部的高密度互联布线，封装工艺简单且成本低廉，对于在ASIC和小型芯片而言非常有价值。
应当理解，上述说明仅是本发明技术方案的概述，以便能够更清楚地了解本发明的技术手段，从而可依照说明书的内容予以实施。为了让本发明的上述和其它目的、特征和优点能够更明显易懂，以下特举例说明本发明的具体实施方式。
附图说明
通过阅读下文的示例性实施例的详细描述，本领域普通技术人员将明白本文所述的优点和益处以及其他优点和益处。附图仅用于示出示例性实施例的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的标号表示相同的部件。在附图中：
图1为根据本发明一实施例的形成半导体封装件的方法的流程示意图；
图2为根据本发明一实施例的半导体封装件的结构示意图；
图3为根据本发明另一实施例的半导体封装件的结构示意图；
图4A为根据本发明一实施例的互联器件的结构示意图；
图4B为根据本发明另一实施例的互联器件的结构示意图；
图5A至图5J为根据本发明一实施例在形成芯片的过程中的中间阶段的截面示意图。
在附图中，相同或对应的标号表示相同或对应的部分。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
应理解，诸如“包括”或“具有”等术语旨在指示本说明书中所公开的特征、数字、步骤、行为、部件、部分或其组合的存在，并且不旨在排除一个或多个其他特征、数字、步骤、行为、部件、部分或其组合存在的可能性。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个 (或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
另外还需要说明的是，在不冲突的情况下，本发明中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本发明。
图1是示出根据本发明一些实施例的形成半导体封装件的方法的流程图。图2示出根据图1示出方法所形成的示例性的半导体封装件的结构示意图。以下参考图1和图2描述本发明实施例的形成半导体封装件的方法。
步骤101、提供半导体衬底10，在半导体衬底10上方附接互连器件20。
其中，半导体衬底10可以是常规的层压形成基板(Regular Laminate BuildupSubstrate)，该半导体衬底10的底部可以包括多个BGA焊盘，顶部可以形成有焊料预涂层，在BGA焊盘和焊料预涂层之间可以形成有激光盲孔(laser via)、电镀穿孔(platedthrough hole)。具体地，可以预先利用芯片附着膜(Die attach film)将互连器件20的一侧表面附接至半导体衬底10。
步骤102、形成至少两个芯片30，在每个芯片的一侧表面形成至少一个第一导电凸块31 和至少一个第二导电凸块32，其中第二导电凸块32的高度高于第一导电凸块31。
其中，每个芯片表面形成的第一导电凸块31和第二导电凸块分布在不同的区域
步骤103、将至少两个芯片30附接至半导体衬底10和互连器件20的上方表面，使每个芯片30的第二导电凸块32接合至半导体衬底10的上方表面，且每个芯片的第一导电凸块31接合至互连器件20的上方表面。
在一些实施方式中，互连器件20的上方表面形成有多个第一接合焊盘(未示出)，半导体衬底10上方形成有多个第二接合焊盘(未示出)，步骤103可以具体包括：将至少两个芯片30倒装安装在半导体衬底10和互连器件20的上方，使得每个芯片30的多个第一导电凸块31对应接合至互连器件20的多个第一接合焊盘上，同时使每个芯片的多个第二导电凸块32对应接合至半导体衬底10的上方表面暴露的多个第二接合焊盘上。
在一些实施方式中，可以使用热压接合技术实现第一导电凸块31与第一接合焊盘的接合，以及实现第二导电凸块32与第二接合焊盘的接合。
在一些实施方式中，第一导电凸块31和第二导电凸块32包括凸块下金属(Under-bump metal，简称UBM)。在传统封装技术的一个方面，诸如晶圆级封装(WLP)、再分布层(RDL)可以形成在半导体晶圆上方以及电连接至半导体晶圆中的有源器件。然后可以形成诸如位于凸块下金属上的焊料球的外部输入/输出(I/O)焊盘(pad)，以通过RDL电连接至半导体晶圆。
在一些实施方式中，参考图3，在步骤103之后，本申请实施例所提供的方法还可以包括：
步骤104、在半导体衬底10的上方附接一罩体40，罩体40将互连器件20和至少两个芯片30容纳在其中。
其中，在半导体衬底、芯片和互连器件之间的空隙中填充底填胶(underfill)。
步骤105、在半导体衬底10的下方形成栅格阵列50，以用于将封装件接合至PCB板60。
在一些实施方式中，在半导体衬底10上方附接互连器件20之前，为了获得该互连器件 20，还可以执行以下步骤21至25以形成互连器件20。图4A示出了示例性互连器件20的结构示意图，以下参考图4A对步骤21至25进行详细描述。
步骤21、提供硅晶圆(Si wafer)21，硅晶圆21具有相对的第一侧面和第二侧面。
步骤22、在硅晶圆21的第一侧面形成重布线结构22。其中，例如可以在硅晶圆的第一侧面光刻、电镀出该重布线(Redistribution Layers，RDL)结构
步骤23、在重布线结构22的表面形成多个第一接合焊盘23。其中，第一接合焊盘可以使用包括铜、铝、银、金、钛、其任何组合或者本领域中已知的任何其他适当材料。
步骤24、根据第一导电凸块31和第二导电凸块32之间的高度差，对硅晶圆21的第二侧面进行减薄。应当理解，对硅晶圆21的第二侧面进行减薄，以使最后形成的互连器件的厚度与第一导电凸块和第二导电凸块的高度差保持一致，如此可以使得具有不同高度差的第一导电凸块31和第二导电凸块32的芯片30能够倒装安装在半导体衬底10和互连器件20的上方。例如，可以使用化学机械抛光工艺、蚀刻工艺、其他方法将部分的硅晶圆材料从第二侧面去除。
步骤25、对减薄后的硅晶圆进行划片，以形成多个互连器件。
可选地，也可以只形成一个互连器件，此时无需进行划片处理即可得到互连器件。
在一些实施方式中，图4B示出了另外一种示例性互连器件的结构示意图，其中，硅晶圆21的第一侧面和第二侧面之间形成有若干个垂直硅通孔24(Through Silicon Via，简称 TSV)。应当理解，TSV技术通过铜、钨、多晶硅等导电物质的填充，实现硅通孔的垂直电气互连，从而可以通过垂直互连减小互联长度，实现器件集成的小型化程度。可选地，可以利用混合键合(Hybrid Bonding)工艺将具有垂直硅通孔24的互连器件的第二侧面附接至半导体衬底上方，从而实现更小的凸点间距，提供更高的互连密度。当然，也可以使用热压结合工艺实现上述附接。
在一些实施方式中，在互连器件20的形成过程中，在对硅晶圆21的第二侧面进行减薄时，可以使用支撑晶片临时粘合在硅晶圆21的第一侧面，以在进行减薄时支撑硅晶圆21。其中，支撑晶片为硅晶片或玻璃。其中，如果使用玻璃作为支撑晶片，则可以使用可紫外线剥离的临时粘合膜将该玻璃支撑晶片临时粘合在硅晶圆21的第一侧面，并在减薄动作完成之后将其剥离。
在一些实施方式中，互连器件的材料为硅晶片或玻璃。
参考图2，芯片30的一侧表面形成有多个第一导电凸块31和多个第二导电凸块32，且第二导电凸块32的高度高于第一导电凸块31。
应当理解，形成于芯片表面的凸块间距可以进行调整变化，但凸块的尺寸通常固定为一个值，这是由于大尺寸凸块在电镀过程中往往比小尺寸凸块镀得更快，进而造成凸块高度的不均匀，芯片良品率降低。
在一些实施方式中，针对在同一晶圆上难以形成不同尺寸高度的导电凸块的技术问题。可以执行步骤31～35以形成该芯片。图5A至图5J示出了形成一种示例性芯片30的各个中间过程的示意图，其具体示出了如何形成如图5J所示出的具有一个第一导电凸块和一个第二导电凸块的芯片的示例。
本实施例中，参考图5A至图5J对步骤31～步骤35进行详细描述，然而应当理解，利用相似的步骤就可以形成图2所示出的具有多个第一导电凸块31和多个第二导电凸块32的芯片，本申请不再赘述。
步骤31、提供半导体器件。
参考图5A，半导体器件至少包括：半导体晶圆301和位于半导体晶圆301上方的至少两种金属焊盘，比如示出的第一金属焊盘311和第二金属焊盘321。
上述半导体器件的形成步骤可以包括：提供半导体晶圆301。其中，半导体晶圆301例如可以是硅晶圆(Si wafer)。将至少两个金属焊盘耦合至半导体晶圆301之上。金属焊盘可以使用包括铜、铝、银、金、钛、其任何组合或者本领域中已知的任何其他适当材料。金属焊盘之间的尺寸可以彼此不同，比如可以是尺寸较小的第一金属焊盘311和尺寸较大的第二金属焊盘321，可以将尺寸不同的两个金属焊盘以一定的间距设置在硅晶圆之上，金属焊盘彼此之间互不接触。
在一些实施例中，上述半导体器件的形成步骤可以还包括：在半导体晶圆301和至少两个金属焊盘的上方形成图案化的钝化层302，钝化层302将每个金属焊盘的至少一部分暴露出来。其中，钝化层302覆盖半导体晶圆301的一部分和每个金属焊盘的一部分。参考图5B，可以在半导体晶圆301的上方形成钝化层302，该钝化层302覆盖第一金属焊盘311和第二金属焊盘321的边缘部分，该钝化层302中形成的图案化开口将每个金属焊盘的中心部分暴露出来。钝化层302可以使用包括SiO2,SiNx，磷硅玻璃(PSG)或本领域中已知的适应于在芯片表面进行钝化处理的任何适当材料。根据一些实施例，图案化的钝化层302在每个金属焊盘的上方形成第三开口(未示出)。
在一些实施例中，参考图5B,可以在钝化层302的上方表面和侧表面形成聚合物层303。聚合物层303可以包括光敏由诸如聚酰亚胺(PI)、聚苯并恶唑(PBO)、苯并环丁烯(BCB)或其任何组合或者本领域中已知的任何其他适当材料等的聚合物形成。聚合物层303可以耦合到钝化层302并且与第一金属焊盘311、第二金属焊盘321接触。具有覆盖聚合物层303的钝化层302的集电成路芯片具有很低的漏电流、较强的机械性能以及耐化学腐蚀性能。同时，也可有效地遮挡潮气，增加元器件的抗潮湿能力，从而改善了芯片的电学性能，降低了生产成本。参考图5B，可以在钝化层302的暴露表面覆盖聚合物层303,聚合物层303延伸至钝化层302在金属焊盘处形成的开口中，并使每个金属焊盘的中心部分保持暴露状态。
步骤32、在半导体器件的上方形成晶种层304，晶种层304与每个金属焊盘电连接。
根据本发明的一些实施例，晶种层304是包括多个层的复合层。例如，该晶种层304可以包括处于下层的钛层和处于上层的铜层，由此可以分别与每个金属焊盘电连接。根据可选实施例，晶种层304也可以是单层，例如，其可以是铜层。可以理解，该晶种层304还可以使用其他合适的导电材料。
参考图5C，可以在聚合物层303和两个金属焊盘的暴露表面上溅射金属材料以形成晶种层304，该晶种层304可包括处于下层的钛层和处于上层的铜层。应当理解，在后续的封装步骤中需要将晶种层304的暴露表面蚀刻去除，以避免发生电路故障。
在步骤33、在晶种层304的上方形成第一光刻胶层305。在第一光刻胶层305中形成第一开口307以暴露晶种层304，其中，第一开口307位于至少两种金属焊盘中的至少一个第一金属焊盘311的至少一部分的正上方。在第一开口307中形成第一高度的第一导电凸块31。去除第一光刻胶层305。
在一些实施例中，参考图5D，可以在晶种层304上方沉淀第一厚度的第一光刻胶层305，在第一光刻胶层305上方放置用于图案化第一光刻胶层305的第一掩模层306，以形成第一开口307，具体而言，可以在提供的半导体器件和晶种层304的上方铺满光刻胶，以形成第一厚度的第一光刻胶层305，可以依据所需的设置在第一金属焊盘311之上的金属部件的高度尺寸确定该第一厚度。接下来将第一掩模层306放置在第一光刻胶层305上方。第一掩模层306可以是光刻掩模，其包括允许光通过的透明部分，以及用于阻挡光通过的不透明部分，光束投射在第一掩模层306上，从而曝光第一光刻胶层305位于透明部分正下方的部分，并且未曝光第一光刻胶层305位于不透明部分正下方的其它部分，从而形成该第一开口307。可以依据所需的第一金属焊盘311的凸块下金属的底部尺寸确定第一开口307的开口面积。
在一些实施例中，参考图5E，该第一导电凸块31可以包括凸块下金属。可选地，该第一导电凸块还可以包括其它用于提供芯片电气互连的金属接口。本实施例以凸块下金属为例进行描述，本申请对此不作具体限制。
参考图5E，在晶种层304的上方且在第一开口307中形成第一高度的第一导电凸块31, 通常情况下，实施电镀工艺在该第一开口307中填满金属材料以形成该第一导电凸块31。换言之，该第一高度大致等同于第一光刻胶层305在第三开口处的第一厚度。第一导电凸块31 的底部通过晶种层304与第一金属焊盘311电连接。根据本发明的一些实施例，第一导电凸块31的形成步骤具体可以包括：在晶种层304之上且在该第一开口307中电镀形成含铜(Cu) 层312，含铜(Cu)层312例如可以为铜柱，在该含铜(Cu)层312的上方形成含镍(Ni)层313，在该含镍(Ni)层313的上方形成膏状软钎焊料314，具体可以为锡银化合物层(例如SnAg1.8％)。
接下来，可以利用光刻胶剥离工艺中去除第一光刻胶层305，并且产生的结构如图5F 所示。
在步骤34、参考图5G，去除第一光刻胶层305之后，在晶种层304之上形成第二光刻胶层308。在第二光刻胶层308中形成第二开口310以暴露晶种层304，其中，第二开口310 位于至少两种金属焊盘中的至少一个第二金属焊盘321的至少一部分的正上方。在第二开口310中形成第二高度的第二导电凸块32，第二高度高于第一高度。
在一些实施例中，参考图5G，在去除第一光刻胶层305之后，在晶种层304的上方形成完全覆盖第一导电凸块31的第二光刻胶层308。在这种情况下，第二光刻胶层308比该第一导电凸块31更高，因此其被光刻胶覆盖并保护。
在一些实施例中，参考图5G，与第一开口307的形成工艺相同或相似，去除第一光刻胶层305之后，在晶种层304上方沉淀第二厚度的第二光刻胶层308，在第二光刻胶层308上方放置用于图案化第二光刻胶层308的第二掩模层309以形成第二开口310。具体而言，去除第一光刻胶层305之后，再次在晶种层304之上铺满光刻胶以形成第二厚度的第二光刻胶层308，可以依据所需的设置在第二金属焊盘321之上的第二导电凸块的高度尺寸确定该第二厚度。接下来将第二掩模层309放置在第二光刻胶层308上方。第二掩模层309同样可以是光刻掩模，其包括允许光通过的透明部分，以及用于阻挡光通过的不透明部分，该透明部分可以设置在第二金属焊盘321的至少部分的正上方，光束投射在第二掩模层309上，从而曝光第二光刻胶层308位于透明部分正下方的部分，也即大致位于第二金属焊盘321正上方的晶种层304，并且未曝光第二光刻胶层308位于不透明部分正下方的其它部分，从而形成该第二开口310。可以依据所需的第二金属焊盘321上的第二导电凸块的底部尺寸自由确定第二开口310的开口面积。
在一些实施例中，参考图5H，该第二导电凸块32可以包括凸块下金属。可选地，该第二导电凸块32还可以为其它用于提供芯片电气互连的金属接口。本实施例以凸块下金属为例进行描述，本申请对此不作具体限制。
参考图5H，与第一导电凸块31的形成工艺相同或相似，在晶种层304的上方且第二开口310中形成第二高度的第二导电凸块32,通常情况下，实施电镀工艺在该第二开口310中填满金属材料以形成该第二导电凸块32。换言之，该第二高度大致等同于第二光刻胶层308 在第三开口处的第二厚度。第二导电凸块32的底部通过晶种层304与第二金属焊盘321电连接。根据本发明的一些实施方式，第二导电凸块32的形成步骤具体可以包括：在晶种层304之上且在该第二开口310中电镀形成含铜(Cu)层322，含铜(Cu)层322例如可以为铜柱，在该含铜(Cu)层322的上方形成含镍(Ni)层323，在该含镍(Ni)层323的上方形成膏状软钎焊料324，具体可以为锡银化合物层(例如SnAg1.8％)，例如SnAg1.8％。
步骤35、去除第二光刻胶层308，形成芯片。去除第二光刻胶层308的步骤与第一光刻胶层305的去除工艺相同或相似，可以利用光刻胶剥离工艺中去除第二光刻胶层308，并且产生的结构如图5I所示。
在一些实施例中，参考图5H，接下来通过蚀刻去除晶种层304的先前由光刻胶覆盖的曝光部分，同时保留晶种层304的由第一导电凸块31和第二导电凸块32覆盖的未曝光部分。通过回流(reflow)焊工艺，重新熔化预先分配到金属焊盘顶部的膏状软钎焊料314和324，通过融化材料的液体表面张力产生如图5J所示的结构，最终形成焊料凸点。
根据以上步骤31-35，通过采用新的封装结构设计和独特的工艺流程，能够在晶圆上形成多种尺寸不同、且凸点高度受控制的晶圆凸点，这对于使用同一封装中的高密度互连布线的ASIC裸芯片和小型芯片的集成而言非常有价值。
根据以上实施方式的各个方面，通过将若干个具有不同凸点高度的芯片集成附接至半导体衬底和互连器件的上方，能够以简单的封装工艺以及低廉的封装成本实现封装件内部的高密度互联布线。
本发明还提供了一种半导体封装件，其采用如上述实施例的方法制造成形。
参考图2，半导体封装件包括：半导体衬底10；互连器件20，附接在半导体衬底的上方表面；至少两个芯片30，每个芯片30的一侧表面形成有至少一个第一导电凸块31和至少一个第二导电凸块32，其中第二导电凸块32的高度高于第一导电凸块31；至少两个芯片30附接于半导体衬底和互连器件20的上方表面，其中每个芯片30的第二导电凸块32接合至半导体衬底的上方表面，且每个芯片30的第一导电凸块31接合至互连器件20的上方表面。
在一些实施方式中，参考图4A，互连器件20包括：硅晶圆层21，硅晶圆层21具有相对的第一侧面和第二侧面；重布线结构22，附接在硅晶圆的第一侧面；多个第一接合焊盘23，形成于重布线结构22的表面；其中，互连器件20的厚度根据第一导电凸块31和第二导电凸块32之间的高度差确定。
在另外一些实施方式中，参考图4B，硅晶圆的第一侧面和第二侧面之间形成有若干个垂直硅通孔24(Through Silicon Via，简称TSV)。可选地，具有垂直硅通孔24的互连器件可以利用混合键合(Hybrid Bonding)工艺将其第二侧面附接至半导体衬底上方，从而实现更高的互连密度。
在一些实施方式中，芯片30包括：半导体器件，其至少包括：半导体晶圆和位于半导体晶圆上方的至少两种金属焊盘；晶种层，形成在半导体器件的上方表面且与每个金属焊盘电连接；至少一个第一导电凸块31，其具有第一高度，形成在晶种层的上方且位于至少两种金属焊盘中的至少一个第一金属焊盘的至少一部分的正上方；至少一个第二导电凸块32，其具有第二高度，形成在晶种层的上方且位于至少两种金属焊盘中的至少一个第二金属焊盘的至少一部分的正上方。
在一些实施方式中，还包括：钝化层，形成在半导体晶圆和至少两种金属焊盘的上方，其中，钝化层中的图案化开口将每个金属焊盘的至少一部分暴露出来。晶种层至少覆盖在每个金属焊盘的暴露表面。
在一些实施方式中，还包括：形成在钝化层的表面的聚合物层。
在一些实施方式中，第一导电凸块和第二导电凸块的粗细度不同。
在一些实施方式中，半导体衬底上方形成有多个第二接合焊盘，其中，每个芯片30的多个第一导电凸块31对应接合至互连器件20的多个第一接合焊盘，且每个芯片30的多个第二导电凸块32对应接合至半导体衬底的上方表面暴露的多个第二接合焊盘。
在一些实施方式中，第一导电凸块31和第二导电凸块32包括凸块下金属。
在一些实施方式中，参见图3，封装件还包括：罩体40，附接在半导体衬底的上方，罩体40将互连器件20和至少两个芯片30容纳在其中；栅格阵列，形成在半导体衬底的下方，用于将封装件接合至PCB板60。
虽然已经参考若干具体实施方式描述了本发明的精神和原理，但是应该理解，本发明并不限于所公开的具体实施方式，对各方面的划分也不意味着这些方面中的特征不能组合以进行受益，这种划分仅是为了表述的方便。本发明旨在涵盖所附权利要求的精神和范围内所包括的各种修改和等同布置。

Claims (28)

1.一种形成半导体封装件的方法，其特征在于，包括：
提供半导体衬底，在所述半导体衬底上方附接互连器件；
形成至少两个芯片，其中，每个所述芯片的一侧表面形成有至少一个第一导电凸块和至少一个第二导电凸块，所述第二导电凸块的高度高于第一导电凸块；
将所述至少两个芯片附接至所述半导体衬底和所述互连器件的上方表面，使每个所述芯片的所述第二导电凸块接合至所述半导体衬底的上方表面，且每个所述芯片的所述第一导电凸块接合至所述互连器件的上方表面。
2.根据权利要求1所述的方法，其特征在于，在所述半导体衬底上方附接互连器件之前，还包括：
提供硅晶圆，所述硅晶圆具有相对的第一侧面和第二侧面；
在所述硅晶圆的所述第一侧面形成重布线结构；
在所述重布线结构的表面形成多个第一接合焊盘；
根据所述第一导电凸块和所述第二导电凸块之间的高度差，对所述硅晶圆的所述第二侧面进行减薄；
对减薄后的所述硅晶圆进行划片，以形成所述互连器件。
3.根据权利要求2所述的方法，其特征在于，在所述硅晶圆的所述第一侧面和所述第二侧面之间形成有垂直TSV通孔。
4.根据权利要求3所述的方法，其特征在于，所述方法还包括：
利用混合键合工艺将所述互连器件附接至所述半导体衬底上方。
5.根据权利要求2所述的方法，其特征在于，对所述硅晶圆的所述第二侧面进行减薄，还包括：
使用支撑晶片临时粘合在所述硅晶圆的所述第一侧面，以在进行减薄时支撑所述硅晶圆；
其中，所述支撑晶片为硅晶片或玻璃。
6.根据权利要求1所述的方法，其特征在于，所述方法还包括形成所述芯片的步骤，包括：
提供半导体器件，所述半导体器件至少包括：半导体晶圆和位于所述半导体晶圆上方的至少两种金属焊盘；
在所述半导体器件的上方形成晶种层，所述晶种层与每个所述金属焊盘电连接；
在所述晶种层的上方形成第一光刻胶层；在所述第一光刻胶层中形成第一开口以暴露所述晶种层，其中，所述第一开口位于所述至少两种金属焊盘中的至少一个第一金属焊盘的至少一部分的正上方；在所述第一开口中形成第一高度的第一导电凸块；去除所述第一光刻胶层；
去除所述第一光刻胶层之后，在所述晶种层之上形成第二光刻胶层；在所述第二光刻胶层中形成第二开口以暴露所述晶种层，其中，所述第二开口位于所述至少两种金属焊盘中的至少一个第二金属焊盘的至少一部分的正上方；在所述第二开口中形成第二高度的第二导电凸块，所述第二高度高于所述第一高度；
去除所述第二光刻胶层，形成所述芯片。
7.根据权利要求6所述的方法，其特征在于，所述方法还包括：
在所述半导体晶圆和所述至少两种金属焊盘的上方形成图案化的钝化层，所述钝化层将每个所述金属焊盘的至少一部分暴露出来；
所述晶种层至少覆盖在每个所述金属焊盘的暴露表面。
8.根据权利要求7所述的方法，其特征在于，形成图案化的钝化层之后，所述方法还包括：在所述钝化层的表面形成聚合物层。
9.根据权利要求8所述的方法，其特征在于，所述方法还包括：
在所述聚合物层和所述至少两种金属焊盘的暴露表面上溅射金属材料以形成所述晶种层；以及，
在去除所述第二光刻胶层之后，蚀刻去除所述晶种层的曝光部分。
10.根据权利要求6所述的方法，其特征在于，所述方法还包括：
在所述晶种层上方沉淀第一厚度的所述第一光刻胶层，在所述第一光刻胶层上方放置用于图案化所述第一光刻胶层的第一掩模层以形成所述第一开口；以及，
去除所述第一光刻胶层之后，在所述晶种层上方沉淀第二厚度的所述第二光刻胶层，在所述第二光刻胶层上方放置用于图案化所述第二光刻胶层的第二掩模层以形成所述第二开口。
11.根据权利要求6所述的方法，其特征在于，还包括：
在所述去除所述第一光刻胶层之后，在所述晶种层的上方形成完全覆盖所述第一导电凸块的所述第二光刻胶层。
12.根据权利要求1所述的方法，其特征在于，所述第一导电凸块和所述第二导电凸块的粗细度不同。
13.根据权利要求1所述的方法，其特征在于，所述互连器件的上方表面形成有多个第一接合焊盘，所述半导体衬底上方形成有多个第二接合焊盘，将所述至少两个芯片附接至所述半导体衬底和所述互连器件的上方表面，还包括：
将所述至少两个芯片倒装安装在半导体衬底和所述互连器件的上方，使得所述每个所述芯片的多个所述第一导电凸块对应接合至所述互连器件的多个所述第一接合焊盘，同时使每个所述芯片的多个所述第二导电凸块接合至所述半导体衬底的上方表面暴露的多个所述第二接合焊盘。
14.根据权利要求1所述的方法，其特征在于，所述第一导电凸块和所述第二导电凸块包括凸块下金属。
15.根据权利要求1所述的方法，其特征在于，将所述至少两个芯片附接至所述半导体衬底和所述互连器件的上方表面之后，所述方法还包括：
在所述半导体衬底的上方附接一罩体，所述罩体将所述互连器件和所述至少两个芯片容纳在其中；
在所述半导体衬底的下方形成栅格阵列，以用于将所述封装件接合至PCB板。
16.根据权利要求1所述的方法，其特征在于，所述互连器件的材料为硅晶片或玻璃。
17.一种半导体封装件，其特征在于，包括：
半导体衬底；
互连器件，附接在所述半导体衬底的上方表面；
至少两个芯片，每个所述芯片的一侧表面形成有至少一个第一导电凸块和至少一个第二导电凸块，其中所述第二导电凸块的高度高于第一导电凸块；所述至少两个芯片附接于所述半导体衬底和所述互连器件的上方表面，其中每个所述芯片的所述第二导电凸块接合至所述半导体衬底的上方表面，且每个所述芯片的所述第一导电凸块接合至所述互连器件的上方表面。
18.根据权利要求17所述的封装件，其特征在于，所述互连器件包括：
硅晶圆层，所述硅晶圆层具有相对的第一侧面和第二侧面；
重布线结构，附接在所述硅晶圆的所述第一侧面；
多个第一接合焊盘，形成于所述重布线结构的表面；
其中，所述互连器件的厚度根据所述第一导电凸块和所述第二导电凸块之间的高度差确定。
19.根据权利要求18所述的封装件，其特征在于，所述硅晶圆的所述第一侧面和所述第二侧面之间形成有垂直TSV通孔。
20.根据权利要求19所述的封装件，其特征在于，所述互连器件利用混合键合工艺附接至所述半导体衬底上方。
21.根据权利要求17所述的封装件，其特征在于，所述芯片包括：
半导体器件，其至少包括：半导体晶圆和位于所述半导体晶圆上方的至少两种金属焊盘；
晶种层，形成在所述半导体器件的上方表面且与每个所述金属焊盘电连接；
至少一个第一导电凸块，其具有第一高度，形成在所述晶种层的上方且位于所述至少两种金属焊盘中的至少一个第一金属焊盘的至少一部分的正上方；
至少一个第二导电凸块，其具有第二高度，形成在所述晶种层的上方且位于所述至少两种金属焊盘中的至少一个第二金属焊盘的至少一部分的正上方。
22.根据权利要求21所述的封装件，其特征在于，还包括：
钝化层，形成在所述半导体晶圆和所述至少两种金属焊盘的上方，其中，所述钝化层中的图案化开口将每个所述金属焊盘的至少一部分暴露出来；所述晶种层至少覆盖在每个所述金属焊盘的暴露表面。
23.根据权利要求22所述的封装件，其特征在于，还包括：形成在所述钝化层的表面的聚合物层。
24.根据权利要求17所述的封装件，其特征在于，所述第一导电凸块和所述第二导电凸块的粗细度不同。
25.根据权利要求17所述的封装件，其特征在于，所述半导体衬底上方形成有多个第二接合焊盘，其中，每个所述芯片的多个所述第一导电凸块对应接合至所述互连器件的多个所述第一接合焊盘，且每个所述芯片的多个所述第二导电凸块对应接合至所述半导体衬底的上方表面暴露的多个所述第二接合焊盘。
26.根据权利要求17所述的封装件，其特征在于，所述第一导电凸块和所述第二导电凸块包括凸块下金属。
27.根据权利要求17所述的封装件，其特征在于，所述封装件还包括：
罩体，附接在所述半导体衬底的上方，所述罩体将所述互连器件和所述至少两个芯片容纳在其中；
栅格阵列，形成在所述半导体衬底的下方，用于将所述封装件接合至PCB板。
28.根据权利要求17所述的封装件，其特征在于，所述互连器件的材料为硅晶片或玻璃。
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