TW202226494A - 形成半導體封裝件的方法及半導體封裝件 - Google Patents

形成半導體封裝件的方法及半導體封裝件 Download PDF

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TW202226494A
TW202226494A TW110148251A TW110148251A TW202226494A TW 202226494 A TW202226494 A TW 202226494A TW 110148251 A TW110148251 A TW 110148251A TW 110148251 A TW110148251 A TW 110148251A TW 202226494 A TW202226494 A TW 202226494A
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layer
semiconductor substrate
wafer
over
conductive bump
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TW110148251A
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TWI797904B (zh
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維平 李
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大陸商上海易卜半導體有限公司
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Abstract

本發明提供了形成半導體封裝件的方法及半導體封裝件，方法包括：提供半導體襯底，在半導體襯底上方附接互連器件；形成至少兩個晶片，其中，每個晶片的一側表面形成有至少一個第一導電凸塊和至少一個第二導電凸塊，第二導電凸塊的高度高於第一導電凸塊；將至少兩個晶片附接至半導體襯底和互連器件的上方表面，使每個晶片的第二導電凸塊接合至半導體襯底的上方表面，且每個晶片的第一導電凸塊接合至互連器件的上方表面。利用上述方法，能夠實現封裝件內部的高密度互聯佈線，封裝工藝簡單且成本低廉。

Description

形成半導體封裝件的方法及半導體封裝件
本發明屬於半導體領域，具體涉及形成半導體封裝件的方法及半導體封裝件。
本部分旨在為申請專利範圍中陳述的本發明的實施方式提供背景或上下文。此處的描述不因為包括在本部分中就承認是現有技術。
隨著半導體行業的快速發展，電子產品的微型化與複雜化需求日益增高，對於半導體封裝件內部的高密度互聯的需求隨之提升。
現有技術中，為了能夠實現封裝件的高密度佈線功能，採用EMIB（Embedded Multi-Die Interconnect Bridge，嵌入式多核心互聯橋接）封裝技術，其通過將互連橋嵌入BGA層壓基板內，利用互連橋頂部的多個RDL層來互連多個管芯以實現了封裝件的高密度佈線功能，然而這種封裝工藝要求必須在常規的BGA層壓基板中形成用於容納各種尺寸大小互連橋的空腔，製造成本較高。
針對上述現有技術中存在的問題，提出了形成半導體封裝件的方法及半導體封裝件，利用這種方法及封裝件，能夠解決上述問題。
本發明提供了以下方案。
第一方面，提供一種形成半導體封裝件的方法，包括：提供半導體襯底，在半導體襯底上方附接互連器件；形成至少兩個晶片，其中，每個晶片的一側表面形成有至少一個第一導電凸塊和至少一個第二導電凸塊，第二導電凸塊的高度高於第一導電凸塊；將至少兩個晶片附接至半導體襯底和互連器件的上方表面，使每個晶片的第二導電凸塊接合至半導體襯底的上方表面，且每個晶片的第一導電凸塊接合至互連器件的上方表面。
在一些實施方式中，在半導體襯底上方附接互連器件之前，還包括： 提供矽晶圓，矽晶圓具有相對的第一側面和第二側面；在矽晶圓的第一側面形成重佈線結構；在重佈線結構的表面形成多個第一接合焊盤；根據第一導電凸塊和第二導電凸塊之間的高度差，對矽晶圓的第二側面進行減薄；對減薄後的矽晶圓進行劃片，以形成互連器件。
在一些實施方式中，在矽晶圓的第一側面和第二側面之間形成有垂直TSV通孔。
在一些實施方式中，方法還包括：利用混合鍵合工藝將互連器件附接至半導體襯底上方。
在一些實施方式中，對矽晶圓的第二側面進行減薄，還包括：使用支撐晶片臨時黏合在矽晶圓的第一側面，以在進行減薄時支撐矽晶圓；其中，支撐晶片為矽晶片或玻璃。
在一些實施方式中，方法還包括形成晶片的步驟，包括：提供半導體器件，半導體器件至少包括：半導體晶圓和位於半導體晶圓上方的至少兩種金屬焊盤；在半導體器件的上方形成晶種層，晶種層與每個金屬焊盤電連接；在晶種層的上方形成第一光刻膠層；在第一光刻膠層中形成第一開口以暴露晶種層，其中，第一開口位於至少兩種金屬焊盤中的至少一個第一金屬焊盤的至少一部分的正上方；在第一開口中形成第一高度的第一導電凸塊；去除第一光刻膠層；去除第一光刻膠層之後，在晶種層之上形成第二光刻膠層；在第二光刻膠層中形成第二開口以暴露晶種層，其中，第二開口位於至少兩種金屬焊盤中的至少一個第二金屬焊盤的至少一部分的正上方；在第二開口中形成第二高度的第二導電凸塊，第二高度高於第一高度；去除第二光刻膠層，形成晶片。
在一些實施方式中，方法還包括：在半導體晶圓和至少兩種金屬焊盤的上方形成圖案化的鈍化層，鈍化層將每個金屬焊盤的至少一部分暴露出來；晶種層至少覆蓋在每個金屬焊盤的暴露表面。
在一些實施方式中，形成圖案化的鈍化層之後，方法還包括：在鈍化層的表面形成聚合物層。
在一些實施方式中，方法還包括：在聚合物層和至少兩種金屬焊盤的暴露表面上濺射金屬材料以形成晶種層；以及，在去除第二光刻膠層之後，蝕刻去除晶種層的曝光部分。
在一些實施方式中，方法還包括：在晶種層上方沉澱第一厚度的第一光刻膠層，在第一光刻膠層上方放置用於圖案化第一光刻膠層的第一掩模層以形成第一開口；以及，去除第一光刻膠層之後，在晶種層上方沉澱第二厚度的第二光刻膠層，在第二光刻膠層上方放置用於圖案化第二光刻膠層的第二掩模層以形成第二開口。
在一些實施方式中，還包括：在去除第一光刻膠層之後，在晶種層的上方形成完全覆蓋第一導電凸塊的第二光刻膠層。
在一些實施方式中，第一導電凸塊和第二導電凸塊的粗細度不同。
在一些實施方式中，互連器件的上方表面形成有多個第一接合焊盤，半導體襯底上方形成有多個第二接合焊盤，將至少兩個晶片附接至半導體襯底和互連器件的上方表面，還包括：將至少兩個晶片倒裝安裝在半導體襯底和互連器件的上方，使得每個晶片的多個第一導電凸塊對應接合至互連器件的多個第一接合焊盤，同時使每個晶片的多個第二導電凸塊接合至半導體襯底的上方表面暴露的多個第二接合焊盤。
在一些實施方式中，第一導電凸塊和第二導電凸塊包括凸塊下金屬。
在一些實施方式中，將至少兩個晶片附接至半導體襯底和互連器件的上方表面之後，方法還包括：在半導體襯底的上方附接一罩體，罩體將互連器件和至少兩個晶片容納在其中；在半導體襯底的下方形成柵格陣列，以用於將封裝件接合至PCB板。
在一些實施方式中，所述互連器件的材料為矽晶片或玻璃。第二方面，提供一種半導體封裝件，包括：半導體襯底；互連器件，附接在半導體襯底的上方表面；至少兩個晶片，每個晶片的一側表面形成有至少一個第一導電凸塊和至少一個第二導電凸塊，其中第二導電凸塊的高度高於第一導電凸塊；至少兩個晶片附接於半導體襯底和互連器件的上方表面，其中每個晶片的第二導電凸塊接合至半導體襯底的上方表面，且每個晶片的第一導電凸塊接合至互連器件的上方表面。
在一些實施方式中，互連器件包括：矽晶圓層，矽晶圓層具有相對的第一側面和第二側面；重佈線結構，附接在矽晶圓的第一側面；多個第一接合焊盤，形成於重佈線結構的表面；其中，互連器件的厚度根據第一導電凸塊和第二導電凸塊之間的高度差確定。
在一些實施方式中，矽晶圓的第一側面和第二側面之間形成有垂直TSV通孔。
在一些實施方式中，互連器件利用混合鍵合工藝附接至半導體襯底上方。
在一些實施方式中，晶片包括：半導體器件，其至少包括：半導體晶圓和位於半導體晶圓上方的至少兩種金屬焊盤；晶種層，形成在半導體器件的上方表面且與每個金屬焊盤電連接；至少一個第一導電凸塊，其具有第一高度，形成在晶種層的上方且位於至少兩種金屬焊盤中的至少一個第一金屬焊盤的至少一部分的正上方；至少一個第二導電凸塊，其具有第二高度，形成在晶種層的上方且位於至少兩種金屬焊盤中的至少一個第二金屬焊盤的至少一部分的正上方。
在一些實施方式中，還包括：鈍化層，形成在半導體晶圓和至少兩種金屬焊盤的上方，其中，鈍化層中的圖案化開口將每個金屬焊盤的至少一部分暴露出來；晶種層至少覆蓋在每個金屬焊盤的暴露表面。
在一些實施方式中，還包括：形成在鈍化層的表面的聚合物層。
在一些實施方式中，第一導電凸塊和第二導電凸塊的粗細度不同。
在一些實施方式中，半導體襯底上方形成有多個第二接合焊盤，其中，每個晶片的多個第一導電凸塊對應接合至互連器件的多個第一接合焊盤，且每個晶片的多個第二導電凸塊對應接合至半導體襯底的上方表面暴露的多個第二接合焊盤。
在一些實施方式中，第一導電凸塊和第二導電凸塊包括凸塊下金屬。
在一些實施方式中，封裝件還包括：罩體，附接在半導體襯底的上方，罩體將互連器件和至少兩個晶片容納在其中；柵格陣列，形成在半導體襯底的下方，用於將封裝件接合至PCB板。
在一些實施方式中，所述互連器件的材料為矽晶片或玻璃。
本申請實施例採用的上述至少一個技術方案能夠達到以下有益效果：通過上述封裝方法，無需採用複雜的封裝技術就能夠實現封裝件內部的高密度互聯佈線，封裝工藝簡單且成本低廉，對於在ASIC和小型晶片而言非常有價值。
應當理解，上述說明僅是本發明技術方案的概述，以便能夠更清楚地瞭解本發明的技術手段，從而可依照說明書的內容予以實施。為了讓本發明的上述和其它目的、特徵和優點能夠更明顯易懂，以下特舉例說明本發明的具體實施方式。
下面將參照附圖更詳細地描述本公開的示例性實施例。雖然附圖中顯示了本公開的示例性實施例，然而應當理解，可以以各種形式實現本公開而不應被這裡闡述的實施例所限制。相反，提供這些實施例是為了能夠更透徹地理解本公開，並且能夠將本公開的範圍完整的傳達給本領域的技術人員。
以下公開內容提供了許多用於實現本發明的不同特徵的不同實施例或實例。下面描述了元件和佈置的具體實例以簡化本發明。當然，這些僅僅是實例，而不旨在限制本發明。此外，本發明可在各個實施例中重複參考標號和/或字元。該重複是為了簡單和清楚的目的，並且其本身不指示所討論的各個實施例和/或配置之間的關係。
應理解，諸如“包括”或“具有”等術語旨在指示本說明書中所公開的特徵、數位、步驟、行為、部件、部分或其組合的存在，並且不旨在排除一個或多個其他特徵、數位、步驟、行為、部件、部分或其組合存在的可能性。
而且，為便於描述，在此可以使用諸如“ 在… 之下”、“ 在… 下方”、“ 下部”、“ 在… 之上”、“ 上部”等空間相對術語，以描述如圖所示的一個元件或部件與另一個(或另一些)原件或部件的關係。除了圖中所示的方位外，空間相對術語旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋轉90度或在其它方位上)，而本文使用的空間相對描述符可以同樣地作出相應的解釋。
另外還需要說明的是，在不衝突的情況下，本發明中的實施例及實施例中的特徵可以相互組合。下面將參考附圖並結合實施例來詳細說明本發明。
圖1是示出根據本發明一些實施例的形成半導體封裝件的方法的流程圖。圖2示出根據圖1示出方法所形成的示例性的半導體封裝件的結構示意圖。以下參考圖1和圖2描述本發明實施例的形成半導體封裝件的方法。
步驟101、提供半導體襯底10，在半導體襯底10上方附接互連器件20。
其中，半導體襯底10可以是常規的層壓形成基板（Regular Laminate Buildup Substrate），該半導體襯底10的底部可以包括多個BGA焊盤，頂部可以形成有焊料預塗層，在BGA焊盤和焊料預塗層之間可以形成有鐳射盲孔（laser via）、電鍍穿孔（plated through hole）。具體地，可以預先利用晶片附著膜(Die attach film)將互連器件20的一側表面附接至半導體襯底10。
步驟102、形成至少兩個晶片30，在每個晶片的一側表面形成至少一個第一導電凸塊31和至少一個第二導電凸塊32，其中第二導電凸塊32的高度高於第一導電凸塊31。
其中，每個晶片表面形成的第一導電凸塊31和第二導電凸塊分佈在不同的區域
步驟103、將至少兩個晶片30附接至半導體襯底10和互連器件20的上方表面，使每個晶片30的第二導電凸塊32接合至半導體襯底10的上方表面，且每個晶片的第一導電凸塊31接合至互連器件20的上方表面。
在一些實施方式中，互連器件20的上方表面形成有多個第一接合焊盤（未示出），半導體襯底10上方形成有多個第二接合焊盤（未示出），步驟103可以具體包括：將至少兩個晶片30倒裝安裝在半導體襯底10和互連器件20的上方，使得每個晶片30的多個第一導電凸塊31對應接合至互連器件20的多個第一接合焊盤上，同時使每個晶片的多個第二導電凸塊32對應接合至半導體襯底10的上方表面暴露的多個第二接合焊盤上。
在一些實施方式中，可以使用熱壓接合技術實現第一導電凸塊31與第一接合焊盤的接合，以及實現第二導電凸塊32與第二接合焊盤的接合。
在一些實施方式中，第一導電凸塊31和第二導電凸塊32包括凸塊下金屬（Under-bump metal，簡稱UBM）。在傳統封裝技術的一個方面，諸如晶圓級封裝(WLP)、再分佈層(RDL)可以形成在半導體晶圓上方以及電連接至半導體晶圓中的有源器件。然後可以形成諸如位於凸塊下金屬上的焊料球的外部輸入/輸出(I/O)焊盤(pad)，以通過RDL電連接至半導體晶圓。
在一些實施方式中，參考圖3，在步驟103之後，本申請實施例所提供的方法還可以包括：
步驟104、在半導體襯底10的上方附接一罩體40，罩體40將互連器件20和至少兩個晶片30容納在其中。
其中，在半導體襯底、晶片和互連器件之間的空隙中填充底填膠（underfill）。
步驟105、在半導體襯底10的下方形成柵格陣列50，以用於將封裝件接合至PCB板60。
在一些實施方式中，在半導體襯底10上方附接互連器件20之前，為了獲得該互連器件20，還可以執行以下步驟21至25以形成互連器件20。圖4A示出了示例性互連器件20的結構示意圖，以下參考圖4A對步驟21至25進行詳細描述。
步驟21、提供矽晶圓（Si wafer）21，矽晶圓21具有相對的第一側面和第二側面。
步驟22、在矽晶圓21的第一側面形成重佈線結構22。其中，例如可以在矽晶圓的第一側面光刻、電鍍出該重佈線(Redistribution Layers，RDL)結構
步驟23、在重佈線結構22的表面形成多個第一接合焊盤23。其中，第一接合焊盤可以使用包括銅、鋁、銀、金、鈦、其任何組合或者本領域中已知的任何其他適當材料。
步驟24、根據第一導電凸塊31和第二導電凸塊32之間的高度差，對矽晶圓21的第二側面進行減薄。應當理解，對矽晶圓21的第二側面進行減薄，以使最後形成的互連器件的厚度與第一導電凸塊和第二導電凸塊的高度差保持一致，如此可以使得具有不同高度差的第一導電凸塊31和第二導電凸塊32的晶片30能夠倒裝安裝在半導體襯底10和互連器件20的上方。例如，可以使用化學機械拋光工藝、蝕刻工藝、其他方法將部分的矽晶圓材料從第二側面去除。
步驟25、對減薄後的矽晶圓進行劃片，以形成多個互連器件。
可選地，也可以只形成一個互連器件，此時無需進行劃片處理即可得到互連器件。
在一些實施方式中，圖4B示出了另外一種示例性互連器件的結構示意圖，其中，矽晶圓21的第一側面和第二側面之間形成有若干個垂直矽通孔24（Through Silicon Via，簡稱TSV）。應當理解，TSV技術通過銅、鎢、多晶矽等導電物質的填充，實現矽通孔的垂直電氣互連，從而可以通過垂直互連減小互聯長度，實現器件集成的小型化程度。可選地，可以利用混合鍵合（Hybrid Bonding）工藝將具有垂直矽通孔24的互連器件的第二側面附接至半導體襯底上方，從而實現更小的凸點間距，提供更高的互連密度。當然，也可以使用熱壓結合工藝實現上述附接。
在一些實施方式中，在互連器件20的形成過程中，在對矽晶圓21的第二側面進行減薄時，可以使用支撐晶片臨時黏合在矽晶圓21的第一側面，以在進行減薄時支撐矽晶圓21。其中，支撐晶片為矽晶片或玻璃。其中，如果使用玻璃作為支撐晶片，則可以使用可紫外線剝離的臨時黏合膜將該玻璃支撐晶片臨時黏合在矽晶圓21的第一側面，並在減薄動作完成之後將其剝離。
在一些實施方式中，互連器件的材料為矽晶片或玻璃。
參考圖2，晶片30的一側表面形成有多個第一導電凸塊31和多個第二導電凸塊32，且第二導電凸塊32的高度高於第一導電凸塊31。
應當理解，形成於晶片表面的凸塊間距可以進行調整變化，但凸塊的尺寸通常固定為一個值，這是由於大尺寸凸塊在電鍍過程中往往比小尺寸凸塊鍍得更快，進而造成凸塊高度的不均勻，晶片良品率降低。
在一些實施方式中，針對在同一晶圓上難以形成不同尺寸高度的導電凸塊的技術問題。可以執行步驟31～35以形成該晶片。圖5A至圖5J示出了形成一種示例性晶片30的各個中間過程的示意圖，其具體示出了如何形成如圖5J所示出的具有一個第一導電凸塊和一個第二導電凸塊的晶片的示例。
本實施例中，參考圖5A至圖5J對步驟31～步驟35進行詳細描述，然而應當理解，利用相似的步驟就可以形成圖2所示出的具有多個第一導電凸塊31和多個第二導電凸塊32的晶片，本申請不再贅述。
步驟31、提供半導體器件。
參考圖5A，半導體器件至少包括：半導體晶圓301和位於半導體晶圓301上方的至少兩種金屬焊盤，比如示出的第一金屬焊盤311和第二金屬焊盤321。
上述半導體器件的形成步驟可以包括：提供半導體晶圓301。其中，半導體晶圓301例如可以是矽晶圓（Si wafer）。將至少兩個金屬焊盤耦合至半導體晶圓301之上。金屬焊盤可以使用包括銅、鋁、銀、金、鈦、其任何組合或者本領域中已知的任何其他適當材料。金屬焊盤之間的尺寸可以彼此不同，比如可以是尺寸較小的第一金屬焊盤311和尺寸較大的第二金屬焊盤321，可以將尺寸不同的兩個金屬焊盤以一定的間距設置在矽晶圓之上，金屬焊盤彼此之間互不接觸。
在一些實施例中，上述半導體器件的形成步驟可以還包括：在半導體晶圓301和至少兩個金屬焊盤的上方形成圖案化的鈍化層302，鈍化層302將每個金屬焊盤的至少一部分暴露出來。其中，鈍化層302覆蓋半導體晶圓301的一部分和每個金屬焊盤的一部分。參考圖5B，可以在半導體晶圓301的上方形成鈍化層302，該鈍化層302覆蓋第一金屬焊盤311和第二金屬焊盤321的邊緣部分，該鈍化層302中形成的圖案化開口將每個金屬焊盤的中心部分暴露出來。鈍化層302可以使用包括SiO2, SiNx，磷矽玻璃(PSG)或本領域中已知的適應於在晶片表面進行鈍化處理的任何適當材料。根據一些實施例，圖案化的鈍化層302在每個金屬焊盤的上方形成第三開口（未示出）。
在一些實施例中，參考圖5B,可以在鈍化層302的上方表面和側表面形成聚合物層303。聚合物層303可以包括光敏由諸如聚醯亞胺(PI)、聚苯並惡唑(PBO)、苯並環丁烯(BCB) 或其任何組合或者本領域中已知的任何其他適當材料等的聚合物形成。聚合物層303可以耦合到鈍化層302並且與第一金屬焊盤311、第二金屬焊盤321接觸。具有覆蓋聚合物層303的鈍化層302的集電成路晶片具有很低的漏電流、較強的機械性能以及耐化學腐蝕性能。同時，也可有效地遮擋潮氣，增加元器件的抗潮濕能力，從而改善了晶片的電學性能，降低了生產成本。參考圖6，可以在鈍化層302的暴露表面覆蓋聚合物層303,聚合物層303延伸至鈍化層302在金屬焊盤處形成的開口中，並使每個金屬焊盤的中心部分保持暴露狀態。
步驟32、在半導體器件的上方形成晶種層304，晶種層304與每個金屬焊盤電連接。
根據本發明的一些實施例，晶種層304是包括多個層的複合層。例如，該晶種層304可以包括處於下層的鈦層和處於上層的銅層，由此可以分別與每個金屬焊盤電連接。根據可選實施例，晶種層304也可以是單層，例如，其可以是銅層。可以理解，該晶種層304還可以使用其他合適的導電材料。
參考圖5C，可以在聚合物層303和兩個金屬焊盤的暴露表面上濺射金屬材料以形成晶種層304，該晶種層304可包括處於下層的鈦層和處於上層的銅層。應當理解，在後續的封裝步驟中需要將晶種層304的暴露表面蝕刻去除，以避免發生電路故障。
在步驟33、在晶種層304的上方形成第一光刻膠層305。在第一光刻膠層305中形成第一開口307以暴露晶種層304，其中，第一開口307位於至少兩種金屬焊盤中的至少一個第一金屬焊盤311的至少一部分的正上方。在第一開口307中形成第一高度的第一導電凸塊31。去除第一光刻膠層305。
在一些實施例中，參考圖5D，可以在晶種層304上方沉澱第一厚度的第一光刻膠層305，在第一光刻膠層305上方放置用於圖案化第一光刻膠層305的第一掩模層306，以形成第一開口307，具體而言，可以在提供的半導體器件和晶種層304的上方鋪滿光刻膠，以形成第一厚度的第一光刻膠層305，可以依據所需的設置在第一金屬焊盤311之上的金屬部件的高度尺寸確定該第一厚度。接下來將第一掩模層306放置在第一光刻膠層305上方。第一掩模層306可以是光刻掩模，其包括允許光通過的透明部分，以及用於阻擋光通過的不透明部分，光束投射在第一掩模層306上，從而曝光第一光刻膠層305位於透明部分正下方的部分，並且未曝光第一光刻膠層305位於不透明部分正下方的其它部分，從而形成該第一開口307。可以依據所需的第一金屬焊盤311的凸塊下金屬的底部尺寸確定第一開口307的開口面積。
在一些實施例中，參考圖5E，該第一導電凸塊31可以包括凸塊下金屬。可選地，該第一導電凸塊還可以包括其它用於提供晶片電氣互連的金屬介面。本實施例以凸塊下金屬為例進行描述，本申請對此不作具體限制。
參考圖5E，在晶種層304的上方且在第一開口307中形成第一高度的第一導電凸塊31,通常情況下，實施電鍍工藝在該第一開口307中填滿金屬材料以形成該第一導電凸塊31。換言之，該第一高度大致等同於第一光刻膠層305在第三開口處的第一厚度。第一導電凸塊31的底部通過晶種層304與第一金屬焊盤311電連接。根據本發明的一些實施例，第一導電凸塊31的形成步驟具體可以包括：在晶種層304之上且在該第一開口307中電鍍形成含銅（Cu）層312，含銅（Cu）層312例如可以為銅柱，在該含銅（Cu）層312的上方形成含鎳（Ni）層313，在該含鎳（Ni）層313的上方形成膏狀軟釺焊料314，具體可以為錫銀化合物層（例如SnAg1.8%）。
接下來，可以利用光刻膠剝離工藝中去除第一光刻膠層305，並且產生的結構如圖5F所示。
在步驟34、參考圖5G，去除第一光刻膠層305之後，在晶種層304之上形成第二光刻膠層308。在第二光刻膠層308中形成第二開口310以暴露晶種層304，其中，第二開口310位於至少兩種金屬焊盤中的至少一個第二金屬焊盤321的至少一部分的正上方。在第二開口310中形成第二高度的第二導電凸塊32，第二高度高於第一高度。
在一些實施例中，參考圖11，在去除第一光刻膠層305之後，在晶種層304的上方形成完全覆蓋第一導電凸塊31的第二光刻膠層308。在這種情況下，第二光刻膠層308比該第一導電凸塊31更高，因此其被光刻膠覆蓋並保護。
在一些實施例中，參考圖5G，與第一開口307的形成工藝相同或相似，去除第一光刻膠層305之後，在晶種層304上方沉澱第二厚度的第二光刻膠層308，在第二光刻膠層308上方放置用於圖案化第二光刻膠層308的第二掩模層309以形成第二開口310。具體而言，去除第一光刻膠層305之後，再次在晶種層304之上鋪滿光刻膠以形成第二厚度的第二光刻膠層308，可以依據所需的設置在第二金屬焊盤321之上的第二導電凸塊的高度尺寸確定該第二厚度。接下來將第二掩模層309放置在第二光刻膠層308上方。第二掩模層309同樣可以是光刻掩模，其包括允許光通過的透明部分，以及用於阻擋光通過的不透明部分，該透明部分可以設置在第二金屬焊盤321的至少部分的正上方，光束投射在第二掩模層309上，從而曝光第二光刻膠層308位於透明部分正下方的部分，也即大致位於第二金屬焊盤321正上方的晶種層304，並且未曝光第二光刻膠層308位於不透明部分正下方的其它部分，從而形成該第二開口310。可以依據所需的第二金屬焊盤321上的第二導電凸塊的底部尺寸自由確定第二開口310的開口面積。
在一些實施例中，參考圖5H，該第二導電凸塊32可以包括凸塊下金屬。可選地，該第二導電凸塊32還可以為其它用於提供晶片電氣互連的金屬介面。本實施例以凸塊下金屬為例進行描述，本申請對此不作具體限制。
參考圖5H，與第一導電凸塊31的形成工藝相同或相似，在晶種層304的上方且第二開口310中形成第二高度的第二導電凸塊32,通常情況下，實施電鍍工藝在該第二開口310中填滿金屬材料以形成該第二導電凸塊32。換言之，該第二高度大致等同於第二光刻膠層308在第三開口處的第二厚度。第二導電凸塊32的底部通過晶種層304與第二金屬焊盤321電連接。根據本發明的一些實施方式，第二導電凸塊32的形成步驟具體可以包括：在晶種層304之上且在該第二開口310中電鍍形成含銅（Cu）層322，含銅（Cu）層322例如可以為銅柱，在該含銅（Cu）層322的上方形成含鎳（Ni）層323，在該含鎳（Ni）層323的上方形成膏狀軟釺焊料324，具體可以為錫銀化合物層（例如SnAg1.8%），例如SnAg1.8%。
步驟35、去除第二光刻膠層308，形成晶片。去除第二光刻膠層308的步驟與第一光刻膠層305的去除工藝相同或相似，可以利用光刻膠剝離工藝中去除第二光刻膠層308，並且產生的結構如圖5I所示。
在一些實施例中，參考圖5H，接下來通過蝕刻去除晶種層304的先前由光刻膠覆蓋的曝光部分，同時保留晶種層304的由第一導電凸塊31和第二導電凸塊32覆蓋的未曝光部分。通過回流（reflow）焊工藝，重新熔化預先分配到金屬焊盤頂部的膏狀軟釺焊料314和324，通過融化材料的液體表面張力產生如圖5J所示的結構，最終形成焊料凸點。
根據以上步驟31-35，通過採用新的封裝結構設計和獨特的工藝流程，能夠在晶圓上形成多種尺寸不同、且凸點高度受控制的晶圓凸點，這對於使用同一封裝中的高密度互連佈線的ASIC裸晶片和小型晶片的集成而言非常有價值。
根據以上實施方式的各個方面，通過將若干個具有不同凸點高度的晶片集成附接至半導體襯底和互連器件的上方，能夠以簡單的封裝工藝以及低廉的封裝成本實現封裝件內部的高密度互聯佈線。
本發明還提供了一種半導體封裝件，其採用如上述實施例的方法製造成形。
參考圖2，半導體封裝件包括：半導體襯底10；互連器件20，附接在半導體襯底的上方表面；至少兩個晶片30，每個晶片30的一側表面形成有至少一個第一導電凸塊31和至少一個第二導電凸塊32，其中第二導電凸塊32的高度高於第一導電凸塊31；至少兩個晶片30附接於半導體襯底和互連器件20的上方表面，其中每個晶片30的第二導電凸塊32接合至半導體襯底的上方表面，且每個晶片30的第一導電凸塊31接合至互連器件20的上方表面。
在一些實施方式中，參考圖4A，互連器件20包括：矽晶圓層21，矽晶圓層21具有相對的第一側面和第二側面；重佈線結構22，附接在矽晶圓的第一側面；多個第一接合焊盤23，形成於重佈線結構22的表面；其中，互連器件20的厚度根據第一導電凸塊31和第二導電凸塊32之間的高度差確定。
在另外一些實施方式中，參考圖4B，矽晶圓的第一側面和第二側面之間形成有若干個垂直矽通孔24（Through Silicon Via，簡稱TSV）。可選地，具有垂直矽通孔24的互連器件可以利用混合鍵合（Hybrid Bonding）工藝將其第二側面附接至半導體襯底上方，從而實現更高的互連密度。
在一些實施方式中，晶片30包括：半導體器件，其至少包括：半導體晶圓和位於半導體晶圓上方的至少兩種金屬焊盤；晶種層，形成在半導體器件的上方表面且與每個金屬焊盤電連接；至少一個第一導電凸塊31，其具有第一高度，形成在晶種層的上方且位於至少兩種金屬焊盤中的至少一個第一金屬焊盤的至少一部分的正上方；至少一個第二導電凸塊32，其具有第二高度，形成在晶種層的上方且位於至少兩種金屬焊盤中的至少一個第二金屬焊盤的至少一部分的正上方。
在一些實施方式中，還包括：鈍化層，形成在半導體晶圓和至少兩種金屬焊盤的上方，其中，鈍化層中的圖案化開口將每個金屬焊盤的至少一部分暴露出來。晶種層至少覆蓋在每個金屬焊盤的暴露表面。
在一些實施方式中，還包括：形成在鈍化層的表面的聚合物層。
在一些實施方式中，第一導電凸塊和第二導電凸塊的粗細度不同。
在一些實施方式中，半導體襯底上方形成有多個第二接合焊盤，其中，每個晶片30的多個第一導電凸塊31對應接合至互連器件20的多個第一接合焊盤，且每個晶片30的多個第二導電凸塊32對應接合至半導體襯底的上方表面暴露的多個第二接合焊盤。
在一些實施方式中，第一導電凸塊31和第二導電凸塊32包括凸塊下金屬。
在一些實施方式中，參見圖3，封裝件還包括：罩體40，附接在半導體襯底的上方，罩體40將互連器件20和至少兩個晶片30容納在其中；柵格陣列，形成在半導體襯底的下方，用於將封裝件接合至PCB板60。
雖然已經參考若干具體實施方式描述了本發明的精神和原理，但是應該理解，本發明並不限於所公開的具體實施方式，對各方面的劃分也不意味著這些方面中的特徵不能組合以進行受益，這種劃分僅是為了表述的方便。本發明旨在涵蓋所附權利要求的精神和範圍內所包括的各種修改和等同佈置。
10:半導體襯底 20:互連器件 21:矽晶圓 22:重佈線結構 23:第一接合焊盤 24:垂直矽通孔 30:晶片 301:半導體晶圓 302:鈍化層 303:聚合物層 304:晶種層 305:第一光刻膠層 306:第一掩模層 307:第一開口 308:第二光刻膠層 309:第二掩模層 31:第一導電凸塊 310:第二開口 311:第一金屬焊盤 312:含銅層 313:含鎳層 314:膏狀軟釺焊料 32:第二導電凸塊 321:第二金屬焊盤 322:含銅層 323:含鎳層 324:膏狀軟釺焊料 40:罩體 50:柵格陣列 60:PCB板
通過閱讀下文的示例性實施例的詳細描述，本領域普通技術人員將明白本文所述的優點和益處以及其他優點和益處。附圖僅用於示出示例性實施例的目的，而並不認為是對本發明的限制。而且在整個附圖中，用相同的標號表示相同的部件。在附圖中：
[圖1]為根據本發明一實施例的形成半導體封裝件的方法的流程示意圖； [圖2]為根據本發明一實施例的半導體封裝件的結構示意圖； [圖3]為根據本發明另一實施例的半導體封裝件的結構示意圖； [圖4A]為根據本發明一實施例的互聯器件的結構示意圖； [圖4B]為根據本發明另一實施例的互聯器件的結構示意圖； [圖5A至圖5J]為根據本發明一實施例在形成晶片的過程中的中間階段的截面示意圖。
在附圖中，相同或對應的標號表示相同或對應的部分。
10:半導體襯底
20:互連器件
30:晶片
31:第一導電凸塊
32:第二導電凸塊

Claims (28)

  1. 一種形成半導體封裝件的方法，其特徵在於，包括： 提供半導體襯底，在所述半導體襯底上方附接互連器件； 形成至少兩個晶片，其中，每個所述晶片的一側表面形成有至少一個第一導電凸塊和至少一個第二導電凸塊，所述第二導電凸塊的高度高於第一導電凸塊； 將所述至少兩個晶片附接至所述半導體襯底和所述互連器件的上方表面，使每個所述晶片的所述第二導電凸塊接合至所述半導體襯底的上方表面，且每個所述晶片的所述第一導電凸塊接合至所述互連器件的上方表面。
  2. 如請求項1所述的方法，其特徵在於，在所述半導體襯底上方附接互連器件之前，還包括： 提供矽晶圓，所述矽晶圓具有相對的第一側面和第二側面； 在所述矽晶圓的所述第一側面形成重佈線結構； 在所述重佈線結構的表面形成多個第一接合焊盤； 根據所述第一導電凸塊和所述第二導電凸塊之間的高度差，對所述矽晶圓的所述第二側面進行減薄； 對減薄後的所述矽晶圓進行劃片，以形成所述互連器件。
  3. 如請求項2所述的方法，其特徵在於，在所述矽晶圓的所述第一側面和所述第二側面之間形成有垂直TSV通孔。
  4. 如請求項3所述的方法，其特徵在於，所述方法還包括： 利用混合鍵合工藝將所述互連器件附接至所述半導體襯底上方。
  5. 如請求項2所述的方法，其特徵在於，對所述矽晶圓的所述第二側面進行減薄，還包括： 使用支撐晶片臨時黏合在所述矽晶圓的所述第一側面，以在進行減薄時支撐所述矽晶圓； 其中，所述支撐晶片為矽晶片或玻璃。
  6. 如請求項1所述的方法，其特徵在於，所述方法還包括形成所述晶片的步驟，包括： 提供半導體器件，所述半導體器件至少包括：半導體晶圓和位於所述半導體晶圓上方的至少兩種金屬焊盤； 在所述半導體器件的上方形成晶種層，所述晶種層與每個所述金屬焊盤電連接； 在所述晶種層的上方形成第一光刻膠層；在所述第一光刻膠層中形成第一開口以暴露所述晶種層，其中，所述第一開口位於所述至少兩種金屬焊盤中的至少一個第一金屬焊盤的至少一部分的正上方；在所述第一開口中形成第一高度的第一導電凸塊；去除所述第一光刻膠層； 去除所述第一光刻膠層之後，在所述晶種層之上形成第二光刻膠層；在所述第二光刻膠層中形成第二開口以暴露所述晶種層，其中，所述第二開口位於所述至少兩種金屬焊盤中的至少一個第二金屬焊盤的至少一部分的正上方；在所述第二開口中形成第二高度的第二導電凸塊，所述第二高度高於所述第一高度； 去除所述第二光刻膠層，形成所述晶片。
  7. 如請求項6所述的方法，其特徵在於，所述方法還包括： 在所述半導體晶圓和所述至少兩種金屬焊盤的上方形成圖案化的鈍化層，所述鈍化層將每個所述金屬焊盤的至少一部分暴露出來； 所述晶種層至少覆蓋在每個所述金屬焊盤的暴露表面。
  8. 如請求項7所述的方法，其特徵在於，形成圖案化的鈍化層之後，所述方法還包括：在所述鈍化層的表面形成聚合物層。
  9. 如請求項8所述的方法，其特徵在於，所述方法還包括： 在所述聚合物層和所述至少兩種金屬焊盤的暴露表面上濺射金屬材料以形成所述晶種層；以及， 在去除所述第二光刻膠層之後，蝕刻去除所述晶種層的曝光部分。
  10. 如請求項6所述的方法，其特徵在於，所述方法還包括： 在所述晶種層上方沉澱第一厚度的所述第一光刻膠層，在所述第一光刻膠層上方放置用於圖案化所述第一光刻膠層的第一掩模層以形成所述第一開口；以及， 去除所述第一光刻膠層之後，在所述晶種層上方沉澱第二厚度的所述第二光刻膠層，在所述第二光刻膠層上方放置用於圖案化所述第二光刻膠層的第二掩模層以形成所述第二開口。
  11. 如請求項6所述的方法，其特徵在於，還包括： 在所述去除所述第一光刻膠層之後，在所述晶種層的上方形成完全覆蓋所述第一導電凸塊的所述第二光刻膠層。
  12. 如請求項1所述的方法，其特徵在於，所述第一導電凸塊和所述第二導電凸塊的粗細度不同。
  13. 如請求項1所述的方法，其特徵在於，所述互連器件的上方表面形成有多個第一接合焊盤，所述半導體襯底上方形成有多個第二接合焊盤，將所述至少兩個晶片附接至所述半導體襯底和所述互連器件的上方表面，還包括： 將所述至少兩個晶片倒裝安裝在半導體襯底和所述互連器件的上方，使得所述每個所述晶片的多個所述第一導電凸塊對應接合至所述互連器件的多個所述第一接合焊盤，同時使每個所述晶片的多個所述第二導電凸塊接合至所述半導體襯底的上方表面暴露的多個所述第二接合焊盤。
  14. 如請求項1所述的方法，其特徵在於，所述第一導電凸塊和所述第二導電凸塊包括凸塊下金屬。
  15. 如請求項1所述的方法，其特徵在於，將所述至少兩個晶片附接至所述半導體襯底和所述互連器件的上方表面之後，所述方法還包括： 在所述半導體襯底的上方附接一罩體，所述罩體將所述互連器件和所述至少兩個晶片容納在其中； 在所述半導體襯底的下方形成柵格陣列，以用於將所述封裝件接合至PCB板。
  16. 如請求項1所述的方法，其特徵在於，所述互連器件的材料為矽晶片或玻璃。
  17. 一種半導體封裝件，其特徵在於，包括： 半導體襯底； 互連器件，附接在所述半導體襯底的上方表面； 至少兩個晶片，每個所述晶片的一側表面形成有至少一個第一導電凸塊和至少一個第二導電凸塊，其中所述第二導電凸塊的高度高於第一導電凸塊；所述至少兩個晶片附接於所述半導體襯底和所述互連器件的上方表面，其中每個所述晶片的所述第二導電凸塊接合至所述半導體襯底的上方表面，且每個所述晶片的所述第一導電凸塊接合至所述互連器件的上方表面。
  18. 如請求項17所述的封裝件，其特徵在於，所述互連器件包括： 矽晶圓層，所述矽晶圓層具有相對的第一側面和第二側面； 重佈線結構，附接在所述矽晶圓的所述第一側面； 多個第一接合焊盤，形成於所述重佈線結構的表面； 其中，所述互連器件的厚度根據所述第一導電凸塊和所述第二導電凸塊之間的高度差確定。
  19. 如請求項18所述的封裝件，其特徵在於，所述矽晶圓的所述第一側面和所述第二側面之間形成有垂直TSV通孔。
  20. 如請求項19所述的封裝件，其特徵在於，所述互連器件利用混合鍵合工藝附接至所述半導體襯底上方。
  21. 如請求項17所述的封裝件，其特徵在於，所述晶片包括： 半導體器件，其至少包括：半導體晶圓和位於所述半導體晶圓上方的至少兩種金屬焊盤； 晶種層，形成在所述半導體器件的上方表面且與每個所述金屬焊盤電連接； 至少一個第一導電凸塊，其具有第一高度，形成在所述晶種層的上方且位於所述至少兩種金屬焊盤中的至少一個第一金屬焊盤的至少一部分的正上方； 至少一個第二導電凸塊，其具有第二高度，形成在所述晶種層的上方且位於所述至少兩種金屬焊盤中的至少一個第二金屬焊盤的至少一部分的正上方。
  22. 如請求項21所述的封裝件，其特徵在於，還包括： 鈍化層，形成在所述半導體晶圓和所述至少兩種金屬焊盤的上方，其中，所述鈍化層中的圖案化開口將每個所述金屬焊盤的至少一部分暴露出來；所述晶種層至少覆蓋在每個所述金屬焊盤的暴露表面。
  23. 如請求項22所述的封裝件，其特徵在於，還包括：形成在所述鈍化層的表面的聚合物層。
  24. 如請求項17所述的封裝件，其特徵在於，所述第一導電凸塊和所述第二導電凸塊的粗細度不同。
  25. 如請求項17所述的封裝件，其特徵在於，所述半導體襯底上方形成有多個第二接合焊盤，其中，每個所述晶片的多個所述第一導電凸塊對應接合至所述互連器件的多個所述第一接合焊盤，且每個所述晶片的多個所述第二導電凸塊對應接合至所述半導體襯底的上方表面暴露的多個所述第二接合焊盤。
  26. 如請求項17所述的封裝件，其特徵在於，所述第一導電凸塊和所述第二導電凸塊包括凸塊下金屬。
  27. 如請求項17所述的封裝件，其特徵在於，所述封裝件還包括： 罩體，附接在所述半導體襯底的上方，所述罩體將所述互連器件和所述至少兩個晶片容納在其中； 柵格陣列，形成在所述半導體襯底的下方，用於將所述封裝件接合至PCB板。
  28. 如請求項17所述的封裝件，其特徵在於，所述互連器件的材料為矽晶片或玻璃。
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