CN109727964A - 多芯片晶片级封装及其形成方法 - Google Patents

多芯片晶片级封装及其形成方法 Download PDF

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Publication number
CN109727964A
CN109727964A CN201810022467.4A CN201810022467A CN109727964A CN 109727964 A CN109727964 A CN 109727964A CN 201810022467 A CN201810022467 A CN 201810022467A CN 109727964 A CN109727964 A CN 109727964A
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China
Prior art keywords
semiconductor chip
chip
layer structure
semiconductor
wafer
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CN201810022467.4A
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Inventor
陈硕懋
许峯诚
黄翰祥
刘献文
郑心圃
李孝文
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN109727964A publication Critical patent/CN109727964A/zh
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Abstract

本发明实施例提供多种多芯片晶片级封装及其形成方法。一种多芯片晶片级封装包括第一层级及第二层级。所述第一层级包括第一重布线层结构及位于所述第一重布线层结构之上的至少一个芯片。所述第二层级包括第二重布线层结构以及位于所述第二重布线层结构之上的至少两个其他芯片。所述第一层级接合到所述第二层级，使得所述至少一个芯片在实体上接触所述第二重布线层结构。所述至少两个其他芯片的连接件的总数目大于所述至少一个芯片的连接件的总数目。

Description

多芯片晶片级封装及其形成方法
技术领域
本发明实施例是涉及一种多芯片晶片级封装及其形成方法。
背景技术
近年来，由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度持续提高，半导体行业已经历快速成长。在很大程度上，集成密度的这种提高来自于最小特征大小(minimum feature size)的连续减小，这使得更多组件能够集成到给定区域中。
与先前的封装相比，这些较小的电子组件也需要占据较小面积的较小的封装。半导体封装类型的实例包括方形扁平封装(quad flat package，QFP)、针格阵列(pin gridarray，PGA)封装、球格阵列(ball grid array，BGA)封装、覆晶(flip chip，FC)、三维集成电路(three-dimensional integrated circuit，3DIC)、晶片级封装(wafer levelpackage，WLP)、及叠层封装(package on package，PoP)器件等。已出现一种多芯片晶片级封装来进一步减小封装的实体大小。然而，存在与这种多芯片晶片级封装相关的许多挑战。
发明内容
根据本发明的一些实施例，一种多芯片晶片级封装包括第一层级(tier)及第二层级。所述第一层级包括第一重布线层结构及位于所述第一重布线层结构之上的至少一个芯片。所述第二层级包括第二重布线层结构以及位于所述第二重布线层结构之上的至少两个其他芯片。所述第一层级接合到所述第二层级，使得所述至少一个芯片在实体上接触所述第二重布线层结构。所述至少两个其他芯片的连接件的总数目大于所述至少一个芯片的连接件的总数目。
附图说明
图1A至图1G是根据一些实施例的形成多芯片晶片级封装的方法的剖视图。
图2至图6是根据一些实施例的多芯片晶片级封装的剖视图。
图7A至图7G是根据替代实施例的形成多芯片晶片级封装的方法的剖视图。
图8至图10是根据替代实施例的多芯片晶片级封装的剖视图。
图11至图14是根据又一些替代实施例的多芯片晶片级封装的剖视图。
图15至图16是根据一些实施例的半导体芯片的剖视图。
图17至图20是根据替代实施例的半导体芯片的剖视图。
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下出于以简化方式传达本公开内容的目的阐述了元件及排列的具体实例。当然，这些仅为实例而不旨在进行限制。举例来说，以下说明中将第二特征形成于第一特征“之上”或第一特征“上”可包括其中第二特征及第一特征形成为直接接触的实施例，且也可包括其中第二特征与第一特征之间可形成有附加特征、进而使得所述第二特征与所述第一特征可能不直接接触的实施例。另外，可使用相同的参考编号及/或字母来指代本公开内容的各个实例中的相同或相似的部件。重复使用参考编号是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，本文中可能使用例如“位于...之下(beneath)”、“位于...下面(below)”、“下部的(lower)”、“位于…上(on)”、“位于…之上(over)”、“上覆的(overlying)”、“位于...上方(above)”、“上部的(upper)”等空间相对性用语以便于阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括器件在使用或操作中的不同取向。设备可具有其他取向(旋转90度或其他取向)，且本文中所用的空间相对性用语可同样相应地进行解释。
也可包括其他特征及工艺。举例来说，可包括测试结构，以帮助对三维(threedimensional，3D)封装或三维集成电路(three dimensional integrated circuit，3DIC)器件进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试接垫(test pad)，以便能够对三维封装或三维集成电路进行测试、对探针及/或探针卡(probecard)进行使用等。可对中间结构以及最终结构执行验证测试。另外，可将本文中所公开的结构及方法与包括对已知良好管芯进行中间验证的测试方法结合使用，以提高良率并降低成本。
图1A至图1G是根据一些实施例的形成多芯片晶片级封装的方法的剖视图。
参照图1A，提供上面形成有第一重布线层结构RDL1的载板C。在一些实施例中，在载板C与第一重布线层结构RDL1之间形成剥离层DB。在一些实施例中，载板C是非半导体材料，例如玻璃载板、陶瓷载板、等等。在一些实施例中，剥离层DB包含紫外(Ultra-Violet，UV)胶、光热转换(Light-to-Heat Conversion，LTHC)胶、等等，但是也可使用其他类型的粘合剂。剥离层DB可在光的热量作用下分解，从而将载板C从形成在载板C上的结构释放。
在一些实施例中，在说明书通篇中将第一重布线层结构RDL1称为“背侧重布线层结构”。在一些实施例中，第一重布线层结构RDL1包括通过多个聚合物层102进行嵌置的多个重布线层104。在一些实施例中，重布线层104中的每一者包含铜、镍、钛、其组合、或类似材料，并通过光刻、镀覆、及光刻胶剥除工艺(photoresist stripping process)形成。在一些实施例中，聚合物层102中的每一者包含聚合物材料(例如，聚苯并恶唑(polybenzoxazole，PBO)、聚酰亚胺(polyimide，PI)、苯并环丁烯(benzocyclobutene，BCB)、其组合、或类似材料)，并通过例如旋转涂布、层叠、沉积等合适的制作技术形成。
参照图1B，在第一重布线层结构RDL1上形成多个集成扇出型穿孔TIV。在一些实施例中，集成扇出型穿孔TIV延伸到最上的聚合物层102中且电连接到最上的重布线层104。在一些实施例中，集成扇出型穿孔TIV包含铜、镍、钛、其组合、或类似材料，并通过光刻、镀覆、及光刻胶剥除工艺形成。
参照图1C，将第一半导体芯片100及第二半导体芯片200放置在第一重布线层结构RDL1的第一侧上并接合到第一重布线层结构RDL1的第一侧。
在一些实施例中，第一半导体芯片100包括衬底100a、一个或多个接垫100b、保护层100c、及一个或多个连接件100d。衬底100a包括(例如但不限于)经掺杂或未经掺杂的块状硅(bulk silicon)、或绝缘体上半导体(semiconductor-on-insulator，SOI)衬底的有源层。接垫100b形成在衬底100a之上，且保护层100c形成在接垫100b之上。在一些实施例中，接垫100b是铝接垫，且保护层100c包含聚合物材料，例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、其组合、或类似材料。连接件100d穿过保护层100c形成且电连接到下伏的接垫100b或内连结构。在一些实施例中，连接件100d形成为第一半导体芯片100的顶部部分。连接件100d从第一半导体芯片100的其余部分或下部部分突出。在本说明通篇中，将第一半导体芯片100的具有连接件100d的侧称为前侧。连接件100d可包含Cu、W、Ni、Sn、Ti、Au、其合金、或其组合，并利用落球工艺(ball drop process)或电镀工艺形成。在一些实施例中，接垫100b构成第一半导体芯片100的连接件的一部分。在一些实施例中，接垫100b及/或连接件100d构成第一半导体芯片100的前侧连接件。
在一些实施例中，第二半导体芯片200包括衬底200a、一个或多个接垫200b、保护层200c、及一个或多个连接件200d。第二半导体芯片200的元件的材料及排列与第一半导体芯片100的元件的材料及排列相似，因此在本文中将不再重复这些细节。
在一些实施例中，第一半导体芯片100及第二半导体芯片200中的每一者包括集成无源器件(integrated passive device)，例如电容器、电感器、或电阻器。在一些实施例中，在说明书通篇中将第一半导体芯片100及第二半导体芯片200称为“第一集成无源器件芯片及第二集成无源器件芯片”。在一些实施例中，第一半导体芯片100及第二半导体芯片200中的每一者配置成以约1GHz或大于1GHz的高频率运行的电容器。在一些实施例中，在说明书通篇中将第一半导体芯片100及第二半导体芯片200称为“高频电容器”。在一些实施例中，基于工艺要求，第一半导体芯片100与第二半导体芯片200是具有不同的电容值、共振频率(resonance frequency)、及/或不同大小的电容器。具体来说，如图15所示，第一半导体芯片100’还具有位于衬底100a与接垫100b之间的深沟槽电容器区CA1，且第二半导体芯片200’还具有位于衬底200a与接垫200b之间的深沟槽电容器区CA2。然而，本公开内容并非仅限于此。在替代实施例中，根据需要将第一半导体芯片100与第二半导体芯片200设计成具有相同的大小、功能、及/或运行范围。
参照图1D，利用第一包封层E1来包封第一半导体芯片100及第二半导体芯片200。在一些实施例中，在载板C之上形成第一包封层E1以包封或环绕集成扇出型穿孔TIV的侧壁以及第一半导体芯片100的侧壁及第二半导体芯片200的侧壁。在一些实施例中，第一包封层E1包含模塑化合物、模塑底部填充胶、树脂等(例如，环氧树脂(epoxy))。在一些实施例中，第一包封层E1包含聚合物材料(例如，聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、其组合、或类似材料)，并通过进行模塑工艺且接着进行研磨工艺直到暴露出集成扇出型穿孔TIV的表面以及第一半导体芯片100的连接件100d的表面及第二半导体芯片200的连接件200d的表面为止来形成。
之后，在第一包封层E1之上形成第二重布线层结构RDL2。在一些实施例中，在说明书通篇中将第二重布线层结构RDL2称为“前侧重布线层结构”。在一些实施例中，第二重布线层结构RDL2包括通过多个聚合物层106进行嵌置的多个重布线层108。在一些实施例中，重布线层108中的每一者包含铜、镍、钛、其组合、或类似材料，并通过光刻、镀覆、及光刻胶剥除工艺形成。在一些实施例中，聚合物层106中的每一者包含聚合物材料(例如，聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、其组合、或类似材料)，并通过例如旋转涂布、层叠、沉积等合适的制作技术形成。在一些实施例中，第二重布线层结构RDL2还包括多个连接接垫110，其配置成与其他半导体芯片连接。
在一些实施例中，第二重布线层结构RDL2的临界尺寸(critical dimension)小于第一重布线层结构RDL1的临界尺寸。在替代实施例中，第二重布线层结构RDL2的临界尺寸可根据需要而实质上相同于或大于第一重布线层结构RDL1的临界尺寸。
参照图1E及图1F，将第三半导体芯片300及第四半导体芯片400放置在第二重布线层结构RDL2上并接合到第二重布线层结构RDL2。
如图1E所示，提供第三半导体芯片300及第四半导体芯片400。在一些实施例中，第三半导体芯片300包括衬底300a、一个或多个接垫300b、保护层300c、一个或多个连接件300d、及一个或多个凸块300e。衬底300a包括(例如但不限于)经掺杂或未经掺杂的块状硅、或绝缘体上半导体(SOI)衬底的有源层。接垫300b形成在衬底300a之上，且保护层300c形成在接垫300b之上。在一些实施例中，接垫300b是铝接垫，且保护层300c包含聚合物材料，例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、其组合、或类似材料。连接件300d穿过保护层300c形成且电连接到下伏的接垫300b或内连结构。在一些实施例中，连接件300d形成为第三半导体芯片300的顶部部分。连接件300d从第三半导体芯片300的其余部分或下部部分突出。在本说明通篇中，将第三半导体芯片300的具有连接件300d的侧称为前侧。连接件300d可包括含铜柱，并利用电镀工艺形成。凸块300e形成在连接件300d上。在一些实施例中，凸块300e可包括焊料凸块，并利用落球工艺或电镀工艺形成。在一些实施例中，接垫300b及/或凸块300e构成第三半导体芯片300的连接件的一部分。在一些实施例中，接垫300b、连接件300d及/或凸块300e构成第三半导体芯片300的前侧连接件。
在一些实施例中，第四半导体芯片400包括衬底400a、一个或多个接垫400b、保护层400c、一个或多个连接件400d、及一个或多个凸块400e。第四半导体芯片400的元件的材料及排列与第三半导体芯片300的元件的材料及排列相似，因此在本文中将不再重复这些细节。
在一些实施例中，第三半导体芯片300及第四半导体芯片400中的每一者包括集成有源器件(integrated active device)，例如逻辑器件。所述逻辑器件包括应用处理器(application processor，AP)、系统芯片(system on chip，SoC)等。在一些实施例中，系统芯片(SoC)包括调制解调器模块(modem module)。可基于工艺要求使用其他类型的有源器件，例如存储器器件、金属氧化物半导体场效晶体管(metal oxide semiconductor fieldeffect transistor，MOSFET)器件、CMOS器件、及/或双极结型晶体管(bipolar junctiontransistor，BJT)器件。在一些实施例中，在说明书通篇中将第三半导体芯片300及第四半导体芯片400称为“第一集成有源器件芯片及第二集成有源器件芯片”。在一些实施例中，第三半导体芯片300及第四半导体芯片400是具有不同功能及/或不同大小的有源器件。在替代实施例中，根据需要将第三半导体芯片300与第四半导体芯片400设计成具有相同的大小及/或功能。在一些实施例中，第三半导体芯片300及第四半导体芯片400中的至少一者电连接到六个或更多个集成无源器件芯片以形成多芯片模块。与其他方式相比，这种排列有助于增大产品的带宽并减小封装大小。
如图1F所示，第三半导体芯片300及第四半导体芯片400接合到第二重布线层结构RDL2且位于第一半导体芯片100及第二半导体芯片200上方。在一些实施例中，第三半导体芯片300的凸块300e及第四半导体芯片400的凸块400e接合到第二重布线层结构RDL2的连接接垫110。
在一些实施例中，第三半导体芯片300的连接件300d与第四半导体芯片400的连接件400d的总数目大于(例如，至少两倍、至少五倍、或至少八倍于)第一半导体芯片100的连接件100d与第二半导体芯片200的连接件200d的总数目。
之后，形成底部填充胶层UF来填充第二重布线层结构RDL2与第三半导体芯片300及第四半导体芯片400中的每一者之间的空间。在一些实施例中，形成底部填充胶层UF来环绕连接件300d及400d以及凸块300e及400e。在一些实施例中，底部填充胶层UF包含模塑化合物(例如，环氧树脂)，并利用点胶(dispensing)、注入(injecting)、及/或喷洒(spraying)技术形成。
然后，利用第二包封层E2包封第三半导体芯片300及第四半导体芯片400。在一些实施例中，在第二重布线层结构RDL2之上形成第二包封层E2以包封或环绕第三半导体芯片300的侧壁和顶部及第四半导体芯片400的侧壁和顶部。在一些实施例中，第二包封层E2包含模塑化合物、模塑底部填充胶、树脂(例如，环氧树脂)等。在一些实施例中，第二包封层E2包含聚合物材料(例如，聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、其组合、或类似材料)，且通过模塑工艺形成。在一些实施例中，第一包封层E1与第二包封层E2包含相同的材料。在替代实施例中，第二包封层E2包含与第一包封层E1的材料不同的材料。
参照图1G，将载板C从第一重布线层结构RDL1的第二侧剥离。在一些实施例中，使剥离层DB在光的热量作用下分解，且接着将载板C从形成在载板C上的结构释放。
之后，对最下的聚合物层102进行图案化以形成开口来暴露出第一重布线层结构RDL1的连接接垫或最下的重布线层104。在一些实施例中，开口是通过激光钻孔工艺(laserdrilling process)、干蚀刻工艺(dry etching process)、或合适的图案化工艺形成。之后，将凸块112放置在第一重布线层结构RDL1的第二侧之上并接合到第一重布线层结构RDL1的连接接垫。在一些实施例中，凸块112可为焊料凸块，及/或可包括金属柱(例如，铜柱)、形成在金属柱上的焊料顶盖、及/或类似元件。凸块112可通过例如蒸镀、电镀、落球、或丝网印刷(screen printing)等合适的工艺形成。由此完成多芯片晶片级封装1。在一些实施例中，多芯片晶片级封装1由彼此实体接触的第一层级T1与第二层级T2构成。在一些实施例中，第一层级T1包括第一重布线层结构RDL1以及位于第一重布线层结构RDL1上的第一半导体芯片100及第二半导体芯片200，且第二层级T2包括第二重布线层结构RDL2以及位于第二重布线层结构RDL2上的第三半导体芯片300及第四半导体芯片400。
在一些实施例中，第一半导体芯片100及第二半导体芯片200配置成使第三半导体芯片300及第四半导体芯片400的电平电压(level voltage)保持相对稳定的解耦合电容器(decoupling capacitors)。具体来说，在电路运行期间，电源线会供应强度相对高的暂态电流(transient current)，所述暂态电流可引起电源线上的电压波动。在本公开内容中并未观察到这种问题。在一些实施例中，解耦合电容器(例如，第一半导体芯片100及第二半导体芯片200)靠近有源器件(例如，第三半导体芯片300及第四半导体芯片400)设置(例如，相对应地位于所述有源元件下方)，并充当向有源器件额外地供应电流的电荷贮存器(chargereservoir)以防止电源电压瞬间下降。在一些实施例中，由于设置有解耦合电容器(例如，第一半导体芯片100及第二半导体芯片200)，因此TIV数目可减少，且因此TIV节距(pitch)可增大。第一重布线层结构RDL1的图案节距可因此增大。因此，工艺裕度(process window)可变宽且可节省生产成本。
可对多芯片晶片级封装作出可能的修改及变更。提供这些修改及变更是出于说明目的，而不应被视为对本公开内容进行限制。图2至图6是根据一些实施例的多芯片晶片级封装的剖视图。
图2所示多芯片晶片级封装2与图1G所示多芯片晶片级封装1相似，其之间的差异在于，多芯片晶片级封装2还包括第五半导体芯片500及第六半导体芯片600。在一些实施例中，第五半导体芯片500及第六半导体芯片600中的每一者包括集成无源器件，例如电容器、电感器、或电阻器。在一些实施例中，在说明书通篇中将第五半导体芯片500及第六半导体芯片600称为“第三集成无源器件芯片及第四集成无源器件芯片”。在一些实施例中，第五半导体芯片500及第六半导体芯片600中的每一者配置成以约1KHz或小于1KHz的低频率运行的电容器。在一些实施例中，在说明书通篇中将第五半导体芯片500及第六半导体芯片600称为“低频电容器”。在一些实施例中，基于工艺要求，第五半导体芯片500与第六半导体芯片600是具有不同的电容值、共振频率、及/或不同大小的电容器。在替代实施例中，根据需要将第五半导体芯片500与第六半导体芯片600设计成具有相同的大小、功能、及/或运行范围。在一些实施例中，当将第一半导体芯片100及第二半导体芯片200放置在第一重布线层结构RDL1上并接合到第一重布线层结构RDL1时，将第五半导体芯片500及第六半导体芯片600通过其凸块501及凸块601放置在第一重布线层结构RDL1上并接合到第一重布线层结构RDL1。
图3所示多芯片晶片级封装3与图2所示多芯片晶片级封装2相似，其之间的差异在于，图2所示第五半导体芯片500及第六半导体芯片600接合到第一重布线层结构RDL1，而图3所示第五半导体芯片500及第六半导体芯片600接合到第二重布线层结构RDL2。在一些实施例中，当将第三半导体芯片300及第四半导体芯片400放置在第二重布线层结构RDL2上并接合到第二重布线层结构RDL2时，将第五半导体芯片500及第六半导体芯片600通过其凸块501及凸块601放置在第二重布线层结构RDL2上并接合到第二重布线层结构RDL2。
图4所示多芯片晶片级封装4与图1G所示多芯片晶片级封装1相似，其之间的差异在于，图1G所示第一半导体芯片100及第二半导体芯片200中的每一者是在单侧上具有连接件100d及200d的单侧式半导体芯片，连接件100d及200d接合到第二重布线层结构RDL2，而图4所示第一半导体芯片101及第二半导体芯片201中的每一者是在相对两侧上具有连接件的双侧式半导体芯片，所述连接件分别接合到第一重布线层结构RDL1及第二重布线层结构RDL2。
在一些实施例中，第一半导体芯片101与第一半导体芯片100相似，其之间的差异在于，第一半导体芯片101还包括位于第一半导体芯片101的背侧部分中的一个或多个接垫100e以及位于前侧接垫100b与背侧接垫100e之间且电连接到前侧接垫100b及背侧接垫100e的一个或多个硅穿孔TSV1。在一些实施例中，背侧接垫100e通过聚合物材料(例如，聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、其组合、或类似材料)进行嵌置。在一些实施例中，在第一半导体芯片101的背侧处形成有凸块且所述凸块接合到接垫100e。在替代实施例中，背侧接垫100e连接到第一重布线层结构RDL1，而在其之间不存在凸块。在一些实施例中，第一半导体芯片的底表面不与第一重布线层结构RDL1的顶表面共面。举例来说，凸块被插置到第一重布线层结构RDL1的顶部聚合物层中。在替代实施例中，第一半导体芯片的底表面与第一重布线层结构RDL1的顶表面共面。在一些实施例中，接垫100b及/或连接件100d构成第一半导体芯片100的前侧连接件，且接垫100e及/或可选凸块构成第一半导体芯片100的背侧连接件。
在一些实施例中，第二半导体芯片201与第二半导体芯片200相似，其之间的差异在于，第二半导体芯片201还包括位于第二半导体芯片201的背侧部分中的一个或多个接垫200e以及位于前侧接垫200b与背侧接垫200e之间且电连接到前侧接垫200b及背侧接垫200e的一个或多个硅穿孔TSV2。第二半导体芯片201的元件的材料及排列与第一半导体芯片101的元件的材料及排列相似，因此在本文中将不再重复这些细节。
在一些实施例中，第一半导体芯片101及第二半导体芯片201中的每一者包括集成无源器件，例如电容器、电感器、或电阻器。在一些实施例中，第一半导体芯片101及第二半导体芯片201中的每一者配置成以约1GHz或大于1GHz的高频率运行的电容器。在一些实施例中，在说明书通篇中将第一半导体芯片101及第二半导体芯片201称为“高频电容器”。在一些实施例中，基于工艺要求，第一半导体芯片101与第二半导体芯片201是具有不同的电容值、共振频率、及/或不同大小的电容器。具体来说，如图16所示，第一半导体芯片101’还具有位于衬底100a与接垫100b之间的深沟槽电容器区CA1，且深沟槽电容器区CA1与硅穿孔TSV1以排除区域(keep out zone，KOZ)间隔开来。相似地，第二半导体芯片201’还具有位于衬底200a与接垫200b之间的深沟槽电容器区CA2，且深沟槽电容器区CA2与硅穿孔TSV2以排除区域(KOZ)间隔开来。
图5所示多芯片晶片级封装5与图2所示多芯片晶片级封装2相似，其之间的差异在于，图2所示第一半导体芯片100及第二半导体芯片200中的每一者是单侧式半导体芯片，而图5所示第一半导体芯片101及第二半导体芯片201中的每一者是双侧式半导体芯片。
图6所示多芯片晶片级封装6与图3所示多芯片晶片级封装3相似，其之间的差异在于，图3所示第一半导体芯片100及第二半导体芯片200中的每一者是单侧式半导体芯片，而图6所示第一半导体芯片101及第二半导体芯片201中的每一者是双侧式半导体芯片。
在以上实施例中，多芯片晶片级封装中的每一者是使用单个载板形成的，其只是出于说明目的，而不应被视为对本公开内容进行限制。在替代实施例中，多芯片晶片级封装可使用两个载板形成。
图7A至图7G是根据替代实施例的形成多芯片晶片级封装的方法的剖视图。
参照图7A，提供上面形成有第一重布线层结构RDL1的第一载板C1。在一些实施例中，在第一载板C1与第一重布线层结构RDL1之间形成第一剥离层DB1。在一些实施例中，第一重布线层结构RDL1包括通过多个聚合物层102进行嵌置的多个重布线层104。在一些实施例中，第一重布线层结构RDL1还包括多个连接接垫103，其配置成与其他半导体芯片进行连接。在一些实施例中，在第一重布线层结构RDL1的连接接垫103上形成多个凸块105。凸块105可包括焊料凸块，并利用落球工艺或电镀工艺形成。
之后，提供芯片模块CM。在一些实施例中，芯片模块CM可通过包括图7B至图7D所示步骤的方法来形成。如图7B所示，提供上面形成有第二剥离层DB2的第二载板C2。之后，在第二剥离层DB2上形成多个集成扇出型穿孔TIV。然后，将第一半导体芯片101及第二半导体芯片201放置在第二载板C2上。在一些实施例中，在第二载板C2与第一半导体芯片101及第二半导体芯片201中的每一者的背侧之间形成第二剥离层DB2。在一些实施例中，在第二剥离层DB2上交替地排列第一半导体芯片101与第二半导体芯片201。接下来，利用第一包封层E1来包封第一半导体芯片101及第二半导体芯片201。接着在第一包封层E1上形成第二重布线层结构RDL2。
在一些实施例中，第二重布线层结构RDL2的临界尺寸可小于第一重布线层结构RDL1的临界尺寸。在替代实施例中，第二重布线层结构RDL2的临界尺寸可根据需要而实质上相同于或大于第一重布线层结构RDL1的临界尺寸。
如图7C所示，将第三半导体芯片300及第四半导体芯片400放置在第二重布线层结构RDL2上并接合到第二重布线层结构RDL2。在一些实施例中，在第二重布线层结构RDL2上交替地排列多个第三半导体芯片300与多个第四半导体芯片400。在一些实施例中，第三半导体芯片300分别对应于第一半导体芯片101，且第四半导体芯片400分别对应于第二半导体芯片201。
之后，形成底部填充胶层UF1来填充第二重布线层结构RDL2与第三半导体芯片300及第四半导体芯片400中的每一者之间的空间。
如图7D所示，将第二载板C2从第一半导体芯片101的背侧及第二半导体芯片201的背侧剥离。在一些实施例中，可在第一半导体芯片101的背侧及第二半导体芯片201的背侧处形成凸块且所述凸块接合到背侧接垫。接着执行单体化工艺来使芯片模块CM彼此分离。在至少一个实施例中，第三半导体芯片300的边缘及第四半导体芯片400的边缘与第二重布线层结构RDL2的边缘实质上对齐。
在一些实施例中，芯片模块CM中的每一者包括：第二重布线层结构RDL2；第一半导体芯片101及第二半导体芯片201，位于第二重布线层结构RDL2的一侧上；第一包封层E1，包封第一半导体芯片101及第二半导体芯片201；以及第三半导体芯片300及第四半导体芯片400，位于第二重布线层结构RDL2的相对侧上。在一些实施例中，各芯片模块CM中的每一者包括包封第一半导体芯片101的侧壁及第二半导体芯片201的侧壁的第一包封层E1。在一些实施例中，各芯片模块CM中的每一者包括集成扇出型穿孔TIV及底部填充胶层UF1。在一些实施例中，集成扇出型穿孔TIV穿透第一包封层E1且位于第一半导体芯片101及第二半导体芯片201的侧边及/或位于第一半导体芯片101与第二半导体芯片201之间，且底部填充胶层UF1形成为填充第二重布线层结构RDL2与第三半导体芯片300及第四半导体芯片400中的每一者之间的空间。
参照图7E及图7F，将一个芯片模块CM放置在第一重布线层结构RDL1的第一侧上并接合到第一重布线层结构RDL1的第一侧。在一些实施例中，将芯片模块CM接合到第一重布线层结构RDL1，使得第一半导体芯片101的背侧及第二半导体芯片201的背侧在实体上接触第一重布线层结构RDL1。在一些实施例中，第一半导体芯片101的背侧接垫及第二半导体芯片201的背侧接垫以及芯片模块CM的集成扇出型穿孔TIV通过对应的凸块105电连接到第一重布线层结构RDL1。
在一些实施例中，当将芯片模块CM放置在第一重布线层结构RDL1上并接合到第一重布线层结构RDL1时，第五半导体芯片500及第六半导体芯片600通过其凸块501及凸块601放置在第一重布线层结构RDL1上并接合到第一重布线层结构RDL1。
之后，形成底部填充胶层UF2来填充第一重布线层结构RDL1与芯片模块CM、第五半导体芯片500及第六半导体芯片600中的每一者之间的空间。
参照图7G，利用第二包封层E2来包封芯片模块CM以及第五半导体芯片500及第六半导体芯片600。在一些实施例中，在第一重布线层结构RDL1之上形成第二包封层E2以包封或环绕芯片模块CM的侧壁和顶部以及第五半导体芯片500的侧壁和顶部及第六半导体芯片600的侧壁和顶部。第一包封层E1与第二包封层E2可包含相同或不同的材料。
之后，将凸块112放置在第一重布线层结构RDL1的与第一侧相对的第二侧上并接合到第一重布线层结构RDL1的连接接垫。由此完成多芯片晶片级封装7。在一些实施例中，多芯片晶片级封装7由彼此实体接触的第一层级T1与第二层级T2构成。在一些实施例中，第一层级T1包括第一重布线层结构RDL1以及位于第一重布线层结构RDL1上的第一半导体芯片101及第二半导体芯片201，且第二层级T2包括第二重布线层结构RDL2以及位于第二重布线层结构RDL2上的第三半导体芯片300及第四半导体芯片400。
可对多芯片晶片级封装作出可能的修改及变更。提供这些修改及变更是出于说明目的，而不应被视为对本公开内容进行限制。图8至图10是根据替代实施例的多芯片晶片级封装的剖视图。
图8所示多芯片晶片级封装8与图7G所示多芯片晶片级封装7相似，其之间的差异在于，图7G所示第一半导体芯片101及第二半导体芯片201中的每一者是双侧式半导体芯片，而图8所示第一半导体芯片100及第二半导体芯片200中的每一者是单侧式半导体芯片。
图9所示多芯片晶片级封装9与图7G所示多芯片晶片级封装7相似，其之间的差异在于，图9所示多芯片晶片级封装9被设置成不具有第五半导体芯片500及第六半导体芯片600。
图10所示多芯片晶片级封装10与图8所示多芯片晶片级封装8相似，其之间的差异在于，图10所示多芯片晶片级封装10被设置成不具有第五半导体芯片500及第六半导体芯片600。
在以上实施例中，多芯片晶片级封装中的每一者具有两个层级且每一个层级具有两个芯片及一个重布线层结构，其是出于说明目的，而不应被视为对本公开内容进行限制。在一些实施例中，在所述两个层级中的至少一者中可包含多于一个重布线层结构。在一些实施例中，可根据需要将所述两个层级中的至少一者设计成具有单个芯片或多于两个芯片。
图11至图14是根据又一些替代实施例的多芯片晶片级封装的剖视图。
图11所示多芯片晶片级封装11与图3所示多芯片晶片级封装3相似，其之间的差异在于，图11所示多芯片晶片级封装11的第一层级T1具有一个半导体芯片，而图3所示多芯片晶片级封装3的第一层级T1具有两个半导体芯片。具体来说，如图11所示，在第一层级T1中设置有单个半导体芯片(例如，第一半导体芯片100)且所述单个半导体芯片通过第二重布线层结构RDL2电连接到第三半导体芯片300及第四半导体芯片400。
图12所示多芯片晶片级封装12与图3所示多芯片晶片级封装3相似，其之间的差异在于，图12所示多芯片晶片级封装12的第一层级T1具有三个半导体芯片，而图3所示多芯片晶片级封装3的第一层级T1具有两个半导体芯片。具体来说，如图12所示，在第一层级T1中设置有第一半导体芯片100及第二半导体芯片200以及位于第一半导体芯片100与第二半导体芯片200之间的中介片150。在一些实施例中，中介片150具有用于为堆叠芯片提供电连接的贯穿硅中介片(through silicon interposer，TSI)结构。在一些实施例中，中介片150包括硅穿孔、无源器件、熔丝、重布线层及凸块中的至少一些元件。在一些实施例中，第三半导体芯片300通过位于第一半导体芯片100与第二半导体芯片200之间的中介片150电连接到第四半导体芯片400。
图13所示多芯片晶片级封装13与图8所示多芯片晶片级封装8相似，其之间的差异在于，图13所示多芯片晶片级封装13的第一层级T1具有一个半导体芯片，而图8所示多芯片晶片级封装8的第一层级T1具有两个半导体芯片。具体来说，如图13所示，在第一层级T1中设置有单个半导体芯片(例如，第一半导体芯片100)且所述单个半导体芯片通过第二重布线层结构RDL2电连接到第三半导体芯片300及第四半导体芯片400。
图14所示多芯片晶片级封装14与图8所示多芯片晶片级封装8相似，其之间的差异在于，图14所示多芯片晶片级封装14的第一层级T1具有三个半导体芯片，而图8所示多芯片晶片级封装8的第一层级T1具有两个半导体芯片。具体来说，如图14所示，在第一层级T1中设置有第一半导体芯片100及第二半导体芯片200以及位于第一半导体芯片100与第二半导体芯片200之间的中介片150。在一些实施例中，第三半导体芯片300通过位于第一半导体芯片100与第二半导体芯片200之间的中介片150电连接到第四半导体芯片400。
所属领域中的普通技术人员应理解，上述单个芯片或中介片的概念可应用于除了图3及图8之外的图1G、图2、图4至图6、图7G、及图9至图14中的多芯片晶片级封装。
以下参照图1G、图2至图6、图7G、以及图8至图14示出了多种多芯片晶片级封装的结构。在一些实施例中，多芯片晶片级封装1/2/3/4/5/6/7/8/9/10/11/12/13/14包括第一层级T1以及堆叠在第一层级T1上的第二层级T2。
在一些实施例中，第一层级T1包括第一重布线层结构RDL1及位于第一重布线层结构RDL1之上的至少一个芯片。在一些实施例中，所述至少一个芯片可为单个芯片(例如，第一半导体芯片100)，如图11及图13所示。在替代实施例中，所述至少一个芯片包括两个芯片(例如，第一半导体芯片100及第二半导体芯片200或第一半导体芯片101及第二半导体芯片201)，如图1G、图2至图6、图7G及图8至图10所示。在又一些替代实施例中，所述至少一个芯片包括三个芯片(例如，第一半导体芯片100及第二半导体芯片200以及中介片150)，如图12及图14所示。可根据需要在第一层级T1中应用多于三个芯片。在一些实施例中，第一重布线层结构RDL1在侧向上延伸超过所述至少一个芯片，如图1G、图2至图6、图7G、以及图8至图14所示。在一些实施例中，所述至少一个芯片被第一包封层E1包封。在一些实施例中，提供第二包封层E2来包封第一包封层E1，如图7G及图8至图10以及图13至图14所示。
在一些实施例中，第二层级T2包括第二重布线层结构RDL2以及位于第二重布线层结构RDL2之上的至少两个其他芯片。在一些实施例中，所述至少两个其他芯片包括第三半导体芯片300及第四半导体芯片400，如图1G、图2至图6、图7G及图8至图14所示。可根据需要在第二层级T2中应用单个芯片或多于两个芯片。在一些实施例中，第一重布线层结构RDL1在侧向上延伸超过第二重布线层结构RDL2或在侧向上延伸超过所述至少两个其他芯片，如图1G、图2至图6、及图11至图12所示。在替代实施例中，第二重布线层结构RDL2的边缘与第一重布线层结构RDL1的边缘或所述至少两个其他芯片的边缘实质上对齐，如图7G、图8至图10、及图13至图14所示。在一些实施例中，所述至少两个其他芯片被第二包封层E2包封。
在一些实施例中，第一层级T1接合到第二层级T2，使得第一层级T1中的所述至少一个芯片在实体上接触第二层级T2中的第二重布线层结构RDL2。在一些实施例中，第一层级T1中的所述至少一个芯片的连接件及第二层级T2中的所述至少两个其他芯片的连接件在实体上接触第二重布线层结构RDL2。
在一些实施例中，第二层级T2中的所述至少两个其他芯片的连接件的总数目大于(例如，至少两倍、至少五倍、或至少八倍于)第一层级T1中所述至少一个芯片的连接件的总数目。然而，本公开内容并非仅限于此。在替代实施例中，第二层级T2中的所述至少两个其他芯片的连接件的总数目可实质上等于或小于第一层级T1中所述至少一个芯片的连接件的总数目。
在一些实施例中，第一层级T1中的所述至少一个芯片包括集成无源器件芯片，且第二层级T2中的所述至少两个其他芯片中的每一个芯片包括集成有源器件芯片。然而，本公开内容并非仅限于此。在替代实施例中，第一层级T1中的多个芯片中的至少一个芯片包括集成有源器件芯片。在又一些替代实施例中，第二层级T2中的多个芯片中的至少一个芯片包括集成无源器件芯片。
在一些实施例中，多芯片晶片级封装2/3/5/6/7/8/11/12/13/14还包括另一芯片，其位于第一重布线层结构RDL1或第二重布线层结构RDL2之上且位于所述至少一个芯片的外侧。在一些实施例中，所述另一芯片包括第五半导体芯片500及第六半导体芯片600，如图2至图3、图5至图6、图7G、图8及图11至图14所示。在一些实施例中，所述另一芯片被第一包封层E1包封，如图2及图5所示。在替代实施例中，所述另一芯片被第二包封层E2包封，如图3、图6、图7G、图8及图11至图14所示。在一些实施例中，所述另一芯片包括集成无源器件芯片。在替代实施例中，所述另一芯片包括集成有源器件芯片。
在一些实施例中，多芯片晶片级封装1/2/3/4/5/6/7/8/9/10包括第一重布线层结构RDL1、第一半导体芯片100/101、第二半导体芯片200/201、第二重布线层结构RDL2、第三半导体芯片300、第四半导体芯片400及多个凸块112。第一半导体芯片100/101位于第一重布线层结构RDL1的第一侧之上。第二半导体芯片200/201位于第一半导体芯片100/101的侧边且位于第一重布线层结构RDL1的第一侧之上。第二重布线层结构RDL2位于第一半导体芯片100/101及第二半导体芯片200/201之上。第三半导体芯片300位于第二重布线层结构RDL2之上且电连接到第一半导体芯片100/101。第四半导体芯片400位于第二重布线层结构RDL2之上且电连接到第二半导体芯片200/201及第三半导体芯片300。凸块112位于第一重布线层结构RDL1的与第一侧相对的第二侧之上。
在一些实施例中，第一半导体芯片100/101及第二半导体芯片200/201中的至少一者包括集成无源器件芯片。在一些实施例中，第一半导体芯片及第二半导体芯片中的至少一者是在单侧上具有连接件的单侧式半导体芯片，所述连接件接合到第二重布线层结构RDL2。在替代实施例中，第一半导体芯片及第二半导体芯片中的至少一者是在相对两侧上具有连接件的双侧式半导体芯片，所述连接件分别接合到第一重布线层结构RDL1及第二重布线层结构RDL2。在一些实施例中，第三半导体芯片300及第四半导体芯片400中的至少一者包括集成有源器件芯片。
在一些实施例中，第三半导体芯片300通过第二重布线层结构RDL2电连接到第四半导体芯片400。在替代实施例中，第三半导体芯片300通过第二重布线层结构RDL2以及位于第一半导体芯片100与第二半导体芯片200之间的中介片150电连接到第四半导体芯片400。
在一些实施例中，在一些所述多芯片晶片级封装中还包括第五半导体芯片500及第六半导体芯片600。在一些实施例中，第五半导体芯片500及第六半导体芯片600位于第一重布线层结构RDL1的第一侧之上且位于第一半导体芯片100的外侧及第二半导体芯片200的外侧。在替代实施例中，第五半导体芯片500及第六半导体芯片600位于第二重布线层结构RDL2之上且位于第三半导体芯片300的外侧及第四半导体芯片400的外侧。
以上半导体芯片中的每一者的元件或特征仅供用于说明目的，而不应被视为对本公开内容进行限制。所属领域中的普通技术人员应理解，根据需要在半导体芯片中可还包括其他元件或特征。
图17至图20是根据替代实施例的半导体芯片的剖视图。
参照图17，半导体芯片510包括衬底500a、内连结构IS、一个或多个接垫500b、保护层500c、后保护内连结构(post-passivation interconnection structure)PPI、及一个或多个连接件500d。衬底500a包括(例如但不限于)经掺杂或未经掺杂的块状硅、或绝缘体上半导体(SOI)衬底的有源层。内连结构IS可形成在衬底500a上。内连结构IS包括通过至少一个介电层进行嵌置的至少一个金属层。接垫500b形成在内连结构IS之上，且保护层500c形成在接垫500b之上。在一些实施例中，接垫500b是铝接垫，且保护层500c包含聚合物材料，例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、其组合、或类似材料。连接件500d穿过保护层500c形成且电连接到下伏的接垫500b或内连结构IS。在一些实施例中，连接件500d可包含Cu、W、Ni、Sn、Ti、Au、其合金、或其组合，且利用落球工艺或电镀工艺形成。
图18所示半导体芯片511与图17所示半导体芯片510相似，其之间的差异在于，图18所示半导体芯片511还包括位于半导体芯片511的背侧部分中的一个或多个接垫500e以及位于接垫500e与内连结构IS之间且电连接到接垫500e及内连结构IS的一个或多个硅穿孔TSV3。在一些实施例中，在半导体芯片511的背侧上可形成有凸块且所述凸块接合到接垫500e。在一些实施例中，连接件500d构成半导体芯片511的前侧连接件，且接垫500e及/或可选凸块构成半导体芯片511的背侧连接件。
图19所示半导体芯片510’与图17所示半导体芯片510相似，其之间的差异在于连接件结构。在一些实施例中，如图19所示，连接件500d’中的每一者由下到上包括铜层502、镍层503、另一铜层504、及焊料凸块505。可基于工艺要求来使用其他类型的连接结构。
图20所示半导体芯片511’与图18所示半导体芯片511相似，其之间的差异在于连接件结构。在一些实施例中，如图20所示，连接件500d’中的每一者由下到上包括铜层502、镍层503、另一铜层504、及焊料凸块505。可基于工艺要求来使用其他类型的连接结构。
在一些实施例中，可基于工艺要求而由半导体芯片510/510’/511/511’取代所提及的多芯片晶片级封装1至14中的半导体芯片中的至少一者。在一些实施例中，半导体芯片510/510’/511/511’的后保护内连结构PPI可用作电源线、重布线层(RDL)、电感器、电容器或任何无源组件且有助于提高工艺灵活性及提高信号/电源集成度。
综上所述，在本公开内容的一些实施例中，至少一个集成无源器件靠近有源器件设置，且这些集成无源器件及集成有源器件通过包封层嵌置在集成扇出型封装结构中。通过这种设置，可显著减小封装大小，且可大大缩短集成无源器件与对应的集成有源器件之间的解耦合距离。另外，可因此增大重布线层结构中的至少一者的图案节距。因此，工艺裕度可变宽且可节省生产成本。
根据本公开内容的一些实施例，一种多芯片晶片级封装包括第一层级及第二层级。第一层级包括第一重布线层结构及位于所述第一重布线层结构之上的至少一个芯片。第二层级包括第二重布线层结构以及位于所述第二重布线层结构之上的至少两个其他芯片。所述第一层级接合到所述第二层级，使得所述至少一个芯片在实体上接触所述第二重布线层结构。所述至少两个其他芯片的连接件的总数目大于所述至少一个芯片的连接件的总数目。
在一些实施例中，所述第一重布线层结构在侧向上延伸超过所述第二重布线层结构。
在一些实施例中，所述第二重布线层结构的边缘与所述第一重布线层结构的边缘实质上对齐。
在一些实施例中，所述至少一个芯片包括集成无源器件芯片。
在一些实施例中，所述至少两个其他芯片中的每一者包括集成有源器件芯片。
在一些实施例中，所述多芯片晶片级封装还包括另一芯片，其位于所述第一重布线层结构或所述第二重布线层结构之上且位于所述至少一个芯片的外侧。
在一些实施例中，所述另一芯片包括集成无源器件芯片。
根据本公开内容的替代实施例，一种多芯片晶片级封装包括：第一半导体芯片、第二半导体芯片、第二重布线层结构、第三半导体芯片、第四半导体芯片、以及多个凸块。所述第一半导体芯片位于第一重布线层结构的第一侧之上。所述第二半导体芯片位于所述第一半导体芯片的侧边且位于所述第一重布线层结构的所述第一侧之上。所述第二重布线层结构位于所述第一半导体芯片及所述第二半导体芯片之上。所述第三半导体芯片位于所述第二重布线层结构之上且电连接到所述第一半导体芯片。所述第四半导体芯片位于所述第二重布线层结构之上且电连接到所述第二半导体芯片及所述第三半导体芯片。所述凸块位于所述第一重布线层结构的与所述第一侧相对的第二侧之上。
在一些实施例中，所述第三半导体芯片的第三连接件与所述第四半导体芯片的第四连接件的总数目大于所述第一半导体芯片的第一连接件与所述第二半导体芯片的第二连接件的总数目。
在一些实施例中，所述第一重布线层结构在侧向上延伸超过所述第二重布线层结构。
在一些实施例中，所述第三半导体芯片的边缘及所述第四半导体芯片的边缘与所述第二重布线层结构的边缘实质上对齐。
在一些实施例中，所述第一半导体芯片及所述第二半导体芯片中的至少一者包括集成无源器件芯片。
在一些实施例中，所述第一半导体芯片及所述第二半导体芯片中的至少一者是在单侧上具有连接件的单侧式半导体芯片，所述连接件接合到所述第二重布线层结构。
在一些实施例中，所述第一半导体芯片及所述第二半导体芯片中的至少一者是在相对两侧上具有连接件的双侧式半导体芯片，所述连接件分别接合到所述第一重布线层结构及所述第二重布线层结构。
在一些实施例中，所述第三半导体芯片及所述第四半导体芯片中的至少一者包括集成有源器件芯片。
在一些实施例中，所述第三半导体芯片通过位于所述第一半导体芯片与所述第二半导体芯片之间的中介片电连接到所述第四半导体芯片。
在一些实施例中，所述多芯片晶片级封装还包括：第一包封层，包封所述第一半导体芯片及所述第二半导体芯片；以及第二包封层，包封所述第三半导体芯片及所述第四半导体芯片。
在一些实施例中，所述多芯片晶片级封装还包括第五半导体芯片及第六半导体芯片，其位于所述第一重布线层结构的所述第一侧之上且位于所述第一半导体芯片的外侧及所述第二半导体芯片的外侧。
根据本公开内容的又一替代实施例，一种形成多芯片晶片级封装的方法包括：提供载板，所述载板上形成有第一重布线层结构；将第一集成无源器件芯片及第二集成无源器件芯片放置在所述第一重布线层结构的第一侧上；使用第一包封层包封所述第一集成无源器件芯片及所述第二集成无源器件芯片；在所述第一包封层上形成第二重布线层结构；将第一集成有源器件芯片及第二集成有源器件芯片放置在所述第二重布线层结构上；使用第二包封层包封所述第一集成有源器件芯片及所述第二集成有源器件芯片；以及剥离所述载板。
在一些实施例中，所述方法还包括：在所述第一集成有源器件芯片及所述第二集成有源器件芯片的侧边形成第三集成无源器件芯片及第四集成无源器件芯片，并使用所述第二包封层包封所述第三集成无源器件芯片及所述第四集成无源器件芯片。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开内容的各个方面。所属领域中的技术人员应知，其可容易地使用本公开内容作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开内容的精神及范围，而且他们可在不背离本公开内容的精神及范围的条件下对其作出各种改变、代替、及变更。
[符号的说明]
1、2、3、4、5、6、7、8、9、10、11、12、13、14：多芯片晶片级封装
100、100’、101、101’：第一半导体芯片
100a、200a、300a、400a、500a：衬底
100b、200b：接垫
100e、200e：接垫
100c、200c、300c、400c、500c：保护层
100d、200d、300d、400d、500d、500d’：连接件
102：聚合物层
103、110：连接接垫
104：重布线层
105、112、300e、400e、501、601：凸块
106：聚合物层
108：重布线层
150：中介片
200、200’、201、201’：第二半导体芯片
300：第三半导体芯片
300b、400b、500b、500e：接垫
400：第四半导体芯片
500：第五半导体芯片
510、510’、511、511’：半导体芯片
502、504：铜层
503：镍层
505：焊料凸块
600：第六半导体芯片
C：载板
C1：第一载板
C2：第二载板
CA1、CA2：深沟槽电容器区
CM：芯片模块
DB：剥离层
DB1：第一剥离层
DB2：第二剥离层
E1：第一包封层
E2：第二包封层
IS：内连结构
PPI：后保护内连结构
RDL1：第一重布线层结构
RDL2：第二重布线层结构
T1：第一层级
T2：第二层级
TSV1、TSV2、TSV3：硅穿孔
TIV：集成扇出型穿孔
UF、UF1、UF2：底部填充胶层

Claims (1)

1.一种多芯片晶片级封装，其特征在于包括：
第一层级，包括第一重布线层结构及位于所述第一重布线层结构之上的至少一个芯片；以及
第二层级，包括第二重布线层结构以及位于所述第二重布线层结构之上的至少两个其他芯片，
其中所述第一层级接合到所述第二层级，使得所述至少一个芯片在实体上接触所述第二重布线层结构，且
其中所述至少两个其他芯片的连接件的总数目大于所述至少一个芯片的连接件的总数目。
CN201810022467.4A 2017-10-27 2018-01-10 多芯片晶片级封装及其形成方法 Pending CN109727964A (zh)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111554656A (zh) * 2020-04-30 2020-08-18 通富微电子股份有限公司 一种半导体封装器件
CN111599768A (zh) * 2019-02-21 2020-08-28 力成科技股份有限公司 半导体封装及其制造方法
CN112117248A (zh) * 2019-06-20 2020-12-22 矽品精密工业股份有限公司 电子封装件及其制法
CN112652608A (zh) * 2019-10-09 2021-04-13 财团法人工业技术研究院 多芯片封装件及其制造方法
CN112652605A (zh) * 2019-10-09 2021-04-13 财团法人工业技术研究院 多芯片封装件及其制造方法
CN114899185A (zh) * 2022-07-12 2022-08-12 之江实验室 一种适用于晶圆级异质异构芯粒的集成结构和集成方法

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11239185B2 (en) * 2017-11-03 2022-02-01 Dialog Semiconductor (Uk) Limited Embedded resistor-capacitor film for fan out wafer level packaging
WO2019139625A1 (en) * 2018-01-12 2019-07-18 Intel Corporation First layer interconnect first on carrier approach for emib patch
US20200035591A1 (en) * 2018-07-30 2020-01-30 Dyi-chung Hu Interposer and manufacturing method thereof
KR102560697B1 (ko) 2018-07-31 2023-07-27 삼성전자주식회사 인터포저를 가지는 반도체 패키지
KR102536269B1 (ko) * 2018-09-14 2023-05-25 삼성전자주식회사 반도체 패키지 및 그 제조 방법
TWI680593B (zh) * 2018-10-12 2019-12-21 欣興電子股份有限公司 發光元件封裝結構及其製造方法
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
US10971446B2 (en) 2018-11-30 2021-04-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11476200B2 (en) * 2018-12-20 2022-10-18 Nanya Technology Corporation Semiconductor package structure having stacked die structure
KR20200099805A (ko) * 2019-02-15 2020-08-25 삼성전자주식회사 반도체 패키지
KR102595865B1 (ko) * 2019-03-04 2023-10-30 삼성전자주식회사 하이브리드 인터포저를 갖는 반도체 패키지
US11063013B2 (en) * 2019-05-15 2021-07-13 Advanced Semiconductor Engineering, Inc. Semiconductor package structure
US11189599B2 (en) * 2019-05-30 2021-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. System formed through package-in-package formation
US11837526B2 (en) * 2019-06-24 2023-12-05 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method for manufacturing the same
US11107770B1 (en) * 2019-06-27 2021-08-31 Xilinx, Inc. Integrated electrical/optical interface with two-tiered packaging
US11088079B2 (en) * 2019-06-27 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having line connected via portions
US11195816B2 (en) * 2019-07-23 2021-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages comprising a plurality of redistribution structures and methods of forming the same
US11145638B2 (en) * 2019-09-16 2021-10-12 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
KR20210044934A (ko) 2019-10-15 2021-04-26 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US11177221B2 (en) * 2019-10-18 2021-11-16 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
TWI701777B (zh) * 2019-10-22 2020-08-11 財團法人工業技術研究院 影像感測器封裝件及其製造方法
US20210159182A1 (en) * 2019-11-22 2021-05-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor Devices and Methods of Manufacture
DE102020116106B4 (de) * 2019-11-22 2023-11-09 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtungen und herstellungsverfahren
US20210159188A1 (en) * 2019-11-22 2021-05-27 Advanced Semiconductor Engineering, Inc. Package structure and method for manufacturing the same
KR20210087337A (ko) 2020-01-02 2021-07-12 삼성전자주식회사 반도체 패키지와 이를 구비하는 전자 장치 및 반도체 패키지의 제조방법
KR20210110008A (ko) * 2020-02-28 2021-09-07 삼성전자주식회사 반도체 패키지
US11302643B2 (en) 2020-03-25 2022-04-12 Intel Corporation Microelectronic component having molded regions with through-mold vias
TWI777467B (zh) * 2020-03-30 2022-09-11 台灣積體電路製造股份有限公司 半導體裝置及其製造方法
US11410982B2 (en) 2020-03-30 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacturing
JP2023520029A (ja) 2020-04-03 2023-05-15 ウルフスピード インコーポレイテッド 裏面ソース端子、ゲート端子及び／又はドレイン端子を有するｉｉｉ族窒化物ベースの高周波増幅器
CN115699326A (zh) 2020-04-03 2023-02-03 沃孚半导体公司 具有源极、栅极和/或漏极导电通孔的基于iii族氮化物的射频晶体管放大器
US20210313283A1 (en) * 2020-04-03 2021-10-07 Cree, Inc. Multi level radio frequency (rf) integrated circuit components including passive devices
US11488901B2 (en) * 2020-04-29 2022-11-01 Advanced Semiconductor Engineering, Inc. Package structure and method for manufacturing the same
US11456245B2 (en) * 2020-05-28 2022-09-27 Taiwan Semiconductor Manufacturing Company Limited Silicon interposer including through-silicon via structures with enhanced overlay tolerance and methods of forming the same
US11715754B2 (en) * 2020-06-09 2023-08-01 Mediatek Inc. Semiconductor package with TSV inductor
US11296065B2 (en) 2020-06-15 2022-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages and methods of forming same
US11424213B2 (en) * 2020-09-10 2022-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure including a first surface mount component and a second surface mount component and method of fabricating the semiconductor structure
US11658103B2 (en) * 2020-09-11 2023-05-23 Qualcomm Incorporated Capacitor interposer layer (CIL) chiplet design with conformal die edge pattern around bumps
EP3975226A1 (en) * 2020-09-28 2022-03-30 Infineon Technologies Austria AG A semiconductor device module comprising vertical metallic contacts and a method for fabricating the same
US11728266B2 (en) 2020-12-23 2023-08-15 Apple Inc. Die stitching and harvesting of arrayed structures
US20220262766A1 (en) * 2021-02-12 2022-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Through-Dielectric Vias for Direct Connection and Method Forming Same
KR20220117032A (ko) 2021-02-16 2022-08-23 삼성전자주식회사 반도체 패키지
US11756873B2 (en) 2021-02-26 2023-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11830798B2 (en) * 2021-03-22 2023-11-28 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US20220344250A1 (en) * 2021-04-22 2022-10-27 Qualcomm Incorporated Integrated circuit (ic) packages employing a capacitor-embedded, redistribution layer (rdl) substrate for interfacing an ic chip(s) to a package substrate, and related methods
US11769712B2 (en) * 2021-05-28 2023-09-26 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US20220392832A1 (en) * 2021-06-06 2022-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods of forming the same
US11978729B2 (en) * 2021-07-08 2024-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package having warpage control and method of forming the same
US20230065615A1 (en) * 2021-08-27 2023-03-02 Advanced Semiconductor Engineering, Inc. Electronic device

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6064187A (en) * 1999-02-12 2000-05-16 Analog Devices, Inc. Voltage regulator compensation circuit and method
JP3861669B2 (ja) * 2001-11-22 2006-12-20 ソニー株式会社 マルチチップ回路モジュールの製造方法
US20060267927A1 (en) * 2005-05-27 2006-11-30 Crenshaw James E User interface controller method and apparatus for a handheld electronic device
TWI414580B (zh) * 2006-10-31 2013-11-11 Sumitomo Bakelite Co 黏著帶及使用該黏著帶而成之半導體裝置
KR100909902B1 (ko) * 2007-04-27 2009-07-30 삼성전자주식회사 플래쉬 메모리 장치 및 플래쉬 메모리 시스템
TWI401753B (zh) * 2009-12-31 2013-07-11 Advanced Semiconductor Eng 可堆疊式封裝結構之製造方法
TWI418269B (zh) * 2010-12-14 2013-12-01 Unimicron Technology Corp 嵌埋穿孔中介層之封裝基板及其製法
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
KR20120110451A (ko) * 2011-03-29 2012-10-10 삼성전자주식회사 반도체 패키지
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US8975726B2 (en) * 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US9478474B2 (en) * 2012-12-28 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for forming package-on-packages
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9633869B2 (en) * 2013-08-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with interposers and methods for forming the same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9601463B2 (en) * 2014-04-17 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) and the methods of making the same
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
WO2016025478A1 (en) * 2014-08-11 2016-02-18 Massachusetts Institute Of Technology Interconnect structures for assembly of semiconductor structures including at least one integrated circuit structure
US20160086930A1 (en) * 2014-09-24 2016-03-24 Freescale Semiconductor, Inc. Fan-out wafer level package containing back-to-back embedded microelectronic components and assembly method therefor
US9666502B2 (en) * 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9601471B2 (en) * 2015-04-23 2017-03-21 Apple Inc. Three layer stack structure
US20160343685A1 (en) * 2015-05-21 2016-11-24 Mediatek Inc. Semiconductor package assembly and method for forming the same
US9679801B2 (en) * 2015-06-03 2017-06-13 Apple Inc. Dual molded stack TSV package
US9768145B2 (en) * 2015-08-31 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multi-die package structures including redistribution layers
US20170098629A1 (en) * 2015-10-05 2017-04-06 Mediatek Inc. Stacked fan-out package structure
US9627365B1 (en) * 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
US10483211B2 (en) * 2016-02-22 2019-11-19 Mediatek Inc. Fan-out package structure and method for forming the same
US9831148B2 (en) * 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
US10833052B2 (en) * 2016-10-06 2020-11-10 Micron Technology, Inc. Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111599768A (zh) * 2019-02-21 2020-08-28 力成科技股份有限公司 半导体封装及其制造方法
CN112117248A (zh) * 2019-06-20 2020-12-22 矽品精密工业股份有限公司 电子封装件及其制法
CN112117248B (zh) * 2019-06-20 2022-07-05 矽品精密工业股份有限公司 电子封装件及其制法
CN112652608A (zh) * 2019-10-09 2021-04-13 财团法人工业技术研究院 多芯片封装件及其制造方法
CN112652605A (zh) * 2019-10-09 2021-04-13 财团法人工业技术研究院 多芯片封装件及其制造方法
CN111554656A (zh) * 2020-04-30 2020-08-18 通富微电子股份有限公司 一种半导体封装器件
CN114899185A (zh) * 2022-07-12 2022-08-12 之江实验室 一种适用于晶圆级异质异构芯粒的集成结构和集成方法

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