CN112117248A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN112117248A
CN112117248A CN201910542299.6A CN201910542299A CN112117248A CN 112117248 A CN112117248 A CN 112117248A CN 201910542299 A CN201910542299 A CN 201910542299A CN 112117248 A CN112117248 A CN 112117248A
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layer
conductive
electronic
circuit structure
electrically connected
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CN112117248B (zh
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黄公敦
李弘和
郑子企
林长甫
邱启新
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

本发明涉及一种电子封装件及其制法，包括：嵌埋有第一电子元件与导电柱的包覆层；设于该包覆层的其中一表面上的线路结构；设于该线路结构上的第二电子元件；以及设于该包覆层的另一表面上的绝缘层；以及设于该绝缘层上的线路部，以经由在该线路结构二侧配置有第一与第二电子元件，使该电子封装件具有多功能、高效能的优点。

Description

电子封装件及其制法
技术领域
本发明有关一种半导体封装技术，尤指一种电子封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。为了满足电子封装件微型化(miniaturization)的封装需求，发展出晶圆级封装(Wafer LevelPackaging，简称WLP)技术。
图1A至图1E为现有采用晶圆级封装技术的半导体封装件1的制法的剖面示意图。
如图1A所示，形成一热化离形胶层(thermal release tape)100于一承载件10上。
接着，置放多个半导体元件11于该热化离形胶层100上，该些半导体元件11具有相对的作用面11a与非作用面11b，各该作用面11a上具有多个电极垫110，且各该作用面11a粘着于该热化离形胶层100上。
如图1B所示，形成一封装胶体14于该热化离形胶层100上，以包覆该半导体元件11。
如图1C所示，烘烤该封装胶体14以硬化该热化离形胶层100，进而移除该热化离形胶层100与该承载件10，以外露出该半导体元件11的作用面11a。
如图1D所示，形成一线路结构16于该封装胶体14与该半导体元件11的作用面11a上，令该线路结构16电性连接该电极垫110。接着，形成一绝缘保护层18于该线路结构16上，且该绝缘保护层18外露该线路结构16的部分表面，以供结合如焊球的导电元件17。
如图1E所示，沿如图1D所示的切割路径L进行切单制程，以获取多个个半导体封装件1。
但是，现有半导体封装件1，仅于该线路结构16单侧设置有半导体元件11，使该半导体封装件1的功能及效能受限，限制终端电子产品的功能及效能。
因此，如何克服现有技术的种种缺点，实为目前各界亟欲解决的技术问题。
发明内容
鉴于上述现有技术的缺陷，本发明提供一种电子封装件及其制法，可使电子封装件具有多功能、高效能的优点。
本发明的电子封装件的制法，包括：提供一具有绝缘层的承载板；形成多个导电柱于该绝缘层上，且设置第一电子元件于该绝缘层上；形成包覆层于该绝缘层上，以令该包覆层包覆该第一电子元件与该导电柱，其中，该包覆层具有相对的第一表面与第二表面，以令该导电柱的端面外露于该包覆层的第一表面，且令该包覆层以其第二表面结合至该绝缘层上；形成线路结构于该包覆层的第一表面上，且令该线路结构电性连接至该导电柱与该第一电子元件；设置第二电子元件于该线路结构上，且令该第二电子元件电性连接该线路结构；以及移除该承载板，且保留该绝缘层。
本发明还提供一种电子封装件，包括：包覆层，其具有相对的第一表面与第二表面；第一电子元件，其嵌埋于该包覆层中；多个导电柱，其嵌埋于该包覆层中；线路结构，其设于该包覆层的第一表面上且电性连接该导电柱与该第一电子元件；第二电子元件，其设于该线路结构上且电性连接该线路结构；以及绝缘层，其形成于该包覆层的第二表面上。
前述的电子封装件及其制法中，该第一电子元件上结合及电性连接多个导电体，使该导电体嵌埋于该包覆层中并电性连接该线路结构。例如，该第一电子元件具有相对的作用面与非作用面，且该作用面结合并电性连接该些导电体；或者，该包覆层的第一表面齐平该导电体的端面。
前述的电子封装件及其制法中，该包覆层的第一表面齐平该导电柱的端面。
前述的电子封装件及其制法中，该第二电子元件经由导电凸块设于该线路结构上以电性连接该线路结构。
前述的电子封装件及其制法中，还包括形成封装层于该线路结构上，以包覆该第二电子元件。
前述的电子封装件及其制法中，还包括形成线路部于绝缘层上，且令该线路部电性连接该导电柱，例如，该线路部为电性接触垫及/或凸块底下金属层。进一步包括形成多个导电元件于该线路部上。又包括设置封装基板于该线路部上。
前述的电子封装件及其制法中，还包括移除该导电柱的端部的部分材料，以令该导电柱于靠近其中一端面的周面形成有凹状。
由上可知，本发明的电子封装件及其制法，主要经由该线路结构的设计，以接置该第二电子元件，故相比于现有技术，本发明的电子封装件在线路结构二侧配置有相对位于上、下位置的第一电子元件与第二电子元件，使该电子封装件具有多功能、高效能的优点。
此外，经由该导电柱的端面作为外接点，可利于控制各该外接点的间的距离，以符合细间距的需求，且能避免各该外接点上的导电元件之间发生桥接。
附图说明
图1A至图1E为现有半导体封装件的制法的剖面示意图；以及
图2A至图2H为本发明的电子封装件及其制法的剖面示意图，其中，图2B’为图2B的局部放大示意图，图2G’为图2G的另一实施例示意图。
符号说明
1 半导体封装件 10 承载件
100 热化离形胶层 11 半导体元件
11a,21a 作用面 11b,21b 非作用面
110,210 电极垫 14 封装胶体
16,20 线路结构 17,24,29 导电元件
18 绝缘保护层 2 电子封装件
2a 封装基板 2b 强固件
200 绝缘层 201 线路重布层
202 电性接触垫 21 第一电子元件
211 保护膜 212 结合层
22 导电体 22a 端面
23 导电柱 23a,23b 端面
23c 周面 240,240’ 线路部
25 包覆层 25a 第一表面
25b 第二表面 26 第二电子元件
260 底胶 27 导电凸块
270 凸块底下金属层 28 封装层
9 承载板 9a 晶种层
9b 金属层 90 离型层
91 绝缘层 L,S 切割路径。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2H为本发明的电子封装件2的制法的剖面示意图。
如图2A及图2B所示，提供一具有晶种层9a的承载板9，再于该承载板9上经由该晶种层9a形成多个导电柱23。接着，设置至少一第一电子元件21于该承载板9上，其中，该第一电子元件21上结合并电性连接多个导电体22，且该导电体22为如导电线路、焊球的圆球状、或如铜柱、焊锡凸块等金属材的柱状、或焊线机制作的钉状(stud)导电件，但不限于此。
在本实施例中，该承载板9例如为半导体材料(如硅或玻璃)的板体，其上以例如涂布方式依序形成有一离型层90、如钛/铜的金属层9b与一如介电材或防焊材的绝缘层91，以供该晶种层9a设于该绝缘层91上。
此外，于图2A中，该晶种层9a上可形成有一图案化阻层(图略)，以令该阻层外露该晶种层9a的部分表面，从而供布设该些导电柱23。待制作该些导电柱23后，移除该图案化阻层及其下的晶种层9a，如图2B所示，且于蚀刻移除该晶种层9a时，会侧蚀该导电柱23的端部，如图2B’所示的周面23c，以令该导电柱23的周面23c形成凹状。
又，形成该导电柱23的材料为如铜的金属材或焊锡材，且形成该晶种层9a的材料例如为钛/铜。
另外，该第一电子元件21为主动元件、被动元件或其二者组合，且该主动元件例如为半导体芯片，而该被动元件例如为电阻、电容及电感。于本实施例中，该第一电子元件21为半导体芯片，其具有相对的作用面21a与非作用面21b，该第一电子元件21以其非作用面21b经由一结合层212粘固于该绝缘层91上，而该作用面21a具有多个电极垫210与一如钝化材的保护膜211，且该导电体22形成于该保护膜211中。
如图2C所示，形成一包覆层25于该承载板9的绝缘层91上，以令该包覆层25包覆该第一电子元件21、该些导电体22与该些导电柱23，其中，该包覆层25具有相对的第一表面25a与第二表面25b，且令该保护膜211、该导电体22的端面22a与该导电柱23的端面23a外露于该包覆层25的第一表面25a，以及令该包覆层25以其第二表面25b结合至该承载板9的绝缘层91上。
在本实施例中，该包覆层25为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dryfilm)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)。例如，该包覆层25的制程可选择液态封胶(liquid compound)、喷涂(injection)、压合(lamination)或模压(compression molding)等方式形成于该绝缘层91上。
此外，可经由整平制程，使该包覆层25的第一表面25a齐平该保护膜211、该导电柱23的端面23a与该导电体22的端面22a，以令该导电柱23的端面23a与该导电体22的端面22a外露于该包覆层25的第一表面25a。例如，该整平制程经由研磨方式，移除该保护膜211的部分材料、该导电柱23的部分材料、该导电体22的部分材料与该包覆层25的部分材料。
又，该些导电柱23的另一端面23b(忽略该晶种层9a)也可大致齐平该包覆层25的第二表面25b。
如图2D所示，形成一线路结构20于该包覆层25的第一表面25a上，且令该线路结构20电性连接该导电柱23与该导电体22。
在本实施例中，该线路结构20包括多个绝缘层200及设于该绝缘层200上的多个线路重布层(redistribution layer，简称RDL)201，且最外层的绝缘层200可作为防焊层，且令最外层的线路重布层201外露于该防焊层，从而供作为电性接触垫202，如微垫(micropad，俗称μ-pad)。或者，该线路结构20也可仅包括单一绝缘层200及单一线路重布层201。
此外，形成该线路重布层201的材料为铜，且形成该绝缘层200的材料为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)等的介电材、或如绿漆、油墨等的防焊材。
如图2E所示，设置至少一第二电子元件26于该线路结构20上，再以一封装层28包覆该第二电子元件26。
在本实施例中，该第二电子元件26为主动元件、被动元件或其二者组合，且该主动元件例如为半导体芯片，而该被动元件例如为电阻、电容及电感。于一实施实施例中，该第二电子元件26例如为图形处理器(graphics processing unit，简称GPU)、高频宽存储器(HighBandwidth Memory，简称HBM)等半导体芯片，并无特别限制。
此外，该第二电子元件26经由多个如焊锡凸块、铜凸块或其它等的导电凸块27电性连接该电性接触垫202，且该封装层28可同时包覆该第二电子元件26与该些导电凸块27。于本实施例中，可形成一凸块底下金属层(Under Bump Metallurgy，简称UBM)270于该电性接触垫202上，以利于结合该导电凸块27。
又，该封装层28为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dry film)、如环氧树脂(expoxy)的封装胶体或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该第一线路结构20上。应可理解地，形成该封装层28的材料可相同或不相同该包覆层25的材料。
另外，也可先形成底胶260于该第二电子元件26与该线路结构20之间以包覆该些导电凸块27，再形成该封装层28以包覆该底胶260与该第二电子元件26。
如图2F所示，移除该承载板9及其上的离型层90与金属层9b，并保留该绝缘层91。
在本实施例中，于剥离该离型层90时，经由该金属层9b作为阻障之用，以避免破坏该绝缘层91，且待移除该承载板9及其上的离型层90后，再以蚀刻方式移除该金属层9b。
如图2G所示，形成一线路部240于该绝缘层91上以电性连接该导电柱23。
在本实施例中，该绝缘层91经由雷射方式形成有多个开孔，以令该些导电柱23的端面23b及该包覆层25的部分第二表面25b外露于该些开孔，从而供结合该线路部240。例如，该线路部240为凸块底下金属层(UBM)，以结合如多个焊锡凸块或焊球(其规格为C4型)的导电元件24；或者，如图2G’所示，该线路部240’为多个电性接触垫，其可经由RDL制程形成于该绝缘层91上，以结合该导电元件24或UBM。
此外，可经由整平制程，如研磨方式，移除该封装层28的部分材料，使该封装层28的上表面齐平该第二电子元件26的表面，以令该第二电子元件26外露于该封装层28。
又，经由提供具有绝缘层91的承载板9，以于移除该承载板9后，可利用该绝缘层91形成该线路部240,240’，因而无需再布设介电层，故能节省制程时间与制程步骤，以达到降低制程成本的目的。
如图2H所示，沿如图2G所示的切割路径S进行切单制程，以获取多个封装单元，再将该封装单元经由该些导电元件24设置于一封装基板2a上。
在本实施例中，该封装基板2a下侧进行植球制程以形成多个如焊球的导电元件29，以形成电子封装件2。于后续制程中，该电子封装件2可以其封装基板2a下侧的导电元件29设于一电路板(图略)上。
此外，该封装基板2a上可依需求设置一强固件2b，如金属框，以消除应力集中的问题而避免该封装基板2a发生翘曲的情况。
因此，本发明的制法中，经由该线路结构20的电性接触垫202与该导电柱23的端面23b作为外接点，可利于控制各该外接点之间的距离，以符合细间距的需求，且能避免各该导电凸块27或各该导电元件24之间发生桥接。
此外，本发明的制法经由该线路结构20的设计，以接置该第二电子元件26，故相比于现有技术，本发明的电子封装件2在线路结构20二侧配置有相对位于上、下位置的第一电子元件20与第二电子元件26，使该电子封装件2具有多功能、高效能的优点。
本发明还提供一种电子封装件2，其包括：一包覆层25、一第一电子元件21、多个导电柱23、一线路结构20、一第二电子元件26以及一线路部240,240’。
所述的包覆层25具有相对的第一表面25a与第二表面25b。
所述的第一电子元件21嵌埋于该包覆层25中，且该第一电子元件21上结合并电性连接多个导电体22，其中，该导电体22嵌埋于该包覆层25中，且令该导电体22的端面22a外露于该包覆层25的第一表面25a。
所述的导电柱23嵌埋于该包覆层25中，且令该导电柱23的端面22a外露于该包覆层25的第一表面25a。
所述的线路结构20设于该包覆层25的第一表面25a上且电性连接该导电柱23与该导电体22。
所述的第二电子元件26设于该线路结构20上且电性连接该线路结构20。
所述的线路部240,240’形成于该包覆层25的第二表面25b上且电性连接该导电柱23。
在一实施例中，该第一电子元件21具有保护膜211，且该导电体22凸出该保护膜211。
在一实施例中，该第一电子元件21具有相对的作用面21a与非作用面21b，且该作用面21a结合并电性连接该些导电体22。
在一实施例中，该包覆层25的第一表面25a齐平该导电柱23的端面23a。
在一实施例中，该包覆层25的第二表面25b齐平该导电柱23的另一端面23b。
在一实施例中，该包覆层25的第一表面25a齐平该导电体22的端面22a。
在一实施例中，该第二电子元件26经由多个导电凸块27设于该线路结构20上以电性连接该线路结构20。
在一实施例中，该线路部24为电性接触垫及/或凸块底下金属层。
在一实施例中，所述的电子封装件2还包括一形成于该线路结构20上的封装层28，其包覆该第二电子元件26。
在一实施例中，所述的电子封装件2还包括一设于该线路部24上的封装基板2a。
在一实施例中，该导电柱23于靠近其中一端面23b(或晶种层9a)的周面23c形成有凹状。
综上所述，本发明的电子封装件及其制法，经由该线路结构与线路部的设计，不仅使封装件的尺寸较小，且能增加外接点的数量，并且当应用于细间距产品时，可避免各该外接点之间发生桥接。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (24)

1.一种电子封装件的制法，其特征在于，包括：
提供一具有绝缘层的承载板；
形成多个导电柱于该绝缘层上，且设置第一电子元件于该绝缘层上；
形成包覆层于该绝缘层上，以令该包覆层包覆该第一电子元件与该导电柱，其中，该包覆层具有相对的第一表面与第二表面，该导电柱的端面外露于该包覆层的第一表面，且该包覆层以其第二表面结合至该绝缘层上；
形成线路结构于该包覆层的第一表面上，且令该线路结构电性连接该导电柱与该第一电子元件；
设置第二电子元件于该线路结构上，且令该第二电子元件电性连接该线路结构；以及
移除该承载板，且保留该绝缘层。
2.根据权利要求1所述的电子封装件的制法，其特征在于，该第一电子元件上结合及电性连接多个导电体，该导电体嵌埋于该包覆层中并电性连接该线路结构。
3.根据权利要求2所述的电子封装件的制法，其特征在于，该第一电子元件具有相对的作用面与非作用面，以于该作用面结合并电性连接该多个导电体。
4.根据权利要求2所述的电子封装件的制法，其特征在于，该包覆层的第一表面齐平该导电体的端面。
5.根据权利要求1所述的电子封装件的制法，其特征在于，该包覆层的第一表面齐平该导电柱的端面。
6.根据权利要求1所述的电子封装件的制法，其特征在于，该第二电子元件经由导电凸块设于该线路结构上以电性连接该线路结构。
7.根据权利要求1所述的电子封装件的制法，其特征在于，该制法还包括形成封装层于该线路结构上，以包覆该第二电子元件。
8.根据权利要求1所述的电子封装件的制法，其特征在于，该制法还包括形成线路部于绝缘层上，且令该线路部电性连接该导电柱。
9.根据权利要求8所述的电子封装件的制法，其特征在于，该线路部为电性接触垫及/或凸块底下金属层。
10.根据权利要求8所述的电子封装件的制法，其特征在于，该制法还包括形成多个导电元件于该线路部上。
11.根据权利要求10所述的电子封装件的制法，其特征在于，该制法还包括设置封装基板于该多个导电元件上。
12.根据权利要求1所述的电子封装件的制法，其特征在于，该制法还包括移除该导电柱的端部的部分材料，以令该导电柱的周面形成凹状。
13.一种电子封装件，其特征在于，包括：
包覆层，其具有相对的第一表面与第二表面；
第一电子元件，其嵌埋于该包覆层中；
多个导电柱，其嵌埋于该包覆层中；
线路结构，其形成于该包覆层的第一表面上且电性连接该导电柱与该第一电子元件；
第二电子元件，其设于该线路结构上且电性连接该线路结构；以及
绝缘层，其设于该包覆层的第二表面上。
14.根据权利要求13所述的电子封装件，其特征在于，该第一电子元件上结合及电性连接多个导电体，该导电体嵌埋于该包覆层中并电性连接该线路结构。
15.根据权利要求14所述的电子封装件，其特征在于，该第一电子元件具有相对的作用面与非作用面，且该作用面结合并电性连接该多个导电体。
16.根据权利要求14所述的电子封装件，其特征在于，该包覆层的第一表面齐平该导电体的端面。
17.根据权利要求13所述的电子封装件，其特征在于，该包覆层的第一表面齐平该导电柱的端面。
18.根据权利要求13所述的电子封装件，其特征在于，该第二电子元件经由导电凸块设于该线路结构上以电性连接该线路结构。
19.根据权利要求13所述的电子封装件，其特征在于，该电子封装件还包括形成于该线路结构上以包覆该第二电子元件的封装层。
20.根据权利要求13所述的电子封装件，其特征在于，该电子封装件还包括线路部，其形成于该绝缘层上且电性连接该导电柱。
21.根据权利要求20所述的电子封装件，其特征在于，该线路部为电性接触垫及/或凸块底下金属层。
22.根据权利要求20所述的电子封装件，其特征在于，该电子封装件还包括形成于该线路部上的多个导电元件。
23.根据权利要求22所述的电子封装件，其特征在于，该电子封装件还包括设置于该多个导电元件上的封装基板。
24.根据权利要求13所述的电子封装件，其特征在于，该导电柱于靠近其中一端面的周面形成有凹状。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210152721A (ko) * 2020-06-09 2021-12-16 삼성전자주식회사 반도체 패키지
KR20220109753A (ko) * 2021-01-29 2022-08-05 삼성전자주식회사 포스트를 포함하는 반도체 패키지
US20220328467A1 (en) * 2021-04-08 2022-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Molded dies in semicondcutor packages and methods of forming same
US11978729B2 (en) * 2021-07-08 2024-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package having warpage control and method of forming the same
US20230060520A1 (en) * 2021-08-27 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and semiconductor device
TWI790916B (zh) * 2022-02-09 2023-01-21 矽品精密工業股份有限公司 電子封裝件及其製法
TWI825790B (zh) * 2022-06-17 2023-12-11 矽品精密工業股份有限公司 電子封裝件及其製法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020096787A1 (en) * 1994-12-29 2002-07-25 Tessera, Inc. Connection components with posts
JP2007335464A (ja) * 2006-06-12 2007-12-27 Nec Corp 金属ポストを有する配線基板、半導体装置、半導体装置モジュール及びそれらの製造方法
CN103201835A (zh) * 2010-07-08 2013-07-10 德塞拉股份有限公司 具有双重或多重蚀刻倒装芯片连接体的微电子封装和相应的制造方法
CN104051383A (zh) * 2013-03-15 2014-09-17 台湾积体电路制造股份有限公司 封装的半导体器件、封装半导体器件的方法以及PoP器件
CN106206482A (zh) * 2015-05-29 2016-12-07 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN109727964A (zh) * 2017-10-27 2019-05-07 台湾积体电路制造股份有限公司 多芯片晶片级封装及其形成方法
US20190139911A1 (en) * 2017-11-03 2019-05-09 Dialog Semiconductor (Uk) Limited Embedded Resistor-Capacitor Film for Fan Out Wafer Level Packaging
CN109844934A (zh) * 2016-10-27 2019-06-04 英帆萨斯公司 用于低温接合的结构和方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI569390B (zh) * 2015-11-16 2017-02-01 矽品精密工業股份有限公司 電子封裝件及其製法
US10163827B1 (en) * 2017-11-14 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with protrusion structure
US10734323B2 (en) * 2017-11-22 2020-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures
TW201926605A (zh) * 2017-11-22 2019-07-01 矽品精密工業股份有限公司 電子封裝件及其製法
TWI643307B (zh) * 2018-01-30 2018-12-01 矽品精密工業股份有限公司 電子封裝件及其製法
US10665545B2 (en) * 2018-09-19 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices, semiconductor packages and methods of forming the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020096787A1 (en) * 1994-12-29 2002-07-25 Tessera, Inc. Connection components with posts
JP2007335464A (ja) * 2006-06-12 2007-12-27 Nec Corp 金属ポストを有する配線基板、半導体装置、半導体装置モジュール及びそれらの製造方法
CN103201835A (zh) * 2010-07-08 2013-07-10 德塞拉股份有限公司 具有双重或多重蚀刻倒装芯片连接体的微电子封装和相应的制造方法
CN104051383A (zh) * 2013-03-15 2014-09-17 台湾积体电路制造股份有限公司 封装的半导体器件、封装半导体器件的方法以及PoP器件
CN106206482A (zh) * 2015-05-29 2016-12-07 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN109844934A (zh) * 2016-10-27 2019-06-04 英帆萨斯公司 用于低温接合的结构和方法
CN109727964A (zh) * 2017-10-27 2019-05-07 台湾积体电路制造股份有限公司 多芯片晶片级封装及其形成方法
US20190139911A1 (en) * 2017-11-03 2019-05-09 Dialog Semiconductor (Uk) Limited Embedded Resistor-Capacitor Film for Fan Out Wafer Level Packaging

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113555327A (zh) * 2021-06-21 2021-10-26 青岛歌尔智能传感器有限公司 封装结构及电子设备

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