CN116613111A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN116613111A
CN116613111A CN202210137472.6A CN202210137472A CN116613111A CN 116613111 A CN116613111 A CN 116613111A CN 202210137472 A CN202210137472 A CN 202210137472A CN 116613111 A CN116613111 A CN 116613111A
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CN
China
Prior art keywords
substrate structure
layer
electronic
height
electronic module
Prior art date
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Pending
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CN202210137472.6A
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English (en)
Inventor
符毅民
何祈庆
卜昭强
王愉博
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN116613111A publication Critical patent/CN116613111A/zh
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract

本发明涉及一种电子封装件及其制法，包括于一具有线路层的基板结构上配置电子模块及支撑件，以经由该支撑件分散该基板结构上的应力而消除应力集中的问题，避免该基板结构发生翘曲的情况。

Description

电子封装件及其制法
技术领域
本发明有关一种半导体装置，尤指一种可改善结构翘曲问题的电子封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。目前应用于芯片封装领域的技术，常用的封装型式如2.5D封装制程、扇出(Fan-Out)布线配合嵌埋桥接(Embedded Bridge)元件的制程(简称FO-EB)等，其中，FO-EB相对于2.5D封装制程具有低成本及材料供应商多等优势。
图1现有FO-EB的半导体封装件1的剖面示意图。该半导体封装件1包括于一具有线路层140的承载结构14上设置第一半导体芯片11(经由粘胶12)与多个导电柱13，再以一包覆层15包覆该第一半导体芯片11与该些导电柱13，之后于该包覆层15上形成一电性连接该第一半导体芯片11与该些导电柱13的线路结构10，以于该线路结构10上设置多个电性连接该线路结构10的第二半导体芯片16，并以一封装层18包覆该些第二半导体芯片16，其中，该线路层140与该线路结构10采用扇出型重布线路层(redistribution layer，简称RDL)的规格，且该第一半导体芯片11作为嵌埋于该包覆层15中的桥接元件(Bridge die)，以电性桥接两相邻的第二半导体芯片16。
现有半导体封装件1主要以该承载结构14经由多个焊球17接置于一封装基板1a上，且该些导电柱13电性连接该线路层140，并使该封装基板1a经由焊球19接置于一电路板(图略)上。
然而，现有半导体封装件1因其设于该封装基板1a上时，周围并无其它元件，致使该封装基板1a容易发生应力不均匀的情况，导致产生极大的翘曲(warpage)，进而发生植球状况不佳(例如该焊球19掉落而电性断路)等可靠度问题。
因此，如何克服上述现有技术的问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺陷，本发明提供一种电子封装件及其制法，避免基板结构发生翘曲的情况。
本发明的电子封装件，包括：基板结构，其具有线路层；电子模块，其设于该基板结构上且电性连接该线路层；以及支撑件，其设于该基板结构上并位于该电子模块周围，且电性连接该线路层。
本发明还提供一种电子封装件的制法，包括：提供一电子模块与至少一支撑件；以及将该电子模块与该至少一支撑件设于一具有线路层的基板结构上，以令该电子模块电性连接该线路层，且该至少一支撑件电性连接该线路层并位于该电子模块周围。
前述的电子封装件及其制法中，该支撑件为主动元件。
前述的电子封装件及其制法中，该电子模块包含第一封装层，且于该基板结构上形成有用以包覆该支撑件与该电子模块的第二封装层，以令该第一封装层的硬度大于该第二封装层的硬度。
前述的电子封装件及其制法中，还包括形成于该基板结构上以包覆该支撑件与该电子模块的第二封装层。例如，该支撑件与该第二封装层等高。或者，该支撑件相对于该基板结构的高度小于该第二封装层相对于该基板结构的高度。
前述的电子封装件及其制法中，该支撑件相对于该基板结构的高度等于该电子模块相对于该基板结构的高度。
前述的电子封装件及其制法中，该支撑件相对于该基板结构的高度大于该电子模块相对于该基板结构的高度。
前述的电子封装件及其制法中，该支撑件相对于该基板结构的高度小于该电子模块相对于该基板结构的高度。
前述的电子封装件及其制法中，该电子模块包含桥接元件。
由上可知，本发明的电子封装件及其制法中，主要经由该支撑件设于该基板结构上，以分散该基板结构上的应力而消除应力集中的问题，故相比于现有技术，本发明的电子封装件能避免该基板结构发生翘曲的情况。
附图说明
图1为现有半导体封装件的剖视示意图。
图2A至图2H为本发明的电子封装件的制法的剖视示意图。
图2I为图2H的另一实施例的剖视示意图。
图3A至图3C为图2H的其它不同实施例的剖视示意图。
附图标记说明
1:半导体封装件
1a:封装基板
10,20:线路结构
11:第一半导体芯片
12:粘胶
13,23:导电柱
14:承载结构
140,290:线路层
15,25:包覆层
16:第二半导体芯片
17,19,32:焊球
18:封装层
2:电子封装件
2a:电子模块
20:线路结构
200:介电层
201:线路重布层
202:电性接触垫
21:第一电子元件
21a:作用面
21b:非作用面
210:电极垫
211:保护膜
212:导电体
22:结合层
23a,23b:端面
230:开口
24:布线层
25a:第一表面
25b:第二表面
26:第二电子元件
26a,300:导电凸块
260,27a:焊锡材料
262:底胶
27:导电元件
28:第一封装层
29:基板结构
30,30a,30b:支撑件
31:第二封装层
9:承载件
90:离型层
91:金属层
92:绝缘层
H,h,h1,h2,h3:高度
S:切割路径。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2H为本发明的电子封装件2的制法的剖面示意图。
如图2A及图2B所示，于一承载件9上设置至少一第一电子元件21及形成多个导电柱23。
于本实施例中，该承载件9例如为半导体材料(如硅或玻璃)的板体，其上以例如涂布方式依序形成有一离型层90与一如钛/铜的金属层91，并使一绝缘层92形成于该金属层91上。例如，形成该绝缘层92的材料如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它介电材。
再者，该第一电子元件21为主动元件、被动元件或其二者组合，且该主动元件例如为半导体芯片，而该被动元件例如为电阻、电容及电感。于本实施例中，该第一电子元件21为半导体芯片，其具有相对的作用面21a与非作用面21b，该第一电子元件21以其非作用面21b经由一结合层22粘固于该绝缘层92上，而该作用面21a具有多个电极垫210与一如钝化材的保护膜211，其中，该多个电极垫210上结合并电性连接多个导电体212，如导电线路、焊球的圆球状、或如铜柱、焊锡凸块等金属材的柱状、或焊线机制作的钉状(stud)导电件，但不限于此，以令该导电体212形成于该保护膜211中。
另外，形成该导电柱23的材料为如铜的金属材或焊锡材，且该导电柱23延伸穿过该绝缘层92以接触该金属层91。例如，经由曝光显影方式，于该绝缘层92上形成多个外露该金属层91的开口230，以经由该金属层91从该开口230中电镀形成该些导电柱23。
如图2C所示，形成一包覆层25于该承载板9的绝缘层92上，以令该包覆层25包覆该第一电子元件21、该些导电体212与该些导电柱23，其中，该包覆层25具有相对的第一表面25a与第二表面25b，且令该保护膜211的上表面、该导电体212的端面与该导电柱23的端面23a外露于该包覆层25的第一表面25a，并令该包覆层25以其第二表面25b结合至该承载板9的绝缘层92上。
于本实施例中，该包覆层25为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dryfilm)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)。例如，该包覆层25的制程可选择液态封胶(liquid compound)、喷涂(injection)、压合(lamination)或模压(compression molding)等方式形成于该绝缘层92上。
再者，可经由整平制程，使该包覆层25的第一表面25a齐平该保护膜211的上表面、该导电柱23的端面23a与该导电体212的端面，以令该导电柱23的端面23a与该导电体212的端面外露于该包覆层25的第一表面25a。例如，该整平制程可经由研磨方式，移除该保护膜211的部分材料、该导电柱23的部分材料、该导电体212的部分材料与该包覆层25的部分材料。
如图2D所示，形成一线路结构20于该包覆层25的第一表面25a上，且令该线路结构20电性连接该多个导电柱23与该多个导电体212。
于本实施例中，该线路结构20包括至少一介电层200及设于该介电层200上的线路重布层(redistribution layer，简称RDL)201，其中，最外层的介电层200可作为防焊层，且令最外层的线路重布层201外露于该防焊层，从而供作为电性接触垫202，如微垫(micropad，俗称μ-pad)。或者，该线路结构20亦可仅包括单一介电层200及单一线路重布层201。
再者，形成该线路重布层201的材料为铜，且形成该介电层200的材料为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)等的介电材、或如绿漆、油墨等的防焊材。
如图2E所示，设置多个第二电子元件26于该线路结构20上，再以一第一封装层28包覆该多个第二电子元件26。
于本实施例中，该第二电子元件26为主动元件、被动元件或其二者组合，且该主动元件例如为半导体芯片，而该被动元件例如为电阻、电容及电感。于一实施例中，该第二电子元件26例如为图形处理器(graphics processing unit，简称GPU)、高频宽记忆体(HighBandwidth Memory，简称HBM)等半导体芯片，并无特别限制，且该第一电子元件21作为桥接元件(Bridge die)，其经由该导电体212电性连接该线路结构20，以电性桥接至少二个第二电子元件26。
再者，该第二电子元件26具有多个如铜柱的导电凸块26a，以经由多个焊锡凸块的焊锡材料260电性连接该电性接触垫202，且该第一封装层28可同时包覆该些第二电子元件26与该些导电凸块26a。于本实施例中，可形成一凸块底下金属层(Under BumpMetallurgy，简称UBM)(图略)于该电性接触垫202上，以利于结合该导电凸块26a。
另外，该第一封装层28为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dryfilm)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该线路结构20上。应可理解地，形成该第一封装层28的材料可相同或不相同该包覆层25的材料。
另外，亦可先形成底胶262于该第二电子元件26与该线路结构20的间以包覆该些导电凸块26a，再形成该第一封装层28以包覆该底胶262与该多个第二电子元件26。
如图2F所示，移除该承载件9及其上的离型层90，再移除该金属层91，并保留该绝缘层92，以外露出该导电柱23的另一端面23b。
于本实施例中，于剥离该离型层90时，经由该金属层91作为阻障的用，以避免破坏该绝缘层92，且待移除该承载件9及其上的离型层90后，再以蚀刻方式移除该金属层91，使该导电柱23的端面23b外露于该绝缘层92的表面。
如图2G所示，形成多个含有焊锡材料27a的导电元件27于该绝缘层92上，以形成FO-EB式电子模块2a，且部分该多个导电元件27电性连接该多个导电柱23。
于本实施例中，于该绝缘层92上进行布线制程，如在该绝缘层92上形成布线层24，以供结合该导电元件27。应可理解的是，当该电子模块2a的接点(IO)的数量不足(如该导电元件27的数量已无法满足产品需求)时，仍可经由RDL制程进行增层作业，以重新配置IO数量及其位置。
如图2H所示，沿如图2G所示的切割路径S进行切单制程，以获取多个电子模块2a，再将该电子模块2a经由该些导电元件27设置于一具有线路层290的基板结构29上，使该电子模块2a电性连接该线路层290，且于该基板结构29上设置至少一支撑件30，以形成电子封装件2。
于本实施例中，该支撑件30为主动元件，如半导体芯片，其经由多个导电凸块300以覆晶方式设于该基板结构29上以电性连接该基板结构29的线路层290，且可于该基板结构29上形成一第二封装层31，以包覆该支撑件30及该电子模块2a，其中，该第二封装层31为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dry film)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该基板结构29上，且令该第一封装层28的硬度大于该第二封装层31的硬度。应可理解地，形成该第一封装层28的材料可相同或不相同该第二封装层31的材料。
再者，如图2H所示，该支撑件30相对于该基板结构29的高度h1等于该第二封装层31相对于该基板结构29的高度H(或如图3A及图3C所示，该支撑件30a与该第二封装层31等高，即两者相对于该基板结构29的高度h2,H相同)，以令该支撑件30外露于该第二封装层31。亦或如图3A所示，该支撑件30相对于该基板结构29的高度h1小于该第二封装层31相对于该基板结构29的高度H。
另外，如图2H及图3A所示，该支撑件30相对于该基板结构29的高度h1等于该电子模块2a相对于该基板结构29的高度h。或如图3A、图3B及图3C所示，该支撑件30a相对于该基板结构29的高度h2大于该电子模块2a相对于该基板结构29的高度h。亦或如图3B所示，该支撑件30b相对于该基板结构29的高度h3小于该电子模块2a相对于该基板结构29的高度h。
另外，于进行切单制程前，可经由整平制程，如研磨方式，移除该第一封装层28的部分材料，使该第一封装层28的上表面齐平该第二电子元件26的上表面，如图2I所示，以令该第二电子元件26外露于该第一封装层28。进一步，可经由整平制程，移除该第二封装层31的部分材料，使该第二封装层31的上表面齐平该第二电子元件26的上表面，如图2I所示，以令该第二电子元件26外露于该第二封装层31。应可理解地，于图3A至图3C中，该第一封装层28的上表面亦可齐平该第二电子元件26的上表面，以令该第二电子元件26外露于该第一封装层28。
另外，该基板结构29下侧进行植球制程以形成多个焊球32，以于后续制程中，供该电子封装件2借其设于一电路板(图略)上。
因此，本发明的制法主要经由该支撑件30设于该基板结构29上，以分散该基板结构29上的应力而消除应力集中的问题，故相比于现有技术，本发明的电子封装件2能避免该基板结构29发生翘曲的情况，进而能避免发生植球状况不佳(例如该焊球32掉落而电性断路)等可靠度问题。
本发明亦提供一种电子封装件2，包括：具有线路层290的基板结构29、一电子模块2a以及至少一支撑件30,30a,30b。
所述的电子模块2a设于该基板结构29上且电性连接该线路层290。
所述的支撑件30,30a,30b设于该基板结构29上且电性连接该线路层290并位于该电子模块2a周围。
于一实施例中，该支撑件30,30a,30b为主动元件。
于一实施例中，该电子模块2a包含第一封装层28，且于该基板结构29上形成有用以包覆该支撑件30,30a,30b与该电子模块2a的第二封装层31，以令该第一封装层28的硬度大于该第二封装层31的硬度。
于一实施例中，所述的电子封装件2还包括形成于该基板结构29上以包覆该支撑件30,30a,30b与该电子模块2a的第二封装层31。例如，该支撑件30,30a与该第二封装层31为等高。或者，该支撑件30相对于该基板结构29的高度h1小于该第二封装层31相对于该基板结构29的高度H。
于一实施例中，该支撑件30相对于该基板结构29的高度h1等于(如图2H及图3A所示)该电子模块2a相对于该基板结构29的高度h。
于一实施例中，该支撑件30a相对于该基板结构29的高度h2大于(如图3A、图3B及图3C所示)该电子模块2a相对于该基板结构29的高度h。
于一实施例中，该支撑件30b相对于该基板结构29的高度h3小于(如图3B所示)该电子模块2a相对于该基板结构29的高度h。
于一实施例中，该电子模块2a包含桥接元件(第一电子元件21)，以及多个通过该桥接元件而相互电性连接的第二电子元件26。
综上所述，本发明的电子封装件及其制法，经由该支撑件的配置，以分散该基板结构上的应力而消除应力集中的问题，故相比于现有技术，本发明的电子封装件能避免该基板结构发生翘曲的情况。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (20)

1.一种电子封装件，包括：
基板结构，其具有线路层；
电子模块，其设于该基板结构上且电性连接该线路层；以及
支撑件，其设于该基板结构上并位于该电子模块周围，且电性连接该线路层。
2.如权利要求1所述的电子封装件，其中，该支撑件为主动元件。
3.如权利要求1所述的电子封装件，其中，该电子模块包含第一封装层，且于该基板结构上形成有用以包覆该支撑件与该电子模块的第二封装层，且令该第一封装层的硬度大于该第二封装层的硬度。
4.如权利要求1所述的电子封装件，还包括形成于该基板结构上以包覆该支撑件与该电子模块的第二封装层。
5.如权利要求4所述的电子封装件，其中，该支撑件与该第二封装层为等高。
6.如权利要求4所述的电子封装件，其中，该支撑件相对于该基板结构的高度小于该第二封装层相对于该基板结构的高度。
7.如权利要求1所述的电子封装件，其中，该支撑件相对于该基板结构的高度等于该电子模块相对于该基板结构的高度。
8.如权利要求1所述的电子封装件，其中，该支撑件相对于该基板结构的高度大于该电子模块相对于该基板结构的高度。
9.如权利要求1所述的电子封装件，其中，该支撑件相对于该基板结构的高度小于该电子模块相对于该基板结构的高度。
10.如权利要求1所述的电子封装件，其中，该电子模块包含桥接元件，以及通过该桥接元件相互电性连接的多个电子元件。
11.一种电子封装件的制法，包括：
提供一电子模块与至少一支撑件；以及
将该电子模块与该至少一支撑件设于一具有线路层的基板结构上，以令该电子模块电性连接该线路层，且该至少一支撑件电性连接该线路层并位于该电子模块周围。
12.如权利要求11所述的电子封装件的制法，其中，该至少一支撑件为主动元件。
13.如权利要求11所述的电子封装件的制法，其中，该电子模块包含第一封装层，且于该基板结构上形成有用以包覆该至少一支撑件与该电子模块的第二封装层，以令该第一封装层的硬度大于该第二封装层的硬度。
14.如权利要求11所述的电子封装件的制法，还包括于该基板结构上形成用以包覆该至少一支撑件与该电子模块的第二封装层。
15.如权利要求14所述的电子封装件的制法，其中，该至少一支撑件与该第二封装层为等高。
16.如权利要求14所述的电子封装件的制法，其中，该至少一支撑件相对于该基板结构的高度小于该第二封装层相对于该基板结构的高度。
17.如权利要求11所述的电子封装件的制法，其中，该至少一支撑件相对于该基板结构的高度等于该电子模块相对于该基板结构的高度。
18.如权利要求11所述的电子封装件的制法，其中，该至少一支撑件相对于该基板结构的高度大于该电子模块相对于该基板结构的高度。
19.如权利要求11所述的电子封装件的制法，其中，该至少一支撑件相对于该基板结构的高度小于该电子模块相对于该基板结构的高度。
20.如权利要求11所述的电子封装件的制法，其中，该电子模块包含桥接元件，以及通过该桥接元件相互电性连接的多个电子元件。
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