TWI548042B - 電子系統及其核心模組 - Google Patents

電子系統及其核心模組 Download PDF

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TWI548042B
TWI548042B TW102114460A TW102114460A TWI548042B TW I548042 B TWI548042 B TW I548042B TW 102114460 A TW102114460 A TW 102114460A TW 102114460 A TW102114460 A TW 102114460A TW I548042 B TWI548042 B TW I548042B
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component
package substrate
electronic system
core module
substrate
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TW102114460A
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TW201442160A (zh
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楊之光
張振義
古永延
薛淦浩
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巨擘科技股份有限公司
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Priority to TW102114460A priority Critical patent/TWI548042B/zh
Priority to CN201310205713.7A priority patent/CN104124223B/zh
Priority to US14/162,130 priority patent/US9379089B2/en
Priority to EP20140155488 priority patent/EP2797113A1/en
Priority to KR1020140045232A priority patent/KR20140127156A/ko
Priority to JP2014087120A priority patent/JP2014216650A/ja
Publication of TW201442160A publication Critical patent/TW201442160A/zh
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Publication of TWI548042B publication Critical patent/TWI548042B/zh

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Description

電子系統及其核心模組
本發明係關於一種電子系統及其核心模組；特別關於一種多元件子母封裝之電子系統及其核心模組。
當前多元件電子系統所採用之堆疊封裝已知技術為因應高積集度以及電子產品微型化且多功能之封裝要求，當前堆疊封裝正蓬勃發展出多種技術。如第1圖所示之堆疊式封裝層疊(Package on Package)技術抑或SiP(System in Package)封裝技術。此已知技術例如具有第一元件A、第二元件B及第三元件C整合於單一封裝模組中。第一元件A首先封裝於第一封裝基板100且以第一模封材料102進行模封后藉由焊錫與基板D連接。並且，為能於設置於上方之第二元件B連接，會於對應位置形成複數個第一通孔104，並填入導電性金屬材料。第二元件B首先封裝於第二封裝基板200且以第二模封材料202進行模封后藉由焊錫與第一元件A連接。並且，為能於設置於上方之第三元件C連接，會於對應位置形成複數個第二通孔204，並填入導電性金屬材料。第三元件C首先封裝於第三封裝基板300且以第三模封材料302進行模封后藉由焊錫與第二元件B連接。此一封裝模組。此外，第1圖所示之堆疊式封裝層疊雖是採用第一通孔104及第二通孔204來實現元件間之電性連接，但亦有採用打線技術之方式實現電性連接。
然而，此類堆疊式封裝層疊PoP技術，存在諸多缺點。由於每一個元件皆需單獨先行模封，因此當堆疊時， 必然限制了元件間週期距的縮小，因此存在高度無法降低的必然性缺陷，也限制了焊錫與焊墊的大小無法更進一步縮小。再者，由於堆疊式封裝層疊後的電性連接複雜，封裝後的良率僅能倚賴各元件堆疊前的測試結果，亦有可能因無法再實施堆疊後之後測試以確保可靠度，因此必需承擔封裝的失敗風險。並且，即便如前述以第一通孔104、第二通孔204或者打線技術來實現元件間之電性連接，皆增加了封裝電性連接的製程多種類及因製造過程繁瑣而必然導致整體成本增加。
因此，確有發展一種可解決前開封裝結構缺點之電子系統及其核心模組為本發明之目的。
本發明之目的在於提供一種核心模組，包括：一封裝基板，具有複數個焊墊；一第一元件，藉由複數個第一接合件與對應該第一元件之該封裝基板的該些焊墊接合，且以一第一模封材料模封該第一元件；一第二元件，藉由複數個第二接合件與對應該第二元件之該封裝基板的該些焊墊接合；以及一第三元件，藉由複數個第三接合件與對應該第三元件之該封裝基板的該些焊墊接合，其中該第一元件、該第二元件及該第三元件之間均透過該封裝基板形成電性連接且以一母模封材料模封該第一元件、該第二元件及該第三元件。
本發明之核心模組可進一步包括至少一第四元件，藉由複數個第四接合件與對應該至少一第四元件之該封裝基板的該些焊墊接合，透過該封裝基板，與該第一元件、該第二元件及該第三元件之間形成電性連接且該母模封材料亦模封該至少一第四元件。
本發明核心模組之實施例中，該第一元件可為一記憶元件。該記憶元件包括至少一非揮發性記憶體。該第二元件可為一邏輯元件。該第三元件可為一電源管理元件。該封裝基板可為一具有多層內連線之薄膜基板。
本發明之目的在於提供一種電子系統，包括：一封裝基板，具有複數個焊墊；一第一元件，藉由複數個第一接合件與對應該第一元件之該封裝基板的該些焊墊接合，且以一第一模封材料模封該第一元件；一第二元件，藉由複數個第二接合件與對應該第二元件之該封裝基板的該些焊墊接合；一第三元件，藉由複數個第三接合件與對應該第三元件之該封裝基板的該些焊墊接合；以及一電路基板，具有複數個電路基板焊墊，藉由複數個電路基板焊錫與該封裝基板接合，其中該第一元件、該第二元件及該第三元件之間均透過該封裝基板形成電性連接且以一母模封材料模封該第一元件、該第二元件及該第三元件。
本發明之電子系統可進一步包括至少一周邊元件，該電路基板藉由該些電路基板焊錫與該至少一周邊元件接合。
本發明電子系統之實施例中，該至少一周邊元件係選自GPS模組、WIFI模組、GSM模組、觸控模組音源影像模組、顯示模組、MEMS磁力計、FM模組、USB host控制器、GPIO介面、直流電源、開關、電池中之至少一者。
本發明利用子母封裝之概念，能解決前開堆疊式封裝層疊PoP技術中各元件皆需先行封裝而徒增製造成本及製程繁瑣的缺點，各元件可視其所需，先行封裝與否並不再受限制，更提供了元件封裝的多樣結構，滿足不同產品設計的功能需求，也明顯地降低了前開堆疊式封裝層疊PoP技術於完成單一封裝模組後測試之複雜性而無法實施測試的可能。並且，本發明提出之核心模組，將所有元件的電性連接皆透過單一封裝基板實現，因此可更進一步簡化所有元件元 件的封裝技術，例如，依據本發明所有元件、第四元件之封裝均可採用表面貼裝技術(Surface Mount Technology)，而大幅提高封裝製程之效率。
1‧‧‧封裝基板
2‧‧‧焊墊
3‧‧‧電路基板
4‧‧‧電路基板焊墊
5‧‧‧電路基板焊錫
10‧‧‧第一元件
12‧‧‧第一模封材料
14‧‧‧第一封裝基板
16‧‧‧第一接合件
20‧‧‧第二元件
26‧‧‧第二接合件
30‧‧‧第三元件
32‧‧‧第三模封材料
36‧‧‧第三接合件
40‧‧‧第四元件
46‧‧‧第四接合件
50‧‧‧母模封材料
100‧‧‧第一封裝基板
102‧‧‧第一模封材料
104‧‧‧第一通孔
200‧‧‧第二封裝基板
202‧‧‧第二模封材料
204‧‧‧第二通孔
300‧‧‧第三封裝基板
302‧‧‧第三模封材料
A‧‧‧第一元件
B‧‧‧第二元件
C‧‧‧第二元件
D‧‧‧基板
第1圖係習知技術的多元件堆疊之示意圖。
第2圖係本發明的電子系統及其核心模組之示意圖。
第3圖係本發明的電子系統及其核心模組之功能方塊圖。
請參閱本發明第2圖。第2圖係本發明的電子系統及其核心模組之示意圖。本發明之核心模組包括一封裝基板1、一第一元件10、一第二元件20以及一第三元件30。封裝基板1具有複數個焊墊2，可為一薄膜基板。並且如第2圖所示，其可為一多層內連線基板。作為封裝基板1之多層內連線基板，其總厚度小於100μm；單一層之厚度小於20μm，且更可小於10μm；最小線寬於30μm，且更可小於15μm；該些焊墊之週期距(pitch)小於80μm，且更可小於50μm。週期距(pitch)之定義係為兩相鄰焊墊之幾何中心點或幾何中心線間之距離。其多層內連線係用以提供第一元件10、第二元件20以及第三元件30等間之電性連接功能。於本發明中，係以第一模封材料12預先進行模封第一元件10。第一元件10可先已封裝於第一封裝基板14上，並且藉由複數個第一接合件16與對應第一元件10之封裝基板1的複數個焊墊2接合。如圖所示，第二元件20可與第一元件10以堆疊之方式，即第一元件10相對於封裝基板1位於第二元件20之上方，藉由複數個第二接合件26與對應第二元件20之封裝基板1的複數個焊墊2接合。於本發明之實施例中，第二元件20可為一邏輯元件，例如可為一處理器。第一元件10可為一記憶元件。 所述記憶元件包括至少一非揮發性記憶體，例如一NAND快閃記憶體或一NOR快閃記憶體。
於本發明中，係以第三模封材料32預先模封第三元件30。第三元件30藉由複數個第三接合件36與對應第三元件30之封裝基板1的複數個焊墊2接合。於本發明之實施例中，第三元件30可為一電源管理元件。並且，本發明之核心模組可進一步包括至少一第四元件40，例如：應用本發明電子產品之電路設計所需之至少一電容或電阻等被動元件，或者為系統設計所需之其他類型元件。同樣地，至少一第四元件40亦藉由複數個第四接合件46與對應至少一第四元件40之封裝基板1的複數個焊墊2接合。第一接合件16、第二接合件26、第三接合件36及第四接合件46例如可為焊錫、凸塊或錫球。透過與封裝基板1的接合，實現與第一元件10、第二元件20以及第三元件30間之電性連接。是以，本發明中，第一元件10、第二元件20、第三元件30以及至少一第四元件40均透過封裝基板1形成電性連接，並且以母模封材料50以單一個製程，同時模封第一元件10、第二元件20、第三元件30以及至少一第四元件40，形成單一模組化(monolithic)之單一個封裝體，以作為一電子產品之核心模組。
如本發明第2圖所示，第一元件10、第二元件20、第三元件30以及至少一第四元件40各別焊錫與焊墊之接點均透過一高密度載板，即封裝基板1互連後，再將各元件封埋於母模封材料50之中。並且，如第2圖中所示，為設計上不同之應用，於第一元件10之正下方與第一封裝基板14間之間隙，或者於已以第一封裝基板14封裝之第一元件10、第二元件20、第三元件30以及至少一第四元件40之正下方與封裝基板1間之間隙中填入保護膠材(第2圖中之虛線表示)。或者可於第二元件20下方先填入一種保護膠材，再於已以第一封裝基板14封裝之第一元件10下方再填入相同或他種保護膠材。前述針對各元件保護膠材之選用係可依間隙 內之特性以及保護膠材本身之吸水性、熱傳係數、熱膨脹係數、玻璃轉化點而可以有不同選擇，可使用同一種保護膠材，亦可以採用不同保護膠材，甚至亦可使用母模封材料50一次灌入所有間隙中亦為本發明可採用之選項。
並且，本發明電子系統及其核心模組之單一模組化(monolithic)於製程上具有之技術優點，即第一元件10、第二元件20、第三元件30以及至少一第四元件40分別透過第一接合件16、第二接合件26、第三接合件36以及第四接合件46與封裝基板1上相對應之焊墊接合，可僅需要一次回焊前述設置於同一平面上之第一接合件16、第二接合件26、第三接合件36以及第四接合件46與封裝基板1上對應之焊墊，然習知技術中一般SiP(System in Package)封裝技術中之SiP模組並非單一模組化(monolithic)，亦即個別元件係以個別之回焊製程將元件與作為載板之晶圓進行接著。因此，進行第二次或之後多次回焊時，晶圓上方已接著之元件即有可能發生脫焊之情形。
現今可行之方法例如：第一次回焊時使用較高溫之接著焊料(焊錫)，第二次回焊或之後多次回焊時，焊接點使用較低溫的焊料(焊錫)。然此類解決方案存在諸多限制。首先，較高溫之接著焊料及其較高溫之回焊製程對元件產生之熱衝擊大，會導致元件之可靠度降低及使用壽命縮短。並且，若不使用較高溫之接著焊料進行第一次或較先之回焊製程，則進行第二次或之後多次回焊時，已接著之元件即有可能發生脫焊之情形。甚至之後多次回焊時，高溫下導致封裝基板1及電路基板3發生熱翹曲，亦會導致焊錫與焊墊之接點脫焊或空焊。
請參閱本發明第2圖及第3圖。第3圖係本發明的電子系統及其核心模組之功能方塊圖。如第2圖及第3圖所示，本發明之電子系統包括一封裝基板1、一第一元件10、一第二元件20、一第三元件30以及一電路基板3。電路 基板3具有複數個電路基板焊墊4。電路基板3藉由複數個電路基板焊錫5與封裝基板1接合。本發明之電子系統可更進一步包括至少一周邊元件。電路基板3亦藉由電路基板焊錫5與該至少一周邊元件接合。
本發明中第二元件20可為一邏輯元件，例如：一處理器(Processor)或一可邏輯化元件(Programmable IC)。由於運作功率較大，在本發明實施例中，例如可採裸晶(bare die)封裝，使其熱阻小。並且如第2圖所示配置接近封裝基板1，第二接合件26可採用微凸塊(micro bump，尺寸如小於50μm，較佳為20~50μm；凸塊高度如小於50μm，較佳為10~20μm)，例如柱形凸塊(stud bump)。則向下熱阻可有效地降低，使其發熱更有效率地傳導至封裝基板1，有利於本發明的電子系統及其核心模組整體之系統效能。
第一元件10可為一記憶元件。所述記憶元件包括至少一非揮發性記憶體(NAND Flash memory)以及同步動態隨機存取存儲器(SDRAM)，或者動態記憶體(DRAM)等及其組合。視本發明電子系統及其核心模組最終系統設計所需而有所不同。如第2圖所示，設置於第二元件20上方使其配置空間較大，配置也較有彈性，可視系統設計所需而更換不同之模組組合，而不影響第二元件20之製程以及空間配置。
第三元件30可為一電源管理元件(Power management IC)。第二元件20與第三元件30之間更耦接至少一電容42，以供電源管理元件能因實際所需對處理器(Processor)或可邏輯化元件(Programmable IC)提供電源。而至少一第四元件40除可為前述電容或電阻等被動元件外，亦可包括通訊元件，數位類比轉換元件(AD convertor)，時脈振盪器…等已封裝完成之元件，亦可為圖示未模封之裸晶元件、或者晶圓級晶片尺寸封裝(wafer level CSP)之元件，使本發明電子系統及其核心模組之整體積集度更高，更微小化。
再者，如第2圖及第3圖所示，電源管理元件 可藉由電路基板3及電路基板焊錫5，對外耦接直流電源、開關、電池等或其他所需元件。處理器(Processor)或可邏輯化元件(Programmable IC)可藉由電路基板3及電路基板焊錫5，對外耦接GPS模組、WIFI模組、GSM模組、觸控模組、音源影像模組、顯示模組、MEMS磁力計、FM模組、USB主控制器(USB host controller)、通用輸入輸出介面(GPIO)等等。利用本發明，由於作為封裝基板1之多層內連線基板係已完成核心模組中所有設計上大部分所需之電性連接，加上本發明以子母封裝形成單一封裝體之核心模組的技術特性，僅需低密度佈線之電路基板3，即能實現本發明電子系統所需之各種功能。
如前所述，由於本發明之電子系統及其核心模組中，第一元件10、第二元件20、第三元件30以及至少一第四元件40均透過封裝基板1形成電性連接，因此第一元件10、第二元件20、第三元件30以及至少一第四元件40之封裝可採用表面貼裝技術(Surface Mount Technology)，以單一回焊製程即實現封裝完成，而使封裝技術使用單純化，當然本發明亦非僅限於以單一回焊製程實現封裝完成。並且，第一元件10、第二元件20、第三元件30可不需要各別先行模封，而是視其需先行模封與否，且本發明於回焊前，或以母模封材料50對所有元件進行模封前，亦更可進行測試步驟，若有電性缺陷可於以母模封材料50進行模封即行修正，不僅大幅提高封裝製程之效率，更能提高最終整體良率避免封裝缺陷，無法回工而導致元件的報廢耗損，有效降低製造成本。
再者，如前所述由於本發明係以母模封材料50形成單一封裝體之核心模組，並且具備高積集度特性，作為封裝基板1之多層內連線基板係已完成核心模組中所有設計上大部分所需之電性連接，加上本發明子母封裝之技術特性，於製作電子系統時所採用之電路基板，僅需低密度佈線之電路板(PCB)即可。而無需如現今技術多必需採用高密度電 路板(HDI PCB)。高密度電路板一般而言其結構至少包括6-8層，同時亦必需配合採用雷射鑽孔形成其中之導通孔結構。而利用本發明，所需低密度佈線之電路基板1的層數僅需4層以下，且其僅需採用機械鑽孔形成其中之導通孔結構即能實現前述與該至少一周邊元件之接合。而相較於需採用高密度電路板(HDI PCB)作為電路基板之現有技術，藉由本發明子母封裝概念，形成單一封裝體之核心模組，所採用之低密度佈線之電路板(PCB)不僅成本大幅降低，製造更有效率，可靠度能更進一步有效地提升。
總之，本發明子母封裝之概念，解決前開堆疊式封裝層疊PoP技術中各元件皆需先行封裝而徒增製造成本及製程繁瑣的缺點。提供了元件封裝的多樣結構，滿足不同產品設計的功能需求，也降低了前開堆疊式封裝層疊技術於完成封裝模組後之測試複雜性。且各元件可視其所需，先行封裝與否並不再受限制，因本發明提出之電子系統及其核心模組所具備子母封裝之特性，最終會實施完整母模封材料之封裝。再者，所有元件的電性連接皆透過單一封裝基板實現，能對所有元件、第四元件之封裝均採用表面貼裝技術(Surface Mount Technology)而以一次回焊即完成電性連接。且在回焊前能進行測試即行修正，大幅提高封裝製程之效率。
雖然本發明已就較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之變更和潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
1‧‧‧封裝基板
2‧‧‧焊墊
3‧‧‧電路基板
4‧‧‧電路基板焊墊
5‧‧‧電路基板焊錫
10‧‧‧第一元件
12‧‧‧第一模封材料
14‧‧‧第一封裝基板
16‧‧‧第一接合件
20‧‧‧第二元件
26‧‧‧第二接合件
30‧‧‧第三元件
32‧‧‧第三模封材料
36‧‧‧第三接合件
40‧‧‧第四元件
46‧‧‧第四接合件
50‧‧‧母模封材料

Claims (46)

  1. 一種核心模組，包括：一封裝基板，具有複數個焊墊；一第一元件，封裝在一第一封裝基板上並藉由複數個第一接合件與對應該第一元件之該封裝基板的該些焊墊接合，接合至該封裝基板的該些第一接合件位於該第一封裝基板的下表面；一第二元件，藉由複數個第二接合件與對應該第二元件之該封裝基板的該些焊墊接合，接合至該封裝基板的該些第二接合件位於該第二元件的下表面；以及一第三元件，藉由複數個第三接合件與對應該第三元件之該封裝基板的該些焊墊接合，接合至該封裝基板的該些第三接合件位於該第三元件的下表面，其中該第一元件相對於該封裝基板位於該第二元件之上方，該第一元件、該第二元件及該第三元件之間均透過該封裝基板形成電性連接且以一母模封材料模封該第一元件、該第二元件及該第三元件，封裝在該第一封裝基板之該第一元件與該封裝基板間之間隙中填入一保護膠材，該保護膠材包覆該些第一接合件及該第二元件，該些第一接合件、該些第二接合件及該些第三接合件設置於該封裝基板的同一平面上。
  2. 根據申請專利範圍第1項之核心模組，其中該第一元件係以一第一模封材料進行模封。
  3. 根據申請專利範圍第1項之核心模組，其中該第一接合件、該第二接合件或該第三接合件係至少選自焊錫、凸塊或錫球之中之一種態樣。
  4. 根據申請專利範圍第1項之核心模組，進一步包括至少一第四元件藉由複數個第四接合件與對應該至少一第四元件之該封裝基板的該些焊墊接合，透過該封裝基板，與該第一元件、該第二元件及該第三元件之間形成電性連接且該母模封材料亦模封該至少一第四元件。
  5. 根據申請專利範圍第4項之核心模組，其中該第四接合件係至少選自焊錫、凸塊或錫球之中之一種態樣。。
  6. 根據申請專利範圍第1項之核心模組，其中該第二元件係為一邏輯元件。
  7. 根據申請專利範圍第6項之核心模組，其中該邏輯元件係為一處理器。
  8. 根據申請專利範圍第1項之核心模組，其中該第一元件係為一記憶元件。
  9. 根據申請專利範圍第8項之核心模組，其中該記憶元件包括至少一非揮發性記憶體。
  10. 根據申請專利範圍第8項之核心模組，其中該記憶元件包括一NAND快閃記憶體。
  11. 根據申請專利範圍第8項之核心模組，其中該記憶元件包括一NOR快閃記憶體。
  12. 根據申請專利範圍第1項之核心模組，其中該第三元件係為一電源管理元件。
  13. 根據申請專利範圍第1項之核心模組，其中該封裝基板係為一薄膜基板。
  14. 根據申請專利範圍第13項之核心模組，其中該薄膜基板係為一多層內連線基板。
  15. 根據申請專利範圍第1項之核心模組，其中該封裝基板之總厚度小於100μm。
  16. 根據申請專利範圍第1項之核心模組，其中該封裝基板中單一層之厚度小於20μm。
  17. 根據申請專利範圍第1項之核心模組，其中該封裝基板中之最小線寬小於30μm。
  18. 根據申請專利範圍第1項之核心模組，其中該些焊墊之週期距(pitch)小於80μm。
  19. 根據申請專利範圍第1項之核心模組，其中該第一元件、該第二元件及該第三元件係以單一回焊使該些第一接合件、該些第二接合件、及該些第三接合件與對應之該些焊墊接合。
  20. 根據申請專利範圍第1項之核心模組，其中該第二元件係為一裸晶元件。
  21. 根據申請專利範圍第20項之核心模組，其中該些第二接合件為複數個微凸塊。
  22. 一種電子系統，包括：一封裝基板，具有複數個焊墊；一第一元件，封裝在一第一封裝基板上並藉由複數個第一接合件與對應該第一元件之該封裝基板的該些焊墊接 合，接合至該封裝基板的該些第一接合件位於該第一封裝基板的下表面；一第二元件，藉由複數個第二接合件與對應該第二元件之該封裝基板的該些焊墊接合，接合至該封裝基板的該些第二接合件位於該第二元件的下表面；一第三元件，藉由複數個第三接合件與對應該第三元件之該封裝基板的該些焊墊接合，接合至該封裝基板的該些第三接合件位於該第三元件的下表面；以及一電路基板，具有複數個電路基板焊墊，藉由複數個電路基板焊錫與該封裝基板接合，其中該第一元件相對於該封裝基板位於該第二元件之上方，該第一元件、該第二元件及該第三元件之間均透過該封裝基板形成電性連接且以一母模封材料模封該第一元件、該第二元件及該第三元件，封裝在該第一封裝基板之該第一元件與該封裝基板間之間隙中填入一保護膠材，該保護膠材包覆該些第一接合件及該第二元件，該些第一接合件、該些第二接合件及該些第三接合件設置於該封裝基板的同一平面上。
  23. 根據申請專利範圍第22項之電子系統，其中該第一元件係以一第一模封材料進行模封。
  24. 根據申請專利範圍第22項之電子系統，其中該第一接合件、該第二接合件或該第三接合件係至少選自焊錫、凸塊或錫球之中之一種態樣。。
  25. 根據申請專利範圍第22項之電子系統，進一步包括至少一第四元件藉由複數個第四接合件與對應該至少一第四元件之該封裝基板的該些焊墊接合，透過該封裝基板，與該第一元件、該第二元件及該第三元件之間形成電性連接且該母模封材料亦模封該至少一第四元件。
  26. 根據申請專利範圍第25項之核心模組，其中該第四接合件係至少選自焊錫、凸塊或錫球之中之一種態樣。。
  27. 根據申請專利範圍第22項之電子系統，其中該第二元件係為一邏輯元件。
  28. 根據申請專利範圍第27項之電子系統，其中該邏輯元件係為一處理器。
  29. 根據申請專利範圍第22項之電子系統，其中該第一元件係為一記憶元件。
  30. 根據申請專利範圍第29項之電子系統，其中該記憶元件包括至少一非揮發性記憶體。
  31. 根據申請專利範圍第29項之電子系統，其中該記憶元件包括一NAND快閃記憶體。
  32. 根據申請專利範圍第29項之電子系統，其中該記憶元件包括一NOR快閃記憶體。
  33. 根據申請專利範圍第22項之電子系統，其中該第三元件係為一電源管理元件。
  34. 根據申請專利範圍第22項之電子系統，其中該封裝基板係為一薄膜基板。
  35. 根據申請專利範圍第34項之電子系統，其中該薄膜基板係為一多層內連線基板。
  36. 根據申請專利範圍第22項之電子系統，其中該封裝基板之總厚度小於100μm。
  37. 根據申請專利範圍第22項之電子系統，其中該封裝基板中單一層之厚度小於20μm。
  38. 根據申請專利範圍第22項之電子系統，其中該封裝基板中之最小線寬於30μm。
  39. 根據申請專利範圍第22項之電子系統，其中該些焊墊之週期距小於80μm。
  40. 根據申請專利範圍第22項之電子系統，其中該第一元件、該第二元件及該第三元件係以單一回焊使該些第一接合件、該些第二接合件、及該些第三接合件與對應之該些焊墊接合。
  41. 根據申請專利範圍第22項之核心模組，其中該第二元件係為一裸晶元件。
  42. 根據申請專利範圍第41項之核心模組，其中該些第二接合件為複數個微凸塊。
  43. 根據申請專利範圍第22項之電子系統，進一步包括至少一周邊元件，該電路基板藉由該些電路基板焊錫與該至少一周邊元件接合。
  44. 根據申請專利範圍第43項之電子系統，其中該至少一周邊元件係選自GPS模組、WIFI模組、GSM模組、觸控模組音源影像模組、顯示模組、MEMS磁力計、FM模組、USB host控制器、GPIO介面、直流電源、開關、電池中之至少一者。
  45. 根據申請專利範圍第22項之電子系統，其中該電路基板之層數小於四層。
  46. 根據申請專利範圍第22項之電子系統，其中該電路基板中之導通孔係以機械鑽孔形成。
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US20140312490A1 (en) 2014-10-23
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JP2014216650A (ja) 2014-11-17

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