TWI599009B - 半導體晶片封裝元件，半導體模組，半導體封裝元件之製造方法及半導體模組之製造方法 - Google Patents

半導體晶片封裝元件，半導體模組，半導體封裝元件之製造方法及半導體模組之製造方法 Download PDF

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TWI599009B
TWI599009B TW100136572A TW100136572A TWI599009B TW I599009 B TWI599009 B TW I599009B TW 100136572 A TW100136572 A TW 100136572A TW 100136572 A TW100136572 A TW 100136572A TW I599009 B TWI599009 B TW I599009B
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disposed
semiconductor
semiconductor wafer
insulating frame
chip package
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權容台
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納沛斯公司
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Description

半導體晶片封裝元件，半導體模組，半導體封裝元件之製 造方法及半導體模組之製造方法
本發明係有關一種半導體晶片封裝元件，半導體模組，以及其方法，尤其是以複數個半導體晶片封裝元件垂直堆疊成一半導體模組，以及一半導體模組的製造方法。
半導體晶片在經過一封裝過程後，設置於一外部基板或一電路裝置。半導體晶片封裝元件設置於一基板上，如印刷電路板(PCB)等，連同其他半導體元件組成一具有特定功用的半導體模組。
當複數個半導體晶片封裝元件設置於一基板時，基板面積因此增加，還需要複數個額外的電力配線，以進行介於該些半導體晶片封裝元件及其他半導體元件之間之信號傳輸。所以，半導體晶片封裝元件的製造過程相當複雜，由於半導體模組的尺寸進一步的增加，信號傳輸通道也跟著增加，所以要高速執行就非易事了。
圖1為一記憶模組10之上視圖，尤指一塊單一半導體晶片，該記憶晶片設置如習知技術。複數個記憶晶片或記憶體封裝元件20以一事先設定好的距離，等距地設置於一PCB基板12之上，而一電子抹除式可複寫唯讀記憶體(EEPROM)30或是一被動元件42，例如電容器，以及一電阻器44也設置於該基板12，複數個連接接頭50從外部連結到該基板12之長邊。
該記憶體模組10係以設置複數個記憶體晶片20和其他元件於該PCB基板12來完成，以水平方向來設置，並透過電力或磁力連接記憶體晶片20，其他元件則以其他方法來固定，例如銲錫。單一之半導體記憶體封裝元件20以事先設定好的距離，水平方向等距設置於該PCB基板20，該PCB基板12之面積因此增加，該記憶體模組10之尺寸跟重量也跟著增加。此外，為了執行在每一元件及該些以水平方向設置之記憶體晶片20之間的高性能之信號傳輸，該PCB基板12需要作成一金屬佈線的複數線路板(6-8層)。所以，製造半導體晶片封裝元件的過程複雜，價格也相對增加。
隨著可攜式電子裝置的發展，以及電子產品的尺寸縮小，各式半導體系統，包含了半導體記憶模組，需滿足體積小，重量又輕的需求。
此外，在佈線設計個別元件的效果時，還需要有所提升，以便執行高速的信號傳輸。
本發明提供了一種以垂直方向堆疊晶片之一半導體晶片封裝元件，以及其製造方法。
本發明也提供了一半導體模組，不但縮小了尺寸，還改善了信號處理性能，及其製造方法。
本發明之主要目的，係提供了一半導體晶片封裝元件，其包含：一絕緣框架，該框架中間有一開口部，該開口部周圍有一沖孔；一半導體晶片，設置於該開口部中；一傳導部，設置於該沖孔內；一內部絕緣層，設置於該絕緣框架之底面與該半導體晶片之底面，以便接觸該傳導部之底面；以及一內部信號圖像佈線，設置於該內部絕緣層上，電性連接了該半導體晶片及該傳導部。
本發明之次一目的，係提供了一半導體模組，其包含：一第一半導體晶片封裝元件，其包含一第一絕緣框架，該第一絕緣框架更進一步包含：一第一開口部，設置於該第一絕緣框架之中間，一第一沖孔，設置於該第一開口部之周圍；一第一半導體晶片，設置於該第一開口部中；一第一傳導部，設置於該第一沖孔內；一第一內部絕緣層，設置於該第一絕緣框架之底面與該第一半導體晶片之底面，以便接觸該第一傳導部之底面；以及一第一內部信號圖像佈線，設置於該第一內部絕緣層上，電性連接了該第一半導體晶片及該第一傳導部；一第二半導體晶片封裝元件，其包含一第二絕緣框架，該第二絕緣框架更進一步包含：一第二開口部，設置於該第二絕緣框架之中間，一第二沖孔，設置於該第二開口部之周圍；一第二半導體晶片，設置於該第二開口部中；一第二傳導部，設置於該第二沖孔內；一第二內部絕緣層，設置於該第二絕緣框架之底面與該第二半導體晶片之底面，以便接觸該第二傳導部之底面；以及一第二內部信號圖像佈線，設置於該第二內部絕緣層上，電性連接了該第二半導體晶片及該第二傳導部，其中，第一半導體晶片封裝元件與第二半導體晶片封裝元件以垂直方向堆疊且電性連接。
本發明之另一目的，係提供一種製造半導體晶片封裝元件之方法，其包含：準備一絕緣框架，該絕緣框架更進一步包含：一開口部，設置於該絕緣框架之中間，一沖孔，設置於該開口部之周圍；在該沖孔內安排一傳導部；設置一半導體晶片於該開口部，而該絕緣框架設置於一支承件；設置一塑模層於該絕緣框架之頂面及該半導體晶片之頂面；從該絕緣框架移除該支承件，以及設置一內部絕緣層於該絕緣框架之底層和該半導體晶片底層；以及設置一內部信號圖像佈線於該內部絕緣層，電性連接該半導體晶片及該傳導部。
本發明之又一目的，係提供一種製造半導體模組之方法，其包含：準備一第一絕緣框架，該第一絕緣框架更進一步包含：一第一開口部，設置於該第一絕緣框架之中間，一第一沖孔，設置於該第一開口部之周圍；在該第一沖孔內安排一第一傳導部；設置一第一半導體晶片於該第一開口部，而該第一絕緣框架設置於一第一支承件；設置一第一塑模層於該第一絕緣框架之頂面及該第一半導體晶片之頂面；從該第一絕緣框架移除該第一支承件，以及設置一第一內部絕緣層於該第一絕緣框架之底層和該第一半導體晶片底層；以及設置一第一內部信號圖像佈線於該第一內部絕緣層，電性連接該第一半導體晶片及該第一傳導部；準備一第二絕緣框架，該第二絕緣框架更進一步包含：一第二開口部，設置於該第二絕緣框架之中間，一第二沖孔，設置於該第二開口部之周圍；在該第二沖孔內安排一第二傳導部；設置一第二半導體晶片於該第二開口部，而該第二絕緣框架設置於一第二支承件；設置一第二塑模層於該第二絕緣框架之頂面及該第二半導體晶片之頂面；從該第二絕緣框架移除該第二支承件，以及設置一第二內部絕緣層於該第二絕緣框架之底層和該第二半導體晶片底層；以及設置一第二內部信號圖像佈線於該第二內部絕緣層，電性連接該第二 半導體晶片及該第二傳導部；以垂直方向堆疊第一半導體晶片封裝元件與第二半導體晶片封裝元件，並以電性及物理連結該兩者。
茲為使 貴審查委員對本發明之結構特徵及所達成之功效更有進一步之瞭解與認識，謹佐以較佳之實施例圖及配合詳細之說明，說明如後：
100‧‧‧絕緣板
102‧‧‧絕緣框架
103‧‧‧支承件
105‧‧‧半導體晶片
107‧‧‧半導體積體電路(IC)元件
108‧‧‧表面黏著型(SMD)被動元件
110‧‧‧開口部
120‧‧‧沖孔
130‧‧‧傳導部
140‧‧‧塑模層
150‧‧‧內部絕緣層
152‧‧‧外部絕緣層
154‧‧‧上絕緣層
160‧‧‧內部信號圖像佈線
162‧‧‧上信號圖像佈線
170‧‧‧外部信號圖像佈線
180‧‧‧傳導連接件
185‧‧‧焊球或焊塊
202‧‧‧絕緣框架
205‧‧‧半導體晶片
230‧‧‧傳導部
250‧‧‧內部絕緣層
260‧‧‧內部信號圖像佈線
270‧‧‧外部信號圖像佈線
280‧‧‧傳導連接件
305‧‧‧半導體晶片
330‧‧‧傳導部
370‧‧‧外部信號圖像佈線
380‧‧‧傳導連接件
405‧‧‧半導體晶片
430‧‧‧傳導部
470‧‧‧外部信號圖像佈線
480‧‧‧傳導連接件
505‧‧‧半導體晶片
530‧‧‧傳導部
第1圖為習知技術之一半導體記憶模組之上視圖；第2-4圖為本發明實施例之剖面圖，說明了設置用來組裝一半導體晶片封裝元件之一絕緣框架；第5圖為本發明實施例之一半導體晶片封裝元件之剖面圖；第6圖為第5圖之該半導體晶片封裝元件之堆疊結構之剖面圖；第7-16圖為本發明實施例之剖面圖，說明了該半導體晶片封裝元件之製造方法；第17圖為本發明實施例之剖面圖，係為複數個半導體晶片封裝元件以垂直方向堆疊多層之結構之一半導體記憶模組；第18圖為第17圖之半導體記憶模組之上視圖；以及第19圖為第17圖之半導體記憶模組底面之底視圖。
本發明提出一種半導體晶片封裝元件，可於垂直方向堆疊。為此，設置供該半導體晶片封裝元件使用之一絕緣框架，對於該半導體晶片提供了物理支撐，同時提供了一電子連接裝置。
第2-4圖為本發明實施例之剖面圖，說明了設置用來組裝一半導體晶片封裝元件I之一絕緣框架102，可參照第5圖之描述，第5圖為本發明實施例之一半導體晶片封裝元件I之剖面圖。該半導體晶片封裝元件I包含了一絕緣框架102，一半導體晶片105，一傳導部130，一內部絕緣層150，以及一內部信號圖像佈線160。
參照第2圖，為了製造該絕緣框架102，首先，準備材質為塑膠或聚合樹脂之一絕緣板100。為了設置一半導體晶片於該絕緣板100上，先設置一個開口部110於該絕緣板100中間，如第3圖。一沖孔120設置於該開口部110周圍，如此完成了該絕緣板102之製作。該開口部110的尺寸根據該半導體晶片105來設置，可能比該半導體晶片105來得大。該沖孔120是電子信號以垂直方向傳輸的通道。如果必要，可設置複數個沖孔120，或是改變該沖孔120的位置。
參照第4圖，一傳導部130設置於該沖孔內，其中並以導體物質加以填充，如導電膏。該絕緣框架102的厚度對應了設置於該開口部110之該半導體晶片105，而不用比該半導體晶片105的厚度來得大。如果需要，透過拋光該絕緣板102之其中一邊時，該絕緣板102厚度會小於該半導體晶片105的厚度。該傳導部130可能比該絕緣框架102的頂面還高，但是，本發明並不以此為限。該絕緣框架102的成品，係為一半導體晶片封裝元件I之固定座之用。此外，該半導體晶片封裝元件I的尺寸，可能縮小到如同該半導體晶片105的大小，且個別之半導體晶片封裝元件還可以以垂直 方向堆疊起來。因此各種半導體模組，透過複數個半導體晶片封裝元件整合成一體來製作是可行的。
參照第5圖，該半導體晶片105設置於該絕緣框架102之該開口部110，該塑模層140設置於該絕緣框架102之頂面及該半導體晶片105的頂面，故該絕緣框架102與該半導體晶片105合為一體。此外，該絕緣框架102之該開口部110之內部與該半導體晶片105的一邊以預定好的距離等距安排，所以該預定好的空間位於該開口部110及該半導體晶片105之間，且該塑模層140填充於該預定好的空間，使得該半導體晶片102具有較強的支撐力。另一方面，該塑模層140接觸到該傳導部130的頂面，故該傳導部130與外部裝置有電性連接。
該內部絕緣層150設置於：該絕緣框架102上，該半導體晶片105的底面，接觸到該半導體晶片105之一部及該傳導部130。該內部信號圖像佈線160設置於該內部絕緣層150之表面，且與該半導體晶片105及該傳導部130有電性連接。該內部信號圖像佈線160係透過像是重新佈金屬線的步驟來完成的。該絕緣框架102，該半導體晶片105及該塑模層140合為一體，形成一結構。在製造該半導體封裝元件I之過程時，拋光該結構之頂面可以將該結構的整體厚度降到最低。一表面黏著型(SMD)被動元件，取代前述之該半導體晶片105設置於該開口部110，或是另一半導體晶片或是SMD被動元件與該半導體晶片105一起設置在該開口部110。
根據本發明，該半導體晶片封裝元件I可為單一封裝元件，或是可封裝成一組合結構，該組合結構可為以垂直方向堆疊的該半導體晶片封裝元件I及相同形式的封裝元件。第6圖說明了兩個該半導體晶片封裝元件I與II以垂直方向堆疊。第一個半導體晶片封裝元件I包含了一第一絕緣框架102，一第一半導體晶片105，一第一傳導部130，一第一內部絕緣層 150及一第一內部信號圖像佈線160。相同地，第二個半導體晶片封裝元件II包含了一第二絕緣框架202，一第二半導體晶片205，一第二傳導部230，一第二內部絕緣層250及一第二內部信號圖像佈線260。
第1-5圖所示，該第一半導體晶片封裝元件I與該第二半導體晶片封裝元件II的結構是全然相同的。因此不再贅述II的詳細結構。
在每一個該第一半導體晶片封裝元件I與該第二半導體晶片封裝元件II中，該第一半導體晶片105與該第二半導體晶片205係設置於該第一與第二絕緣框架102與202的中間，且I與II可以垂直方向堆疊，彼此之間有電性連結。詳細來說，每一個I包含了一第一外部信號圖像佈線170，與該第一內部信號圖像佈線160電性連接，每一個II包含了一第二外部信號圖像佈線270，與該第二內部信號圖像佈線260電性連接，且該第一外部信號圖像佈線170與該第二外部信號圖像佈線270，透過一導體連接部180電性連接起來。圖六說明了該第一外部信號圖像佈線170與該第二傳導部230，透過該導體連接部180電性連接。然而，本發明並非限定於此，該第一傳導部130與該第二外部信號圖像佈線270，也可以該導體連接部180電性連接。該導體連接部180可以透過像是焊接或是導電膠(液體或膠帶)來設置。雖然沒有圖示，焊球或焊塊可同時設置於下層之該封裝元件II的底面。此外，被動元件，積體電路(IC)晶片或是其他類似的元件可設立在上層之該封裝元件I或是下層之該封裝元件II。
在垂直堆疊結構中，單獨的封裝元件附加於每一封裝元件上，如此來製作一多層的半導體記憶模組。如同下述，一半導體記憶模組的尺寸接近一半導體晶片是可行的。
第7-16圖為本發明實施例之剖面圖，說明了該半導體晶片封裝元件之製造方法。參考第7-16圖，根據本發明的實施例，描述了該半導體晶片封裝元件的製造方法及其細節。
參照第7圖，該絕緣框架102其係包含：一開口部110位於該絕緣框架102中間，一沖孔120設立於該開口部110周圍及一傳導部130設置於該沖孔120並填充有導電膏。該傳導部130也可以其他方法設置於該沖孔120內。例如該傳導部130也可以傳導針腳方式或金屬電鍍方式設置於該沖孔內。一支承件103附著於該絕緣框架102的底面，在這種狀況下，一半導體晶片105設置於該絕緣框架102之該開口部110上。該半導體晶片105設置於該開口部110上，所以該半導體晶片105之一電極板(未圖示)位於正下方。
接著，一塑模層140設置於該絕緣框架102的頂面及該半導體晶片的頂面，如第8圖所示。該塑模層140的厚度可以被控制，端視接觸到該傳導部130的表面而定，等到該塑模層140設置後，該塑模層140會被拋光，以接觸該傳導部130的表面。在這種狀況下，該塑模層140的厚度會與該傳導部130相同。因此，整體之該半導體晶片封裝的厚度可以降到最低。
如第7圖所示，該絕緣框架102之該開口部110之內部與該半導體晶片105的一邊以預定好的距離等距安排，所以該預定好的空間位於該開口部110及該半導體晶片105之間，且該塑模層140填充於該預定好的空間，使得該半導體晶片102具有較強的支撐力。該塑模層140設置穿過且填滿該空間110a，所以該半導體晶片105可完整固定於該絕緣框架102之上。接著，該支承件103從該絕緣框架102移除，所以該半導體晶片105的底面與該傳導部130的底面暴露於外，如第9圖所示。
參照第10圖，一內部絕緣層150設置於該絕緣框架102的底面及該半導體晶片105的底面，所以不在該傳導部130的暴露部份130a與該 半導體晶片105的暴露部份105a之中。參照第11圖，一內部信號圖像佈線160設置於該內部絕緣層150上。該內部信號圖像佈線160與該半導體晶片105與該傳導部130電信連接。參照第12圖，如果需要，可額外設置一外部信號圖像佈線170，且一外部絕緣層152可進一步設置於該外部信號圖像佈線170，而使得該外部信號圖像佈線170會暴露一部分出來。
在設置一半導體晶片封裝元件電路後，將鎳(Ni)、金(Au)、銀(Ag)、銅(Cu)、錫(Sn)或其合金，被覆於該內部或外部信號圖像佈線160或170或是該傳導部130的暴露部份，可進一步改善該半導體晶片封裝元件的電子效能。在本發明中，該塑模層140係設置於該絕緣框架102的頂面及該半導體晶片105的頂面，在之後的步驟將該塑模層140拋光，所以該絕緣框架102及該半導體晶片的表面105會暴露出來。
參照第13圖，該塑模層140只填充於該絕緣框架102與該半導體晶片105之間的空間，所以該絕緣框架102與該半導體晶片105合為一體，且該絕緣框架102、該傳導部130及該半導體晶片130三者的頂面均暴露出來。在如此情況下，該塑模層140的高度等同於該絕緣框架102、該傳導部130及該半導體晶片130。
如第14圖所示，一上絕緣層154更進一步覆蓋於該絕緣框架102上及該半導體晶片105上，所以只有該傳導部130的頂面是暴露出來的。參照第15圖，一上信號圖像佈線162設置於該上絕緣層154上及該暴露出來的傳導部130，如此使得(該上絕緣層15與該傳導部130)與外部線路或其他半導體封裝元件電性連接。
參照第16圖，一內部信號圖像佈線160與該半導體晶片105及該傳導部130電性連接，一外部信號圖像佈線170與該內部信號圖像佈線160電性連接，一外部絕緣層152保護了該內部信號圖像佈線160並將該外 部信號圖像佈線170暴露一部分出來，且該外部絕緣層152更可進一步設置於該塑模層140、該絕緣框架102及該半導體晶片105三者之底面。
雖然已經描述了單一半導體晶片，但為方便理解，複數個半導體晶片可以在一個步驟內同時封裝。在這種狀況下，複數個開口部設置於一絕緣板上，複數個半導體晶片設置於每一個開口部上，並且設置一塑模層、一絕緣層、一信號圖像佈線，然後，複數個半導體晶片晶片最後切成封裝元件單元，進而得到個別的封裝元件。
第17圖為本發明實施例之剖面圖，係為複數個半導體晶片封裝元件以垂直方向堆疊多層之結構之一半導體記憶模組。複數個半導體晶片封裝元件I、II、III、IV及V以垂直方向堆疊，複數個晶片105、205、305、405及505個別嵌入該半導體晶片封裝元件I、II、III、IV及V。該半導體晶片封裝元件I、II、III、IV及V以導電膠或焊錫的方式，各自電性及物理連接。該些半導體晶片封裝元件I、II、III、IV及V中，該些傳導部彼此電性連接，或是一傳導部及一信號圖像佈線彼此電性連接。
參照第17圖，於上兩個半導體晶片封裝元件I及II，一第一傳導部130和一第二傳導部230經由一傳導連接件180電性連接。另一方面，剩下的半導體晶片封裝元件III、IV及V，其該些傳導部330、430及530透過傳導連接件280、380及480，個別跟該些外部信號圖像佈線270、370及470電性連接。此外，一半導體積體電路(IC)元件107，像是一電子抹除式可複寫唯讀記憶體(EEPROM)，和一表面黏著型(SMD)被動元件108，均設置於該最上面之半導體晶片封裝元件I上，並且與該些信號圖像佈線電性連接。在最下面之半導體晶片封裝元件V上，焊球或焊塊185作為外部連接端子，設置及連接於該些信號圖像佈線上。一印刷電路板(PCB)基板上沒有半導體晶片，取而代之的是堆疊最上面之半導體晶片封裝元件I。
第18、19圖各自說明了第17圖所述之該半導體記憶模組的頂面及底面，而第17圖中之半導體記憶模組之一堆疊結構的尺寸，洽為單一封裝元件的尺寸。特別是半導體晶片，記憶晶片可被嵌於每一個堆疊的半導體晶片封裝元件中。記憶體晶片也可能只被嵌於中間三個半導體晶片封裝元件II、III及IV，且一被動元件IC晶片(IPD)可能嵌在最上面之半導體晶片封裝元件I及最下面之半導體晶片封裝元件V。
當以上述方式堆疊了記憶晶片後，該些記憶晶片的輸入/輸出(IO)路徑不是共通的，而是獨立連結到一最終的焊塊，因此組成了一IO32或IO64記憶模組。因此，每一單元的半導體晶片封裝元件的形狀跟數量可能會被更動。在垂直堆疊的半導體模組中，記憶模組的尺寸可能會被縮減到一個封裝元件的大小，所以當記憶模組使用於一外部電子裝置時，空間利用會有所改善，且一現存的記憶模組結構，本來以水平方向擺放著改為垂直堆疊，可使得電路設計變得更精簡，一PCB基板被移除，該半導體模組的電子特性大大地改善，且達成高效能的記憶效果。
根據本發明，一半導體晶片封裝元件和一半導體模組可能有效率地使用於一記憶模組，各種的半導體系統封裝元件，以及特定之相當適合實施的立體封裝元件。根據本發明，單一半導體晶片封裝元件以垂直方向堆疊，所以一半導體模組可以各種結構來組裝。
此外，由於一半導體模組的尺寸被縮成一半導體晶片封裝元件的大小，該半導體模組的基板並非必要，所以空間利用有效率及各式電子裝置的輕量化是可實現的。此外，在垂直堆疊的半導體晶片內的信號處理速度有所增強，所以可實現一高性能的半導體模組。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技術者，在不脫離本發明之精神和範圍內，當可作些許 之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
102‧‧‧絕緣框架
105‧‧‧半導體晶片
110‧‧‧開口部
130‧‧‧傳導部
150‧‧‧內部絕緣層
160‧‧‧內部信號圖像佈線
170‧‧‧外部信號圖像佈線
180‧‧‧傳導連接件
202‧‧‧絕緣框架
205‧‧‧半導體晶片
230‧‧‧傳導部
250‧‧‧內部絕緣層
260‧‧‧內部信號圖像佈線
270‧‧‧外部信號圖像佈線

Claims (7)

  1. 一半導體模組，其包含：一第一半導體晶片封裝元件，其包含：一第一絕緣框架，該第一絕緣框架更進一步包含一第一開口部，設置於該第一絕緣框架之中間，及一第一沖孔，設置於該第一開口部之周圍；一第一半導體晶片，設置於該第一開口部中；一第一傳導部，設置於該第一沖孔內；一第一內部絕緣層，設置於該第一絕緣框架之一底面與該第一半導體晶片之一底面，以暴露該第一傳導部之一底面；一第一內部信號圖像佈線，設置於該第一內部絕緣層之上，電性連接該第一半導體晶片及該第一傳導部；一第一外部信號圖像佈線，電性連接該第一內部信號圖像佈線；以及一第一外部絕緣層，設置於該第一外部信號圖像佈線之上，並暴露該第一外部信號圖像的一部分；以及一第二半導體晶片封裝元件，其包含：一第二絕緣框架，該第二絕緣框架包含一第二開口部，設置於該第二絕緣框架之中間，及一第二沖孔，設置於該第二開口部之周圍；一第二半導體晶片，設置於該第二開口部；一第二傳導部，設置於該第二沖孔內； 一第二內部絕緣層，設置於該第二絕緣框架之底面與該第二半導體晶片之一底面，以暴露該第二傳導部之一底面；一第二內部信號圖像佈線，設置於該第二內部絕緣層上，電性連接該第二半導體晶片及該第二傳導部；一第二外部信號圖像佈線，電性連接該第二內部信號圖像佈線；以及一第二外部絕緣層，設置於該第二外部信號圖像佈線之上，並暴露該第二外部信號圖像的一部分；其中，該第一半導體晶片封裝元件與該第二半導體晶片封裝元件以垂直方向堆疊且電性連接；其中，該半導體模組更進一步包含一傳導連接件，該傳導連接件的一頂面接觸該第一外部信號圖像之該暴露部分的一底面，該傳導連接件的一底部接觸該第二傳導部的一頂面，且該傳導連接件電性連接該第一外部信號圖像佈線及該第二傳導部；其中該第一半導體晶片的一底面與該第一傳導部的一底面形成一共平面區域，且該第二半導體晶片的一底面與該第二傳導部的一底面形成另一共平面區域；其中該第一傳導部、該第一外部信號圖像佈線的該暴露部分、該傳導連接件、該第二傳導部與該第二外部信號圖像佈線的該暴露部分於垂直方向上對齊。
  2. 如申請專利範圍第1項所述之半導體模組，其中該半導體模組更進一步包含該傳導連接件與該第一傳導部及該第二外部信號圖像佈線電性連接。
  3. 如申請專利範圍第1項所述之半導體模組，其中該傳導連接件與該第一傳導部及該第二傳導部電性連接。
  4. 如申請專利範圍第1項所述之半導體模組，其中該半導體晶片包含一記憶晶片。
  5. 如申請專利範圍第1項所述之半導體模組，更進一步包含一半導體積體電路(IC)元件或一表面黏著型(SMD)被動元件，其係設置於該第一半導體晶片封裝元件或該二半導體晶片封裝元件之一表面上。
  6. 如申請專利範圍第1項所述之半導體模組，更進一步包含複數個焊球或複數個焊塊，其係設置於該第一半導體晶片封裝元件或該第二半導體晶片封裝元件之一表面上。
  7. 一半導體晶片模組之製造方法，其包含：製備一第一半導體晶片封裝元件，其包含：準備一第一絕緣框架，該第一絕緣框架包含：一第一開口部，設置於該第一絕緣框架之中間，一第一沖孔，設置於該第一開口部之周圍；設置一第一傳導部於該第一沖孔內；設置一第一半導體晶片於該第一開口部，同時該第一絕緣框架設置於一第一承載件；設置一第一塑模層於該第一絕緣框架之頂面及該第一半導體晶片之頂面；從該第一絕緣框架移除該第一承載件，以及設置一第一內部絕緣層於該第一絕緣框架之底層和該第一半導體晶片之底層；及 設置一第一內部信號圖像佈線於該第一內部絕緣層，電性連接該第一半導體晶片及該第一傳導部；製備一第二半導體晶片封裝元件，其包含：準備一第二絕緣框架，該第二絕緣框架包含：一第二開口部，設置於該第二絕緣框架之中間，一第二沖孔，設置於該第二開口部之周圍；設置一第二傳導部於該第二沖孔內；設置一第二半導體晶片於該第二開口部，同時該第二絕緣框架設置於一第二承載件；設置一第二塑模層於該第二絕緣框架之頂面及該第二半導體晶片之頂面；從該第二絕緣框架移除該第二承載件，以及設置一第二內部絕緣層於該第二絕緣框架之底層和該第二半導體晶片底層；及設置一第二內部信號圖像佈線於該第二內部絕緣層，電性連接該第二半導體晶片及該第二傳導部；以及以垂直方向堆疊該第一半導體晶片封裝元件與該第二半導體晶片封裝元件，並以電性及物理連結該兩者。
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