KR101058637B1 - 웨이퍼 레벨 패키지의 제조방법 - Google Patents
웨이퍼 레벨 패키지의 제조방법 Download PDFInfo
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- KR101058637B1 KR101058637B1 KR20090010093A KR20090010093A KR101058637B1 KR 101058637 B1 KR101058637 B1 KR 101058637B1 KR 20090010093 A KR20090010093 A KR 20090010093A KR 20090010093 A KR20090010093 A KR 20090010093A KR 101058637 B1 KR101058637 B1 KR 101058637B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 239000012778 molding material Substances 0.000 claims abstract description 67
- 238000000465 moulding Methods 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 10
- 238000005520 cutting process Methods 0.000 claims description 7
- 230000017525 heat dissipation Effects 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 description 9
- 239000000463 material Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 238000010923 batch production Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000006260 foam Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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- H01L2224/92—Specific sequence of method steps
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/1815—Shape
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Abstract
Description
Claims (16)
- 지지부재 상에 일면에 패드가 구비된 칩을 복수개 실장하는 단계;상기 각 칩의 실장면을 제외한 상기 칩들 간의 사이 공간에 몰딩재를 형성하는 단계;상기 지지부재를 제거하는 단계;상기 칩을 포함한 상기 몰딩재의 일면에, 상기 칩의 패드와 접속되는 재분배선을 포함한 절연층을 형성하는 단계; 및상기 재분배선과 접속되는 외부연결수단을 형성하는 단계;를 포함하는 웨이퍼 레벨 패키지의 제조방법.
- 제1항에 있어서,상기 지지부재로는, 글래스, 몰딩 시트 및 프레임 중 어느 하나를 사용하는 웨이퍼 레벨 패키지의 제조방법.
- 제1항에 있어서,상기 칩을 실장하는 단계에서,상기 칩은 페이스-업(face-up) 또는 페이스-다운(face-down) 방식으로 실장하는 웨이퍼 레벨 패키지의 제조방법.
- 제1항에 있어서,상기 몰딩재를 형성하는 단계에서,상기 몰딩재는 상기 칩 사이 공간만을 오픈시키는 프린팅 마스크를 이용한 프린팅 방식으로 형성하는 웨이퍼 레벨 패키지의 제조방법.
- 제4항에 있어서,상기 프린팅 마스크는 100 ㎛ 이하의 두께를 갖는 웨이퍼 레벨 패키지의 제조방법.
- 제1항에 있어서,상기 몰딩재를 형성하는 단계 이후에,상기 몰딩재를 경화시키는 단계를 더 포함하는 웨이퍼 레벨 패키지의 제조방법.
- 제1항에 있어서,상기 칩을 포함한 상기 몰딩재의 일면에, 상기 칩의 패드와 접속되는 재분배선을 포함한 절연층을 형성하는 단계 이전에,상기 칩의 패드가 구비되지 않은면을 재몰딩하는 단계;를 더 포함하는 웨이퍼 레벨 패키지의 제조방법.
- 제1항에 있어서,상기 칩을 포함한 상기 몰딩재의 일면에, 상기 칩의 패드와 접속되는 재분배선을 포함한 절연층을 형성하는 단계 이전에,상기 칩의 패드가 구비되지 않은면 상에 방열기판을 형성하는 단계;를 더 포함하는 웨이퍼 레벨 패키지의 제조방법.
- 제1항에 있어서,상기 재분배선과 접속되는 외부연결수단을 형성하는 단계 이후에,상기 칩 사이의 다이싱 라인을 따라 절단하여 단위 패키지로 분리하는 단계;를 더 포함하는 웨이퍼 레벨 패키지의 제조방법.
- 방열기판 상에 일면에 패드가 구비된 칩을 복수개 실장하는 단계;상기 각 칩의 실장면을 제외한 상기 칩들 간의 사이 공간에 몰딩재를 형성하는 단계;상기 칩을 포함한 상기 몰딩재 상에, 상기 칩의 패드와 접속되는 재분배선을 포함한 절연층을 형성하는 단계;상기 재분배선과 접속되는 외부연결수단을 형성하는 단계; 및상기 칩 사이의 다이싱 라인을 따라 절단하여 단위 패키지로 분리하는 단계;를 포함하는 웨이퍼 레벨 패키지의 제조방법.
- 제10항에 있어서,상기 칩을 실장하는 단계에서,상기 칩은 페이스-업(face-up) 방식으로 실장하는 웨이퍼 레벨 패키지의 제조방법.
- 캐리어 시트 상에 복수의 캐비티가 관통형성된 지지부재를 부착시키는 단계;상기 캐비티 내의 상기 캐리어 필름 상에 일면에 패드가 구비된 칩을 고정시키는 단계;상기 캐비티와 상기 칩 사이에 몰딩재를 충전시키는 단계;상기 캐리어 필름을 제거하는 단계;상기 칩 및 상기 몰딩재를 포함한 상기 지지부재의 일면에 상기 칩의 패드와 접속되는 재분배선을 포함한 절연층을 형성하는 단계; 및상기 재분배선과 접속되는 외부연결수단을 형성하는 단계;를 포함하는 웨이퍼 레벨 패키지의 제조방법.
- 제12항에 있어서,상기 지지부재의 CTE는 20보다 작은 웨이퍼 레벨 패키지의 제조방법.
- 제12항에 있어서,상기 몰딩재를 충전시키는 단계에서,상기 몰딩재는 프린팅 또는 디스펜싱 방식으로 충전시키는 웨이퍼 레벨 패키지의 제조방법.
- 제12항에 있어서,상기 몰딩재를 충전시키는 단계 이후에,상기 몰딩재를 경화시키는 단계;를 더 포함하는 웨이퍼 레벨 패키지의 제조방법.
- 제12항에 있어서,상기 재분배선과 접속되는 외부연결수단을 형성하는 단계 이후에,상기 칩 사이의 다이싱 라인을 따라 절단하여 단위 패키지로 분리하는 단계;를 더 포함하는 웨이퍼 레벨 패키지의 제조방법.
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KR101145041B1 (ko) * | 2010-10-19 | 2012-05-11 | 주식회사 네패스 | 반도체칩 패키지, 반도체 모듈 및 그 제조 방법 |
WO2013001171A1 (en) * | 2011-06-30 | 2013-01-03 | Murata Electronics Oy | A method of making a system-in-package device, and a system-in-package device |
KR101958831B1 (ko) | 2012-06-08 | 2019-07-02 | 삼성전자주식회사 | 양면 접착성 테이프, 반도체 패키지 및 그 제조 방법 |
US11355358B2 (en) * | 2018-09-24 | 2022-06-07 | Applied Materials, Inc. | Methods of thinning silicon on epoxy mold compound for radio frequency (RF) applications |
KR102175825B1 (ko) * | 2018-11-26 | 2020-11-06 | 엘비세미콘 주식회사 | 반도체 패키지의 제조방법 |
CN114975137A (zh) * | 2021-11-02 | 2022-08-30 | 盛合晶微半导体(江阴)有限公司 | 晶圆级封装结构及其制备方法 |
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JP2001118953A (ja) | 1999-10-20 | 2001-04-27 | Nissan Motor Co Ltd | 半導体電子部品の製造方法 |
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JP2001118953A (ja) | 1999-10-20 | 2001-04-27 | Nissan Motor Co Ltd | 半導体電子部品の製造方法 |
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