CN103229293B - 半导体芯片封装、半导体模块及其制造方法 - Google Patents
半导体芯片封装、半导体模块及其制造方法 Download PDFInfo
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Abstract
本发明涉及一种半导体芯片封装及将所述半导体芯片封装垂直层压的半导体模块及其制造方法,所述半导体芯片封装包括:绝缘架,其包括形成于中央的开口部及形成于所述开口部周围的通孔;半导体芯片,其设置在所述开口部中;导电部,其填充在所述通孔中;内部绝缘层,其形成于所述绝缘架和所述半导体芯片的底面,以使所述导电部的底面露出;内部信号图案,其形成于所述内部绝缘层上,使所述半导体芯片和所述导电部电气连接。由此,通过垂直层压单一的半导体芯片封装,从而减小半导体模块的大小,从而具有以下优点。能够实现各种电子装置的空间效率化及轻量化,并提高层压的半导体芯片之间的信号处理速度。
Description
技术领域
本发明涉及半导体芯片封装(package)、半导体模块及其制造方法,更详细地涉及多个半导体芯片封装垂直层压形成的半导体模块及其制造方法。
背景技术
半导体芯片通过封装工序安装在外部基板或电路装置上。半导体芯片封装主要与其它半导体部件一起安装在PCB等基板上,构成执行独特功能的半导体模块。
将多个半导体芯片封装安装在一个基板上,会使基板的面积增加,为了各封装间的信号传输或与其它部件之间的信号传输,需要形成额外的多个电气布线。因此,存在以下问题。使工序变得复杂,整体的半导体模块的尺寸变得更大,信号传输距离增加,高速运行变得困难。
图1表示的是每一个独立的半导体芯片,特别是安装有存储器片的存储器模块10。在PCB基板12上,以一定间距相隔设置有存储器片或存储器封装20,并同时安装有EEPROM(电可擦只读存储器)30或电容器等无源元件42及电阻44,在一侧形成有用于外部连接的连接器端线50。
这种存储器模块10是在PCB基板12上水平地设置多个存储器片20及各部件后,通过焊接(soldering)等方法,电气及机械地连接固定。因为每一个独立的半导体存储器封装20相互间隔地水平设置,使基板12的面积变大,从而使存储器模块10的大小和重量增加。此外,为了实现水平设置的各部件和存储器芯片之间的高性能信号传输,需要在基板12上形成多层(6~10层)的金属布线,因此,会产生制造工序复杂、制造费用上升的问题。
随着便携式电子器件的发展和电子产品的小型化趋势,半导体存储器模块等各种半导体系统不仅要满足轻薄短小的条件,对技术方面的要求也在加强,要使各部件的配置设计最优化,以能够传输高速信号。
发明内容
要解决的技术问题
本发明是为了解决上述问题而完成的,本发明的目的是提供一种能够垂直层压的半导体芯片封装及其制造方法。
本发明的另一目的是提供一种尺寸减小、信号处理性能得到提高的半导体模块及其制造方法。
技术方案
为了实现上述目的,本发明提供一种半导体芯片封装,所述半导体芯片封装包括:绝缘架,其包括形成于中央的开口部及形成于所述开口部周围的通孔;半导体芯片,其设置在所述开口部中;导电部,其填充在所述通孔中;内部绝缘层,其形成于所述绝缘架和所述半导体芯片的底面,以使所述导电部的底面露出;以及内部信号图案,其形成于所述内部绝缘层上,使所述半导体芯片和所述导电部电气连接。
此外,本发明提供一种半导体模块,所述半导体模块包括第一半导体芯片封装和第二半导体芯片封装,所述第一半导体芯片封装和第二半导体芯片封装垂直地层压并电气连接;所述第一半导体芯片封装包括:第一绝缘架,其包括形成于中央的第一开口部及形成于所述第一开口部周围的第一通孔;第一半导体芯片,其设置在所述第一开口部中;第一导电部,其填充在所述第一通孔中;第一内部绝缘层,其形成于所述第一绝缘架和所述第一半导体芯片的底面,以使所述第一导电部的底面露出;第一内部信号图案,其形成于所述第一内部绝缘层上,使所述第一半导体芯片和所述第一导电部电气连接;所述第二半导体芯片封装包括:第二绝缘架,其包括形成于中央的第二开口部及形成于所述第二开口部周围的第二通孔;第二半导体芯片,其设置在所述第二开口部中;第二导电部,其填充在所述第二通孔中;第二内部绝缘层,其形成于所述第二绝缘架和所述第二半导体芯片的底面,以使所述第二导电部的底面露出;第二内部信号图案,其形成于所述第二内部绝缘层上,使所述第二半导体芯片和所述第二导电部电气连接。
此外,本发明提供一种半导体芯片封装的制造方法,所述半导体芯片封装的制造方法包括以下步骤:准备绝缘架,所述绝缘架的中央形成有开口部,并在所述开口部周围形成有通孔;在所述通孔中形成导电部;在支撑部件上安装所述绝缘架的状态下,在所述开口部中设置半导体芯片;在所述绝缘架和所述半导体芯片的上面形成模塑层;从所述绝缘架上去除所述支撑部件,并在所述绝缘架和所述半导体的底面形成内部绝缘层;在所述内部绝缘层上形成内部信号图案,所述内部信号图案使所述半导体芯片和所述导电部电气连接。
此外,本发明提供一种半导体模块的制造方法,其包括形成第一半导体芯片封装的步骤;形成第二半导体芯片封装的步骤;以及使所述第一半导体芯片封装和所述第二半导体芯片封装垂至地层压,并使所述第一半导体芯片封装和所述第二半导体芯片封装电气连接或物理连接的步骤;其中,形成第一半导体芯片封装包括以下步骤:准备第一绝缘架,所述第一绝缘架在中央形成有第一开口部,并在所述第一开口部周围形成有第一通孔;在所述第一通孔中形成第一导电部;在第一支撑部件上安装所述第一绝缘架的状态下,在所述第一开口部中设置第一半导体芯片;在所述第一绝缘架和所述第一半导体芯片的上面形成第一模塑层;从所述第一绝缘架上去除所述第一支撑部件,并在所述第一绝缘架和所述第一半导体芯片的底面形成第一内部绝缘层;在所述第一内部绝缘层上形成第一内部信号图案,所述第一内部信号图案使所述第一半导体芯片和所述第一导电部电气连接;形成第二半导体芯片封装包括以下步骤:准备第二绝缘架,所述第二绝缘架的中央形成有第二开口部,并在所述第二开口部周围形成有第二通孔;在所述第二通孔中形成第二导电部;在第二支撑部件上安装所述第二绝缘架的状态下,在所述第二开口部中设置第二半导体芯片;在所述第二绝缘架和所述第二半导体芯片的上面形成第二模塑层;从所述第二绝缘架上去除所述第二支撑部件,并在所述第二绝缘架和所述第二半导体芯片的底面形成第二内部绝缘层;在所述第二内部绝缘层上形成第二内部信号图案,所述第二内部信号图案使所述第二半导体芯片和所述第二导电部电气连接。
有益效果
本发明具有以下优点:能够将单一的半导体芯片封装垂直地层压,从而制造多种结构的半导体模块。
此外,还具有以下优点:使半导体模块的大小减小至半导体芯片封装的水平,由此,不需要用于半导体模块的基板,从而能够实现各种电子器件的空间效率化及轻量化。
此外,还能够提高垂直层压的半导体芯片之间的信号处理速度,从而实现高性能半导体模块。
附图说明
图1是表示根据现有技术的半导体存储器模块的平面图。
图2至图4是表示用于本发明半导体芯片封装的绝缘架的形成过程的截面图。
图5是表示本发明的半导体芯片封装的截面图。
图6是表示本发明的半导体芯片封装层压结构的截面图。
图7至图16是表示本发明的半导体芯片封装制造工序的截面图。
图17是表示利用本发明半导体芯片封装形成的半导体存储器模块的截面图。
图18是表示图17的半导体存储器模块的上面的平面图。
图19是表示图17的半导体存储器模块底面的底视图。
具体实施方式
本发明提供一种能够垂直层压的半导体芯片封装。为此,使用一种绝缘架,其对半导体芯片提供物理性支撑力的同时,还提供电气连接单元。下面,参照附图详细地说明本发明的优选实施例。
图2至图4是表示用于实现本发明半导体芯片封装Ⅰ所使用的绝缘架102的形成过程的截面图,图5是表示本发明的半导体芯片封装Ⅰ的截面图。
本发明的半导体封装Ⅰ包括绝缘架102、半导体芯片105、导电部130、内部绝缘层150及内部信号图案160。
参照图2,为了制造绝缘架102,首先准备绝缘板100,所述绝缘板100使用塑料或高分子树脂等形成。为了在此绝缘板100上安装半导体芯片,如图3所示,在绝缘板100的中央形成开口部110。通过在开口部110周围形成通孔120,制得绝缘架102。
开口部110作为安装半导体芯片105的部分,优选大于半导体芯片105的尺寸。通孔120是垂直传输电信号的通路,根据需要可以形成多个通孔120或改变位置。
参照图4,在通孔120中填充导电性浆料(conductivepaste)等导电性物质来形成导电部130。绝缘架102的厚度与安装在开口部110上的半导体芯片105的厚度对应,不需要比半导体105的厚度厚,但可以根据需要研磨一面,使其比半导体芯片105的厚度薄。导电部130的高度优选形成为高于绝缘架102的上面,但并不限定于此。
制造完成的绝缘架102用作半导体封装Ⅰ的支撑部。此外,由于能够将半导体芯片封装Ⅰ的大小缩减成与半导体芯片105的尺寸类似的形状,且能够使个别半导体芯片封装的垂直层压,因此可以实现将多个半导体芯片封装系统地一体化的多种半导体模块。
参照图5,在绝缘架102的开口部上设置有半导体芯片105,在绝缘架102的上面及半导体芯片105的上面形成有模塑层140,从而使绝缘架102和半导体芯片105一体化。
此外,绝缘架102开口部110的里面和半导体芯片105的侧面相隔形成一定的空间,模塑层140填充在所述一定的空间内,从而对半导体芯片105的侧面提供强的支撑力。相反,模塑层140使导电部130的上面露出,以使导电部130能够与外部电气连接。
在绝缘架102和半导体芯片105的底面形成有使半导体芯片105的一部分及导电部130露出的内部绝缘层150,在内部绝缘层150的表面形成有内部信号图案160,所述内部信号图案与半导体芯片105及导电部130电气连接。该内部信号图案160可以通过金属布线等重新配置工序形成。
绝缘架102、半导体芯片105及模塑层140形成一体化,构成一个结构体,在制造工序中,对上面进行研磨,可使整体的厚度最小化。
在开口部110上可以设置表面安装型无源元件来代替上述半导体芯片105,或进一步设置与半导体芯片105不同的其它半导体芯片或表面安装型无源元件。
本发明的半导体芯片封装不仅可以用作单一封装,而且可以通过与相同形状的其它封装进行垂直层压,用作复合结构的封装。图6表示将两个半导体芯片封装Ⅰ、Ⅱ相互垂直层压的状态。
第一半导体芯片封装Ⅰ包括第一绝缘架102、第一半导体芯片105、第一导电部130、第一内部绝缘层150及第一内部信号图案160。同样,第二半导体芯片封装Ⅱ包括第二绝缘架202、第二半导体芯片205、第二导电部230、第二内部绝缘层250及第二内部信号图案260。
第一半导体芯片封装Ⅰ和第二半导体封装Ⅱ的各结构与图1至图5记载的半导体芯片封装的结构相同,因此省略详细的说明。
在各自的封装中,第一半导体芯片105和第二半导体芯片205分别设置在第一绝缘架102及第二绝缘架202的中央,第一半导体芯片封装Ⅰ和第二半导体封装Ⅱ垂直地层压并电气连接。具体地,第一半导体芯片封装Ⅰ和第二半导体封装Ⅱ分别包括与第一内部信号图案160及第二内部信号图案260电气连接的第一外部信号图案170及第二外部信号图案270,第一外部信号图案170与第二导电部230通过导电性连接部180电气连接。图6中虽然示出了第一外部信号图案170和第二导电部230通过导电性连接部180电气连接的实施例,但第一导电部130和第二外部信号图案270也可以通过导电性连接部180电气连接。
可以使用焊接或导电性粘合剂(液体或胶带)等形成导电性连接部180。虽然没有图示,但在下端封装Ⅱ的底面可以进一步形成焊锡球或焊接凸点。此外,在上端或下端的封装上可以安装无源元件、集成电路芯片等。
这种垂直层压结构具有以下优点:在每一个封装上进一步附加其它的封装,从而能够形成多层半导体模块,而且如后面所述,能够实现与半导体芯片尺寸相近的半导体存储器模块。而且,由于各半导体芯片间的电信号传输通路变短,对高速运行非常有利。
下面,具体说明本发明的半导体芯片封装的制造工序。
参照图7,准备绝缘架102,在绝缘架102的中央有开口部110,在开口部110的周围形成有通孔120,在该绝缘架102的通孔120中填充导电性浆料,从而形成导电部130。除导电性浆料外,可以通过其它方法,在通孔120中形成导电部130。例如,在通孔120中插入导电性销或在通孔120中实施金属电镀来形成导电部130。
在绝缘架102的底面附着有支撑部件103,在该状态下,在绝缘架102的开口部110上安装半导体芯片105。设置半导体芯片105时,使电极极板(未图示)向下。
之后,如图8所示,在绝缘架102及半导体芯片105的上面形成模塑层140。可以控制模塑层140的厚度,使导电部130的表面露出,也可以在形成模塑层140后,研磨模塑层140的表面,使导电部130的表面露出。在这种情况下,模塑层140的厚度与导电部130的厚度相同,从而能够使半导体芯片封装的整体厚度得以最小化。
如图7所示,优选开口部110的里面与半导体芯片105的侧面相隔形成一定的空间110a。通过使模塑层140渗透及填充到上述空间110a中,从而使半导体芯片105完全固定在绝缘架102上。
之后,如图9所示,从绝缘架102上去除支撑部件103,使半导体芯片105的底面和导电部130的底面向外部露出。
参照图10,在除了导电部130的露出部130a和半导体芯片105的露出部105a以外的绝缘架102和半导体芯片105的底面形成内部绝缘层150。参照图11,在内部绝缘层150上形成内部信号图案160,所述内部信号图案160使半导体芯片105和导电部130电气连接。参照图12,根据需要可以进一步形成外部信号图案170,在外部信号图案170上还可以进一步形成外部绝缘层152,使外部信号图案170的一部分露出。
在形成封装的电路后,可以通过在信号图案或导电部露出的表面上镀金的方法进行涂布,从而能够进一步提高电气性能,例如可以镀上镍、金、银、铜、锡或其合金等。
在本发明中,可以通过对形成在绝缘架102的上面和半导体芯片105上面的模塑层140进行后续的研磨工序来使绝缘架102和半导体芯片105的表面露出。
参照图13,可以确认模塑层140只填充在绝缘架102和半导体芯片105之间的空间中,使绝缘架102和半导体105一体化,并使绝缘架102的上面、导电部130的上面及半导体芯片105的上面全部露出。在这种情况下,模塑层140形成为:绝缘架102、半导体芯片105、导电部130的高度相同。
如图14所示,进一步形成覆盖绝缘架102和半导体芯片105的上部绝缘层154,从而能够只露出导电部130的上面。参照图15,在上部绝缘层154和露出的导电部130上形成上部信号图案162,从而能够使其与外部电路或其它半导体封装电气连接。
参照图16,在模塑层140、绝缘架102及半导体芯片105的底面,还可以形成内部信号图案160,其使半导体芯片105和导电部130电气连接;外部信号图案170,其与所述内部信号图案160连接;外部绝缘层152,其保护内部信号图案160的同时,使外部信号图案170的一部分露出。
为了便于理解,以单一半导体芯片为对象进行了说明,但也可以将多个半导体芯片同时用一个工序进行封装化。在这种情况下,在一个绝缘板上形成多个开口部,再在每个开口部上设置半导体芯片后,形成模塑层、绝缘层及信号图案,最终切割成一个个封装单元,得到单个封装。
图17表示利用本发明的半导体芯片封装进行多层垂直层压的半导体存储模块。
多个半导体芯片封装Ⅰ、Ⅱ、Ⅲ、Ⅳ、Ⅴ被垂直地层压,在每个封装中内置有半导体芯片105、205、305、405、505。利用导电性粘合剂或焊接等,将各封装Ⅰ、Ⅱ、Ⅲ、Ⅳ、Ⅴ之间相互电气或机械地连接。
多个半导体芯片封装Ⅰ、Ⅱ、Ⅲ、Ⅳ、Ⅴ相互之间,导电部之间或导电部和信号图案之间通过电气连接。
参照图17,上部的两个半导体芯片封装Ⅰ、Ⅱ中,第一导电部130和第二导电部230通过导电性连接部180相互电气连接,与此相反,可以看到剩余的半导体芯片封装Ⅲ、Ⅳ、Ⅴ之间的导电部330、430、530与外部信号图案270、370、470分别通过导电性连接部280、380、480电气连接。
此外,在上端的半导体芯片封装Ⅰ中,安装有EEPROM等半导体集成电路元件107和表面安装型(SMD,surfacemounteddevice)无源元件108,并与信号图案电气连接。
另一方面,在下端的封装Ⅴ中形成有作为外部连接端子的焊锡球或焊接凸点185,并与信号图案连接。可以层压不具有半导体芯片的普通PCB基板来代替上端的半导体芯片封装。
图18和19分别表示半导体模块的上面和底面,可以看出层压结构的尺寸仅相当于单一封装的大小。
在层压的每个封装的半导体芯片中,尤其可以内置存储器芯片,也可以只在中央的三个封装Ⅲ、Ⅳ、Ⅴ中内置存储器芯片,在上端封装Ⅰ和下端封装Ⅴ中搭载无源元件集成电路芯片(IPD)。
用上述方法层压存储器芯片时,每个存储器芯片的输入输出路径(IOpath)互不共用,独立地与最终的焊接凸点连接,从而构成IO32或IO64存储器模块。在该情况下,可以改变层压的各单元封装的导电部的个数来形成,使得每个输入输出路径连接到焊接凸点上。由此,各单元封装上的信号图案的形状或图案的个数也可以不同。
上述的垂直层压型半导体模块能够将存储器模块的大小缩小至一个封装的水平,安装在外部电子器件时,具有提高空间效率的优点,通过将现有水平的排列存储器模块改变为垂直层压结构,使电路设计大大简化,由于PCB基板被去除,使电气特性更好地得到改善,从而能够实现高性能存储器。
本发明的半导体芯片封装及半导体模块不仅可以应用在存储器模块上,还可以有效地应用在半导体系统封装等上,特别适合实现三维封装。
以上,通过优选实施例对本发明例示地进行了说明,但本发明并不限定在这些特定实施例中,在本发明提供的技术方案,以及权利要求书中记载的范畴内可以进行多种形式的修改、变更或改进。
工业实用性
根据本发明,可以制造能够垂直层压的半导体芯片封装。
Claims (12)
1.一种半导体芯片封装,其特征在于,所述半导体芯片封装包括:绝缘架,其包括形成于中央的开口部及形成于所述开口部周围的通孔;半导体芯片,其设置在所述开口部中;导电部,其填充在所述通孔中;模塑层,所述模塑层以覆盖所述绝缘架和所述半导体芯片的上面的方式设置,使所述绝缘架和所述半导体芯片一体化;内部绝缘层,其形成于所述绝缘架和所述半导体芯片的底面,以使所述导电部的底面露出;以及内部信号图案,其形成于所述内部绝缘层上,使所述半导体芯片和所述导电部电气连接,所述导电部向所述绝缘架的上部突出设置,所述模塑层以露出所述导电部端部的方式形成。
2.根据权利要求1所述的半导体芯片封装,其特征在于,所述开口部的里面与所述半导体芯片相隔形成一定的空间,所述模塑层填充在所述一定的空间内。
3.根据权利要求1所述的半导体芯片封装,其特征在于,所述半导体芯片封装还包括覆盖所述绝缘架和所述半导体芯片的上部绝缘层,以使所述导电部的上面露出。
4.根据权利要求3所述的半导体芯片封装,其特征在于,所述半导体芯片封装还包括形成于所述上部绝缘层和所述导电部上面的上部信号图案。
5.根据权利要求1所述的半导体芯片封装,其特征在于,所述半导体芯片封装还包括与所述内部信号图案电气连接的外部信号图案;以及形成于所述外部信号图案上的外部绝缘层,以使所述外部信号图案的一部分露出。
6.一种半导体模块,其特征在于,所述半导体模块包括第一半导体芯片封装和第二半导体芯片封装,所述第一半导体芯片封装和第二半导体芯片封装垂直地层压并电气连接;所述第一半导体芯片封装包括:第一绝缘架,其包括形成于中央的第一开口部及形成于所述第一开口部周围的第一通孔;第一半导体芯片,其设置在所述第一开口部中;第一导电部,其填充在所述第一通孔中;第一模塑层,所述第一模塑层以覆盖所述第一绝缘架和所述第一半导体芯片的上面的方式设置,使所述第一绝缘架和所述第一半导体芯片一体化;第一内部绝缘层,其形成于所述第一绝缘架和所述第一半导体芯片的底面,以使所述第一导电部的底面露出;第一内部信号图案,其形成于所述第一内部绝缘层上,使所述第一半导体芯片和所述第一导电部电气连接;所述第二半导体芯片封装包括:第二绝缘架,其包括形成于中央的第二开口部及形成于所述第二开口部周围的第二通孔;第二半导体芯片,其设置在所述第二开口部中;第二导电部,其填充在所述第二通孔中;第二模塑层,所述第二模塑层以覆盖所述第二绝缘架和所述第二半导体芯片的上面的方式设置,使所述第二绝缘架和所述第二半导体芯片一体化;第二内部绝缘层,其形成于所述第二绝缘架和所述第二半导体芯片的底面,以使所述第二导电部的底面露出;第二内部信号图案,其形成于所述第二内部绝缘层上,使所述第二半导体芯片和所述第二导电部电气连接,
所述第一导电部和第二导电部分别向所述第一绝缘架和所述第二绝缘架的上部突出设置,
所述第一模塑层和第二模塑层分别以露出所述第一导电部和第二导电部的端部的方式形成。
7.根据权利要去6所述的半导体模块,其特征在于,所述第一半导体芯片封装还包括与所述第一内部信号图案电气连接的第一外部信号图案;以及使所述第一外部信号图案和所述第二导电部电气连接的导电性连接部。
8.根据权利要求6所述的半导体模块,其特征在于,所述第二半导体芯片封装还包括与所述第二内部信号图案电气连接的第二外部信号图案;以及使所述第一导电部和所述第二外部信号图案电气连接的导电性连接部。
9.根据权利要求6所述的半导体模块,其特征在于,其还包括使所述第一导电部和所述第二导电部电气连接的导电性连接部。
10.根据权利要求6所述的半导体模块,其特征在于,所述半导体芯片为存储器片。
11.根据权利要求6所述的半导体模块,其特征在于,其还包括安装于所述第一半导体芯片封装或所述第二半导体芯片封装一面上的半导体集成电路元件或表面安装型无源元件。
12.根据权利要求6所述的半导体模块,其特征在于,其还包括形成于所述第一半导体芯片封装或所述第二半导体芯片封装一面上的焊锡球或焊接凸点。
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US9179541B1 (en) | 2014-07-10 | 2015-11-03 | International Business Machines Corporation | Surface-mount connector structure for embedded optical and electrical traces |
TWI581387B (zh) * | 2014-09-11 | 2017-05-01 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
KR101656269B1 (ko) * | 2014-12-30 | 2016-09-12 | 주식회사 네패스 | 반도체 패키지 및 그 제조방법 |
KR102384863B1 (ko) | 2015-09-09 | 2022-04-08 | 삼성전자주식회사 | 반도체 칩 패키지 및 이의 제조 방법 |
CN108346649B (zh) * | 2017-01-24 | 2021-03-02 | 比亚迪半导体股份有限公司 | 一种半桥功率模块及其制造方法 |
US9865570B1 (en) * | 2017-02-14 | 2018-01-09 | Globalfoundries Inc. | Integrated circuit package with thermally conductive pillar |
KR102061850B1 (ko) | 2018-02-26 | 2020-01-02 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
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