WO2013181768A1 - 具有线路布局的预注成形模穴式立体封装模块 - Google Patents
具有线路布局的预注成形模穴式立体封装模块 Download PDFInfo
- Publication number
- WO2013181768A1 WO2013181768A1 PCT/CN2012/000771 CN2012000771W WO2013181768A1 WO 2013181768 A1 WO2013181768 A1 WO 2013181768A1 CN 2012000771 W CN2012000771 W CN 2012000771W WO 2013181768 A1 WO2013181768 A1 WO 2013181768A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- cavity
- packaging
- mold cavity
- packaging module
- dimensional
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
- 238000004806 packaging method and process Methods 0.000 claims description 138
- 230000017525 heat dissipation Effects 0.000 claims description 36
- 230000008054 signal transmission Effects 0.000 claims description 32
- 230000004308 accommodation Effects 0.000 claims description 14
- 238000012360 testing method Methods 0.000 claims description 14
- 238000001746 injection moulding Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- 239000011344 liquid material Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 6
- 230000008878 coupling Effects 0.000 claims description 6
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 239000011148 porous material Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000465 moulding Methods 0.000 claims 35
- 239000011261 inert gas Substances 0.000 claims 4
- 239000000758 substrate Substances 0.000 description 17
- 229910000679 solder Inorganic materials 0.000 description 12
- 239000000969 carrier Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- GSJBKPNSLRKRNR-UHFFFAOYSA-N $l^{2}-stannanylidenetin Chemical compound [Sn].[Sn] GSJBKPNSLRKRNR-UHFFFAOYSA-N 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000007791 dehumidification Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001802 infusion Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
- 238000011897 real-time detection Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/4917—Crossed wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10156—Shape being other than a cuboid at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Definitions
- the present invention relates to a three-dimensional package module, and more particularly to a pre-filled cavity-type three-dimensional package module having a line layout. Background technique
- the three-dimensional packaging technology can integrate the die, the package and the passive component into a package, and can be a solution for the unified package.
- the integration of three-dimensional packaging technology can be combined side by side (s ide - by - s ide), stacked or a combination of the above two methods, especially the three-dimensional package has the advantages of small footprint, high performance and low cost.
- system-in-package is a die that assembles different IC types in one package, and a new technology is extended based on system-in-package (SiP), which can make more
- the die is stacked in a package and uses three dimensions to achieve more functionality or higher density integration.
- the first to be introduced is the stack (CSP).
- the products are mostly memory combo, which can stack six layers of memory chips in a BGA package, except for the traditional ones. Wi re bonding, you can also use tin tin
- the melting bumps or flip-chi p technology, and the interposers to facilitate stacking, or heat dissipation, are gradually being adopted.
- a package of stacked die will contain die as a bui lding block, which may contain a stack of memory chips, an analog die stack.
- a separate RF die is placed on an interconnected subs trate, and these constituent grains have different controls and I/ O (Input/Output) path.
- the conventional stacked package structure mainly includes a plurality of substrates, a plurality of packaged chipsets and solder balls, and some of the packaged chips are bonded or bonded on the upper surface of one of the substrates. And electrically connected by pins or solder balls, and some of the packaged chipsets are bonded or bonded on the upper substrate and/or the lower surface, and are used in the three-dimensional space by using pins or soldering.
- the substrate, the printed circuit board, and the lead frame are connected by a solder ball, a connecting post, a ring type and a substrate or a printed circuit board having an opening area in the middle, and
- the bent foot is formed as an interposer to provide the space required for the joint.
- the traditional three-dimensional package or the interposer of the module provides the upper and lower layers to be connected by the circuit-equipped pins. If the bottom carrier is a substrate or a printed circuit board, the external output electrode will be solder ball. However, if the bottom carrier is a lead frame, the external output electrode will be pinned.
- the main object of the present invention is to overcome the above-mentioned background of the invention, and in order to meet the special needs of the industry, the present invention provides a pre-filled cavity-type three-dimensional packaging module having a line layout, which can be used to solve the above-mentioned conventional art failure.
- the subject matter The pre-formed cavity-type three-dimensional package module having the line layout, the three-dimensional package or module structure appearance of the present invention can provide a protection function, and the packaged or unpackaged component can still be protected by the three-dimensional package or module structure.
- the exterior of the three-dimensional package or module structure provides a flat area for laser or ink stamping to facilitate tracking of the overall module package date.
- the architecture of the present invention can provide pads or solder balls as output electrodes, and pre-form test pads by bottom perforations to provide internal component functional testing during production, thereby increasing throughput.
- Another object of the present invention is to provide a three-dimensional package module structure that can be composed of a number of pre-formed carrier or cavity structures and that is assembled into a three-dimensional package or module structure.
- the chip and the bonding wire will not be directly exposed and protected, and the package component, the passive component, and the chip are soldered to the pre-formed cavity carrier, and The package component or the passive component is soldered to the substrate or the printed circuit board, and can also be used as the three-dimensional seal of the present invention.
- the present invention also has the object of the invention that the circuit line connection of the three-dimensional package or module structure of the present invention can be made by the bottom surface and via the side wall to the upper substrate and the cover.
- the upper substrate of the three-dimensional package module structure of the present invention can be adhered to the circuit board by the conductive material on the side wall of the pre-filled hole carrier.
- the three-dimensional package or module structure of the present invention can have a bulky module with a small pin size, and is a three-dimensional package structure using the pre-formed cavity carrier board, sub-module, printed circuit board, etc., the three-dimensional package or module of the present invention.
- Many of the substrates in the structure can be designed to accommodate other modules, or circuit area requirements, and are not limited by the apparent dimensions of the three-dimensional package or module structure of the present invention.
- the area of the circuit layout can be extended by a substrate or printed circuit board, and the substrate or printed circuit board can be placed inside the three-dimensional package or module structure of the present invention by a conductive material.
- the wire length can be shortened by the line layout of the three-dimensional package or module structure of the present invention.
- the design idea of the three-dimensional package or module structure of the present invention can be extended to a three-dimensional package structure with multiple modules.
- the three-dimensional package or module structure of the present invention is composed of a pre-formed mold holder, and the angle between the wall and the vertical surface of the pre-formed cavity carrier has an angle of more than 30. .
- the bottom and side walls of the three-dimensional package or module structure of the present invention are in the shape of a circular arc to facilitate circuit fabrication of the circuit layout.
- the line connection manner of the three-dimensional package or module structure of the present invention can be through the step structure of the side wall, and is not limited by the plane, and the staggered wire layout on the different vertical planes can be arranged by the three-dimensional package or module structure of the present invention. Avoid the short circuit caused by the mold infusion line.
- the circuitry of the three-dimensional package or module structure of the present invention can be fabricated on the bottom plane of the pre-filled die carrier and connected to the external output pads via vias.
- the external output pads of the three-dimensional package or module structure of the present invention can be elastically fabricated to be connected to the bottom of the cavity carrier by via holes, or by a solder ball of the upper cover as a solder ball pad.
- the pre-filled cavity-type three-dimensional package module having the line layout of the present invention not only solves various defects of the conventional art, but also has arbitrarily designed characteristics. Therefore, the present invention can be widely applied to commercial and industrial packaging modules to achieve an important target for the industry to develop.
- the present invention provides a pre-formed cavity-type three-dimensional package module having a line layout, the pre-filled cavity-type three-dimensional package module having a line layout comprising at least one specific layout of the first line and At least one package cavity, the at least one cavity of the package cavity
- the surface has the first line, and the package cavity forms an accommodating space by a bottom of a cavity and a sidewall of the cavity surrounding the bottom of the cavity, wherein the sidewall of the cavity is opposite to the bottom of the cavity
- the vertical axial formation is greater than three.
- the slanting angle, and the accommodating space can be placed in at least one component to electrically couple with the first line.
- the boundary between the sidewall of the cavity and the bottom of the cavity is an arc-shaped boundary region so as to form a line of the at least one specific layout in the arc-shaped boundary region, and the bottom end of the sidewall of the arc-shaped boundary region is formed at a height.
- the at least one package cavity includes at least one first via hole, so that the first line is electrically coupled to the outside via the first via hole, and the outer surface of the at least one package cavity includes At least one signal transmission area, the at least one signal transmission area is electrically coupled via the first line of the first via hole to transmit an internal and external signal, wherein the at least one signal transmission area may be a module test area.
- the at least one package cavity includes at least one heat dissipation channel for dissipating heat, wherein the at least one heat dissipation channel exposes at least one heat dissipation region on the outer surface of the package cavity, and the at least one package cavity includes at least one air hole , in order to exchange with the outside air, thereby forming an air-type package module, wherein the material can be filled with the barrier pores, and when the entire mold cavity is adhered, the air is filled with ablative gas or heated to remove moisture, thereby forming a sealed package module.
- the pre-filled cavity-type three-dimensional package module having a line layout further includes at least one first cavity carrier, the length of the first cavity carrier being greater than or equal to the opening width of the at least one package cavity.
- the first cavity carrier further includes at least one second line of a specific layout and at least one second via, the second line being formed on a surface of the first cavity carrier and via
- the at least one second via hole forms at least one signal transmission region on the other surface of the first cavity carrier, and the cavity sidewall has at least one step to form a stepped surface having at least one stage In the accommodating space.
- the pre-filled cavity-type three-dimensional package module having a line layout further includes at least one second cavity carrier plate disposed on the stage, and the second cavity carrier plate further includes at least one specific layout. a third line and at least one third via hole formed on a surface of the second cavity carrier and via the at least one third via hole on the other of the second cavity carrier An electrical coupling region is formed on the surface, wherein the accommodating space of the at least one package cavity can be filled with a low-stress liquid material to protect the internal components and the bonding wires.
- the pre-filled cavity-type three-dimensional package module having a line layout further comprises a U-shaped package cavity, a pair of symmetrical package cavity and a H-type package cavity which are mutually symmetric in appearance, wherein the pre-formed die has a line layout
- the packaging method of the injection cavity type three-dimensional package module may be selected from one of the above aspects or any combination thereof, and the above-mentioned H-type package
- the cavity further comprises two opposite openings and two H-type package cavity carrier plates, and the symmetric package cavity further comprises at least one symmetric package cavity carrier.
- the present invention provides a pre-filled cavity-type three-dimensional package module having a line layout, the pre-filled cavity-type three-dimensional package module having a line layout comprising a package module, the package module having a majority a package cavity, each package cavity is formed by a cavity bottom and a cavity sidewall surrounding the bottom of the cavity to form an accommodating space for inserting at least one component, wherein the cavity sidewall is The vertical axis of the bottom of the cavity forms an inclination angle greater than 3°, and the boundary between the sidewall of the cavity and the bottom of the cavity is an arcuate boundary zone to form a line of the at least one specific layout in the arcuate boundary zone; a first line of at least one specific layout, the first line forming and bypassing a surface of the sidewall of the cavity to electrically couple the component inside each package cavity with at least one cavity carrier, the cavity carrier For packaging each of the package cavities, wherein the bottom end of the side wall of the isolated boundary region is formed with different height steps to facilitate
- the package module includes at least one first via hole, so that the first line is electrically coupled to the external via the first via hole, and the outer surface of the package module includes at least one signal transmission area. At least one signal transmission region is electrically coupled via the first line of the first via hole to transmit an internal and external signal.
- the at least one signal transmission area may be at least one package module test area
- the package module includes at least one heat dissipation channel for dissipating heat, wherein the heat dissipation channel may expose at least one heat dissipation area on the outer surface of the package cavity.
- the package module includes at least one air hole for exchanging with the outside air, and thereby forming an air-type package module, wherein the barrier hole can be filled with a material, and the air is encapsulated or dehumidified when the whole module is packaged, thereby
- the cavity carrier board can be formed by at least one specific layout of the second line and the at least one second via hole, and the second line is formed on a surface of the cavity carrier board.
- the accommodating space described above can be filled with a low stress liquid material to protect the internal components and the bonding wires.
- the plurality of cavities described above each have a different thickness of the bottom of the cavity.
- the present invention provides a pre-filled cavity-type three-dimensional package module having a line layout, the pre-filled cavity-type three-dimensional package module having a line layout comprising a package cavity, the package cavity Is by the bottom of a cavity and a cavity side surrounding the bottom of the cavity
- the wall forms an accommodating space, wherein the sidewall of the cavity forms an inclination angle greater than 3° with the vertical axis of the bottom of the cavity, and the boundary between the sidewall of the cavity and the bottom of the cavity is an arc boundary zone
- the sidewall of the cavity has a plurality of steps to form a stepped surface having a plurality of steps in the accommodating space; a plurality of first lines of a specific layout, the package mold formed in the accommodating space
- the first line may be formed on the surface of the hole, and the first line may be electrically coupled to the component placed in the accommodating space; and the plurality of package carriers, the plurality of packages
- the boards may be respectively carried on the plurality of stages, and the plurality
- the bottom ends of the side walls of the arc-shaped junction area are formed with different height steps to facilitate interlaced wire bonding or wire bonding manufacturing processes on different vertical planes.
- the package cavity includes a plurality of first via holes, so that the first line is electrically coupled to the outside via the first via hole.
- the outer surface of the package cavity includes a plurality of signal transmission regions, and the plurality of signal transmission regions are electrically coupled via the first line of the first via hole to transmit internal and external signals.
- the above plurality of signal transmission areas may be module test areas.
- the plurality of package carriers have a plurality of second vias and a plurality of second lines of a specific layout, and the plurality of second lines are respectively formed on the surface of the plurality of package carriers, and the plurality of The two vias electrically couple the components of the two surfaces of the package carrier.
- the package cavity includes at least one heat dissipation channel for dissipating heat, wherein the at least one heat dissipation channel exposes at least one heat dissipation region on an outer surface of the package cavity.
- the above-mentioned package cavity includes at least one air hole for exchanging air with the outside air, thereby forming an air-type package module, wherein the barrier hole can be filled with a material, and the air is filled with the air or the heat is dehumidified when the whole cavity of the package is adhered. Thereby, a sealed package module can be formed.
- the accommodating space of the above-mentioned package cavity can be filled with a low-stress liquid material to protect the internal components and the bonding wires.
- the present invention provides a pre-filled cavity-type three-dimensional package module having a line layout
- the pre-filled cavity-type three-dimensional package module having a line layout comprising a plurality of package cavities, each of which is by a package cavity Forming an accommodating space at a bottom of the cavity and a sidewall of the cavity surrounding the bottom of the cavity, wherein the sidewall of the cavity forms an inclination angle greater than 3° with a vertical axis of the bottom of the cavity, and the cavity
- the intersection of the sidewall and the bottom of the cavity is an arc-shaped interface;
- the plurality of package cavities further comprise a first package cavity, a second package cavity, a third package cavity and a fourth package cavity.
- the appearance of the second package cavity and the third package cavity are mutually symmetrical and the opening size is larger than the sidewall of the cavity of the first package cavity to respectively form the sidewall of the cavity, and the fourth The opening of the cavity of the package cavity is smaller than the bottom of the cavity of the first package cavity to form a bottom of the cavity of the first package cavity, and the sidewall of the cavity of the first package cavity has a plurality of Stepping to form a stepped surface having a plurality of stages in the accommodating space; a plurality of first lines of a specific layout are respectively formed on a surface of the package cavity in the accommodating space, and the first The circuit may be formed in the arc-shaped junction area, wherein the first line is electrically coupled to the component placed in the accommodating space; and the plurality of package boards, the plurality of package carriers may be respectively carried on the plurality of stages Above, and the plurality of package carriers respectively have components on the surface thereof.
- the bottom end of the sidewall of the arc-shaped boundary region is formed with different height steps to facilitate the interlaced wire bonding or wire bonding manufacturing process on different vertical planes
- the plurality of package cavities described above comprise a plurality of first a via hole, so that the first line is electrically coupled to the external via the first via hole, wherein an outer surface of the plurality of package cavities includes a plurality of signal transmission regions, and the plurality of signal transmission regions pass through the first
- the first line of a via is electrically coupled to transmit internal and external signals, and the plurality of signal transmission areas may be module test areas.
- the plurality of package carriers have a plurality of second vias and a plurality of second lines of a specific layout, and the plurality of second lines are respectively formed on the surface of the plurality of package carriers, and the majority is
- the second vias are electrically coupled to the components of the two surfaces of the package carrier, and the package cavity includes at least one heat dissipation channel for dissipating heat, wherein the at least one heat dissipation channel is exposed on the outer surface of the package cavity At least one heat sink area.
- the above-mentioned package cavity includes at least one air hole for exchanging with the outside air, thereby forming an air-type package module, wherein the barrier hole can be filled with material, and the air is deficient or dehumidified when the whole cavity is packaged.
- the sealed package module can be formed, wherein the accommodating space of the above-mentioned package cavity can be filled with a low-stress liquid material to protect the internal components and the rifling.
- FIG. 1A to 1D are schematic views of a prior art of the present invention.
- FIGS. 2A to 2K are schematic views of a pre-filled cavity-type three-dimensional package module having a line layout according to an embodiment of the present invention
- 3A through 3D are actual black and white photographs of a pre-filled cavity-type three-dimensional package module having a line layout in accordance with an embodiment of the present invention.
- Pre-formed cavity-type three-dimensional package module 200A/200B Type II package cavity
- 200E/200F Symmetrical package cavity
- 200C/200D H-package cavity
- heat dissipation channel 265 heat dissipation zone
- a pre-filled cavity-type three-dimensional package module having a line layout according to the present invention is hereinafter described with reference to the accompanying drawings and preferred embodiments. The embodiment, structure, characteristics and efficacy thereof are described in detail below.
- the present invention is directed to a three-dimensional package module, and in order to provide a thorough understanding of the present invention, the detailed structure and its components and method steps are set forth in the following description. Obviously, the practice of the present invention is not limited to the special field section that is familiar to those skilled in the art of packaging modules. On the other hand, well-known structures and components thereof are not described in detail to avoid unnecessarily limiting the invention. In addition, in order to provide a clearer description and to enable those skilled in the art to understand the invention of the present invention
- the present invention provides a pre-filled cavity-type three-dimensional package module 200 having a line layout
- the pre-filled cavity-type three-dimensional package module having a line layout includes less a first line 21 OA of a specific layout and at least one package cavity 220, and the at least one package cavity 220 is formed by a cavity bottom 220A and a cavity sidewall 220B surrounding the cavity bottom 220A.
- the space 220C is pre-formed on the cavity surface of the package cavity 220 including the cavity bottom 220A and the cavity sidewall 220B, as shown in FIG. 2B.
- the accommodating space 220C can be used to insert at least one component 230 to be electrically coupled to the first line 210A, wherein the component 230 can be a pin or solder ball pad at a specific position if the component is a package component.
- the first line 210A is electrically coupled,
- the component 230 if it is an unpackaged component, can be electrically coupled to the first line 21 OA at a specific location directly in a wire bonding process.
- the cavity sidewall 220B is formed with an inclination angle greater than 3° with the vertical axis of the cavity bottom 220A, and the cavity sidewall 220B and the cavity bottom 220A.
- the junction is an arcuate boundary region R so that the first line 210A is formed from the cavity bottom portion 220A via the isolated boundary region R to the cavity sidewall 220B, wherein the cavity boundary portion 220B of the arcuate boundary region R is formed.
- the bottom end forms a step of varying heights to facilitate interleaved wire bonding or wire bonding processes on different vertical planes, as shown in Figure 2D.
- the at least one package cavity 220 includes at least one first via 240A, so that the first line 210A is electrically coupled to the outside via the first via 240A.
- the outer surface of the at least one package cavity 220 includes at least one first signal transmission region 250A electrically coupled via the first line 210A of the first via 240A.
- the internal and external signals are transmitted, as shown in FIG. 2E, wherein the first signal transmission area 250A can be a test electrode of the module test area and/or an input/output electrode, and the outer surface of the package cavity 220 can be used for packaging cycle or information. Stamped, as shown in Figure 2F.
- the at least one package cavity 220 includes at least one heat dissipation channel 260 for heat dissipation, wherein the at least one heat dissipation channel 260 can be exposed on the outer surface of the package cavity.
- the at least one package cavity 220 includes at least one air hole for exchanging air with the outside air, thereby forming an air-type package module, wherein the barrier pores can be filled with a material, and the air is filled with the air or the heat is fixed when the package is integrally sealed. Dehumidification can be used to form a sealed package module.
- the pre-filled cavity-type three-dimensional package module having a line layout further includes at least one first cavity carrier 270A, and the length of the first cavity carrier 270A is equal to the at least one package cavity 220.
- the first cavity carrier 270 further includes at least one specific layout of the second line 210B and at least one second via 240B.
- the second line 210B is formed on the first cavity carrier 270A. Forming at least one second signal transmission region 250B on the other surface of the first cavity carrier 270A via the at least one second via 240B, as shown in FIG. 2G, wherein the second The signal transmission region 250B can be used to carry a conductive material such as a pad/solder ball.
- the cavity sidewall 220B has at least one step to form a stepped surface having at least one step 225 in the accommodating space 220C, as shown in FIG. 2C, and the at least one first cavity described above
- the plate 270A can be placed on the stage 225 to be in close contact with the accommodating space 220C.
- the accommodating space 220C of the at least one package cavity 220 may be filled with a low-stress liquid material to protect the internal components and the bonding wires.
- the pre-formed cavity-type three-dimensional package module 200 having a line layout further includes a U-shaped package cavity 200A/200B, and a pair of symmetric shapes that are symmetrical to each other.
- the package cavity 200E/200F and the H-type package cavity 200C/200D, wherein the package layout of the pre-formed cavity-type three-dimensional package module 200 having the line layout may be selected from one of the above aspects or any combination thereof.
- the above-mentioned H-type package cavity 200C/200D further comprises two opposite openings and two H-type package cavity carrier plates
- the above-mentioned symmetric package cavity 200E/200F further comprises at least one symmetric package cavity carrier plate.
- the combination of the present invention is a concept of spatial stacking, like the architecture of a building block, which is quite different from the conventional shelf concept.
- the present invention can adopt different cavity combinations for visual requirements, such as: 200B/200C
- the schematic diagram of the application combination of /200B, 200A/200C/200A, etc. is shown in Fig. 21.
- the first modification of the application of the present invention has a multi-stage structure on the side wall of the cavity of the single package cavity, and is mounted with the cavity carrier plates of appropriate sizes.
- the cavity carrier of the three-dimensional package or module structure of the present invention can be directly regarded as a PCB or a PVB, so that the present invention can be extended not only by an internal substrate or a printed circuit board but also by similar
- the cavity-type substrates of different modules are soldered to the basic module substrate for extension, as shown in Fig. 2K.
- the application of FIG. 2K is a plurality of package cavities having different thicknesses in the same package module, and each cavity can be directly connected by the line on the sidewall of the cavity. Therefore, the present invention can be easily achieved.
- 3A to 3D are black and white photographs which are implemented according to the present invention, and the circuit layout can be designed on the sidewall of the package cavity.
- the line connection method of the present invention can be performed via the side.
- the wall is not limited by the plane.
- the present invention also enables the unpackaged component to be wired directly into the packaged module for wire bonding manufacturing processes. Obviously, the present invention may have many modifications and differences as described in the above embodiments. It is therefore to be understood that within the scope of the appended claims, the invention may be
- the three-dimensional package or module structure of the present invention is composed of a pre-formed cavity-type carrier, and the wall of the pre-formed cavity carrier has an included angle of more than 30 between the wall and the vertical.
- the junction of the bottom and the side wall of the three-dimensional package or module structure of the present invention is in the shape of a circular arc to facilitate circuit fabrication of the circuit layout.
- the three-dimensional package or module structure of the present invention can provide a protective function, and the packaged or unpackaged components can still be protected within the three-dimensional package or module structure.
- the exterior of the three-dimensional package or module structure provides a flat area for laser or ink stamping to facilitate tracking of the overall module package date.
- the architecture of the present invention can provide solder pads or solder balls as output electrodes, and pre-form test pads by bottom perforations to provide functional testing of internal components during production, thus increasing throughput.
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
一种具有线路布局的预注成形模穴立体封装模块。立体式封装或模块结构由预先成型的模穴式载板组成,并且预先成型的模穴式载板的墙与垂直面间具有一含有30°以上的夹角。立体式封装或模块结构的底部与侧墙的交界处是圆弧的形状,以利于电路布局的线路制作。
Description
具有线路布局的预注成形模穴式立体封装模块 技术领域
本发明涉及一种立体封装模块,特别是涉及一种具有线路布局的预注 成形模穴式立体封装模块。 背景技术
低成本、 小尺寸与多功能性的需求已成为电子工业发展的主要动力。 而
IC 产业当前的主要挑战的一, 即在于如何运用适当的成本, 有效组装各 式功能在一个有限的封装形式中, 并使不同功能的晶粒达到最佳化的表 现。 为达这些目的, 目前已发展出许多的先进封装技术, 例如覆晶、 芯片 尺寸封装(Chip Scale Package; CSP ). 晶圆级封装以及立体封装(3D Package )技术等。 然而, 在数字、 模拟、 内存及无线射频等领域的应用 中, 不同功能的电子电路随着在需要制造工艺技术微缩化下,会产生不同 的需求及结果,因此在单一晶粒上整合不同的功能已非达成最佳化的解决 方案。随着系统单晶片(S0C)、 系统级封装(S iP)、堆叠封装(Pi P; Package - in - Package)、层叠封装(PoP; Package - on - Package),以及堆栈( CSP ) 技术的快速发展, 近年来最有效能的是统芯片应朝向单一封装结构中,借 由充分利用多维空间的架构,整合使用异质性技术及不同电压操作环境的 各种功能不同的晶粒。 因此, 目前的是统芯片的封装已朝向立体封装技术 的概念, 立体封装技术可将晶粒、 封装与被动组件整合成一封装体, 而可 成为是统封装的一种解决方式。 立体封装技术的整合可以并排式(s ide - by - s ide)、 堆栈式或上述两方式的结合, 尤其立体封装具有有小占位面 积、 高性能与低成本的优势。
具有体来说,上述是统级封装(System - in - Package; SiP )是在一个封 装中组装不同 IC种类的晶粒,基于系统级封装 (SiP)延伸出一种新技术,其 可让多片晶粒堆栈在一个封装模块中,并运用三度空间来达成更多功能或 更高密度的整合。 在这类封装结构中,首先被推出的是堆栈(CSP ), 其产 品多为 组合式存储器(memory combo) , 其可在一个 BGA封装中堆栈六层 的内存晶粒, 其内除了传统的打线烊接(wi re bonding ), 也可使用烊锡
熔点(solder bumps)或覆晶 ( f l i p - chi p ) 技术, 而力口入中介层 ( interposers )以利于堆栈, 或散热亦逐渐被采用。 举例来说, 一个堆栈 晶粒的封装中会包含分开但互相用导线连结的晶粒组成(die as bui lding block ), 可能包含一颗到数颗内存晶粒的堆栈、一颗模拟晶粒堆栈在另一 颗单晶片(S0C)或数字晶粒上,另有一颗独立的 RF晶粒位于一个多层相连 结基板 ( interconnected subs trate )上, 而这些组成晶粒都有不同的控 制及 I/O (Input/Output)路径。
请参阅图 1A图至图 1D图所示,传统堆栈式封装结构主要包括多数个 基板、 多数个已封装芯片组及焊球等, 部分已封装芯片组黏合或接合在其 中一基板的上表面上, 并利用接脚或焊球的方式电性连接,部分已封装芯 片组则黏合或接合在另一基板之上且 /或下表面上, 并透过利用接脚或焊 以便于在立体空间中迭加而形成立体封装的架构, 其中, 基板、 印刷电路 板, 导线架间的连结方式是借由锡球、 连接柱、 环型且中间具有有开孔面 积设计的基板或印刷电路板,及弯脚成形作为中介层以提供连结所需的空 间。传统的立体式封装或模块的中介层提供上下层电路借由具有有电路功 能的接脚进行连结, 如果底层载板是采用基板或印刷电路板, 其对外的输 出电极将是采用锡球方式,但若底层载板是采用导线架, 其对外的输出电 极将是采用接脚方式。
目前是传统厂商的封装方式大多如上图所示,为一种多层堆栈式封装 架构, 其主要是以封装完成的 Die 为主 jtbi†多层堆 樣架构有着种种 的困难以及缺陷,一方面芯片和焊线直接暴露于空气中无保护,将导致可 靠度问题,因此在目前所行的任何载板上无法采用焊线制造工艺将芯片的 电路连接至载板上,故这些封装架构所使用的组件必须为已封装组件,且皆 以外观棵露而无保护的方式焊接于载板结构或是印刷电路^反 ( PCB )上, 虽 然可以借由涂布保护层的方式予以再封装保护, 但是一旦涂布保护层之 后, 内部组件具有有瑕疵或是毁损的情形时, 除非去除此涂布层, 否则整 个封装模块即必须抛弃, 并无法再拆解封装组件进行修复, 此对于是传统 厂商而言, 维修成本相当高。 另一方面, 由于传统立体封装的方式无法于 生产当下实时检测, 仅能于封装完成时逐一测试, 此亦造成难以量产的重 大因素。
传统的多层堆栈式封装架构若使用刚性导体作为层架支撑,虽能控制
层间高度, 但在制造工艺上的准位控制相当困难。 相对地,若使用焊球为 层架支撑, 虽能轻易地解决准位的问题, 但有其高度限制,尤其易使上层 基板压制于下层组件上。此外,传统的立体架构最被诟病的处在于散热问 题, 越多层的架构, 代表运作的是统模块越多,每个组件运作时所产生的 热,会产生加乘的效应,对于多层堆栈式封装架构而言,散热效果极差。再 者, 以单独的已封装组件而言, 都具有有各自的盖印, 但对于整个封装模 块而言, 其盖印方式是制作于载板结构或印刷电路板上, 并无针对模块的 封装制造工艺日期可供追溯。
上述种种因素均会严重影响立体封装的可靠度,并大大地降低封装制 造工艺的良率, 导致成本大幅提高。 因此, 如何克服上述缺陷仍为当前产 业亟需发展的重要标的。
有鉴于上述现有的封装存在的缺陷,本发明人基于从事此类产品设计 制造多年丰富的实务经验及专业知识, 积极加以研究创新, 以期创设一种 新型结构的具有线路布局的预注成形模穴式立体封装模块,能够改进一般 现有的封装封装, 使其更具有有实用性。 经过不断的研究、 设计, 并经反 复试作样品及改进后, 终于创设出确具有实用价值的本发明。 发明内容
本发明的主要目的在于,克服上述的发明背景中, 为了符合产业上特 别的需求,本发明提供一种具有有线路布局的预注成形模穴式立体封装模 块可用以解决上述传统技艺未能达成的标的。使其具有线路布局的预注成 形模穴式立体封装模块,本发明的立体式封装或模块结构外观可提供保护 功能, 并且已封装或未封装组件仍可被保护于此立体式封装或模块结构 内。 此外, 该立体式封装或模块结构的外部可提供一平坦区域以供激光或 油墨盖印, 以便于追踪整体模块封装日期。 再者, 本发明的架构可提供焊 垫或锡球做为输出电极, 并借由底部穿孔预先制作测试焊垫, 以便于生产 期间, 提供内部组件功能测试, 如此即可提高产量。
本发明的另一目的是提供立体封装模块结构可由许多预先成形的载 板或模穴结构组成, 并且被组装成一立体式封装或模块结构。在此立体式 封装或模块结构中, 芯片和焊线将不会直接被暴露而不受到保护, 而封装 组件、 被动组件、 和芯片被焊着于预先成形的模穴式载板上, 且已封装组 件或被动组件被焊着于基板或印刷电路板上亦可做为本发明的立体式封
装或模块结构的盖子或内部线路层。
本发明还具有下述的目的,本发明的立体式封装或模块结构的电路线 路连接方式可由底面制作线路, 并经由侧墙至上层基板与盖子。
本发明的立体式封装模块结构的上层基板可借由导电材料于预注模 穴载板的侧墙上平阶作电路线路黏着。
本发明的立体式封装或模块结构可具有小脚位尺寸的庞大模块,是利 用预先成形的模穴式载板、 次模块,印刷电路板等迭合成立体封装结构,本 发明的立体式封装或模块结构中的许多基板可因应其它模块,或电路面积 需求而设计, 并不受本发明的立体式封装或模块结构外观尺寸的限制。 电 路布局的区域可借由基板或印刷电路板被延伸,且基板或印刷电路板可被 置放于本发明的立体式封装或模块结构内部借由导电材料接着。可借由本 发明的立体式封装或模块结构的线路布局方式缩短焊线长度。
本发明的立体式封装或模块结构的设计想法可被延伸至设计于具有 多模块的立体封装结构方式。本发明的立体式封装或模块结构是由预先成 型的模穴式载板(Pre- mold cavi ty holder)组成, 并且预先成型模穴载板 的墙与垂直面间具有有一含 30 以上的夹角。
本发明的立体式封装或模块结构的底部与側墙是圓弧的形状,以利于 电路布局的线路制作。
本发明的立体式封装或模块结构的线路连接方式可经由侧墙的步阶 结构, 并不受平面的限制,借由本发明的立体式封装或模块结构于不同垂 直平面上的交错焊线布局可避免模流灌注冲线造成短路。
本发明的立体式封装或模块结构的线路可制作于预注模穴式载板的 底部平面, 并且经由导通穿孔与对外输出焊垫连接。
本发明的立体式封装或模块结构的对外输出焊垫可弹性地制作成借 由导通孔连接于模穴载板的底部,或由上盖的印刷电路板以锡球焊垫作为 接着。
据此,借由本发明的具有线路布局的预注成形模穴式立体封装模块,不 但可解决传统技艺的种种缺陷, 其更具有可任意设计的特性。故本发明可 广泛地应用于封装模块的商业与工业中以达成产业亟需发展的重要标的。
根据本发明上述的目的,本发明提供一种具有线路布局的预注成形模 穴式立体封装模块,该具有线路布局的预注成形模穴式立体封装模块包含 至少一特定布局的第一线路与至少一封装模穴,该至少一封装模穴的模穴
表面具有该第一线路,且该封装模穴是借由一模穴底部与环绕该模穴底部 的一模穴侧壁形成一容置空间,其中该模穴侧壁是与该模穴底部的垂直轴 向形成大于 3。 的倾斜角, 且该容置空间可置入至少一组件以便与该第一 线路电性耜合。此外, 上述的模穴侧壁与该模穴底部交界处是为一弧状交 界区以便于形成该至少一特定布局的线路于该弧状交界区,且上述的弧状 交界区的侧壁底端形成高度不一的步阶,以便于不同的垂直平面上进行交 错式焊线布局或打线制造工艺。再者, 上述的至少一封装模穴包含至少一 第一导通孔, 以便于该第一线路经由该第一导通孔与外部电性耦合,且上 述的至少一封装模穴的外部表面包含至少一个信号传输区,该至少一个信 号传输区经由该第一导通孔的该第一线路电性耦合以传输内外信号, 其 中, 上述的至少一个信号传输区可为模块测试区。
上述的至少一封装模穴包含至少一个散热通道, 以便于散热, 其中, 该至少一个散热通道可于封装模穴的外表面外露至少一散热区,且上述的 至少一封装模穴包含至少一个气孔, 以便与外界空气交换,借此可形成空 气型封装模块, 其中, 可以材料填充阻隔气孔, 并于黏着封装整体模穴时 以填充钝气或加热去湿气, 借此可形成密封型封装模块的用。 此外, 上述 的具有线路布局的预注成形模穴式立体封装模块更包含至少一第一模穴 载板,该第一模穴载板的长度大于等于该至少一封装模穴的开口宽度。再 者,上述的第一模穴载板更包至少一特定布局的第二线路与至少一第二导 通孔,该第二线路形成于该第一模穴载板的一表面上, 并经由该至少一第 二导通孔于该第一模穴载板的另一表面上形成至少一信号传输区,且上述 的模穴侧壁具有至少一步阶以形成具有至少一阶台的阶梯状表面于该容 置空间中。
上述的具有线路布局的预注成形模穴式立体封装模块更包含至少一 第二模穴载板容置于该阶台上,且上述的第二模穴载板更包至少一特定布 局的第三线路与至少一第三导通孔,该第三线路形成于该第二模穴载板的 一表面上,并经由该至少一第三导通孔于该第二模穴载板的另一表面上形 成电性耦合区, 其中, 上述的至少一封装模穴的该容置空间可填充一低应 力的液态材料以保护内部组件与焊线。 此外, 该具有线路布局的预注成形 模穴式立体封装模块更包含 U型封装模穴、一对外观相互对称的对称型封 装模穴、 H型封装模穴, 其中, 该具有线路布局的预注成形模穴式立体封 装模块的封装方式可选择上述样态的一或其任意组合,且上述的 H型封装
模穴更包含相对两开口与两 H型封装模穴载板,而上述的对称型封装模穴 更包含至少一对称型封装模穴载板。
本发明的目的是由以下技术方案实现的。
根据本发明上述的目的,本发明提供一种具有线路布局的预注成形模 穴式立体封装模块,该具有线路布局的预注成形模穴式立体封装模块包含 一封装模块, 该封装模块具有多数个封装模穴,每个封装模穴是借由一模 穴底部与环绕该模穴底部的一模穴侧壁形成一容置空间以置入至少一组 件, 其中,该模穴側壁是与该模穴底部的垂直轴向形成大于 3°的倾斜角,且 该模穴侧壁与该模穴底部交界处是为一弧状交界区以便于形成该至少一 特定布局的线路于该弧状交界区; 至少一特定布局的第一线路, 该第一线 路形成并绕行于该模穴侧壁的表面以电性耦合各封装模穴内部的该组件 与至少一模穴载板, 该模穴载板用以封装每个封装模穴, 其中上述的孤状 交界区的侧壁底端形成高度不一的步阶,以便于不同的垂直平面上进行交 错式焊线布局或打线制造工艺, 且上述的封装模块包含至少一第一导通 孔, 以便该第一线路经由该第一导通孔与外部电性耦合, 而上述的封装模 块的外部表面包含至少一个信号传输区,该至少一个信号传输区经由该第 一导通孔的该第一线路电性耦合以传输内外信号。
上述的至少一个信号传输区可为至少一封装模块测试区,且上述的封 装模块包含至少一个散热通道, 以便于散热, 其中该散热通道可于封装模 穴的外表面外露至少一散热区。 此外, 上述的封装模块包含至少一个气孔 以便与外界空气交换, 并借此形成空气型封装模块, 其中, 可以材料填充 阻隔气孔, 并于封装整体模块时填充钝气或加热去湿气,借此可形成密封 型封装模块之用,且上述的模穴载板更包至少一特定布局的第二线路与至 少一第二导通孔, 该第二线路形成于该模穴载板的一表面上, 并经由该至 少一第二导通孔于该模穴载板的另一表面上形成电性耦合区, 其中, 上述 的模穴侧壁具有至少一步阶以形成具有至少一阶台的阶梯状表面,且该至 少一阶台可用以承载该模穴载板。再者, 上述的容置空间可填充一低应力 的液态材料以保护内部组件与焊线。上述的多数个模穴分别具有不同厚度 的该模穴底部。
根据本发明上述的目的,本发明提供一种具有线路布局的预注成形模 穴式立体封装模块,该具有线路布局的预注成形模穴式立体封装模块包含 一封装模穴,该封装模穴是借由一模穴底部与环绕该模穴底部的一模穴侧
壁形成一容置空间, 其中, 该模穴侧壁是与该模穴底部的垂直轴向形成大 于 3° 的倾斜角,且该模穴側壁与该模穴底部交界处是为一弧状交界区,且 该模穴侧壁具有多数个步阶以形成具有多数个阶台的阶梯状表面于该容 置空间中; 多数个特定布局的第一线路, 形成于该容置空间中的该封装模 穴的表面上, 且该第一线路可形成于该弧状交界区, 其中, 该第一线路可 与置入该容置空间的组件电性耦合; 与多数个封装载板, 该多数个封装载 板可分别承载于该多数个阶台上,且该多数个封装载板分别具有组件于其 表面上。 上述的弧状交界区的侧壁底端形成高度不一的步阶,以便于不同 的垂直平面上进行交错式焊线布局或打线制造工艺。上述的封装模穴包含 多数个第一导通孔,以便于该第一线路经由该第一导通孔与外部电性耦 合。上述的封装模穴的外部表面包含多数个信号传输区, 该多数个信号传 输区经由该第一导通孔的该第一线路电性鵪合以传输内外信号。上述的多 数个信号传输区可为模块测试区。上述的多数个封装载板具有多数个第二 导通孔与多数个特定布局的第二线路,该多数个第二线路分别形成于该多 数个封装载板的表面上,并经由该多数个第二导通孔电性耦合该封装载板 的两表面的组件。 上述的封装模穴包含至少一个散热通道,以便于散热,其 中, 该至少一个散热通道可于封装模穴的外表面外露至少一散热区。 上述 的封装模穴包含至少一个气孔, 以便与外界空气交换,借此可形成空气型 封装模块, 其中, 可以材料填充阻隔气孔, 并于黏着封装整体模穴时以填 充钝气或加热去湿气, 借此可形成密封型封装模块之用。 上述的封装模穴 的该容置空间可填充一低应力的液态材料以保护内部组件与焊线。
本发明的目的及解决其技术问题还采用以下技术方案来实现。
本发明提供一种具有线路布局的预注成形模穴式立体封装模块,该具 有线路布局的预注成形模穴式立体封装模块包含多数个封装模穴,每一个 该封装模穴是借由一模穴底部与环绕该模穴底部的一模穴侧壁分别形成 一容置空间, 其中该模穴侧壁是与该模穴底部的垂直轴向形成大于 3° 的 倾斜角,且该模穴側壁与该模穴底部交界处是为一弧状交界区; 多数个封 装模穴更包含一第一封装模穴、 一第二封装模穴、一第三封装模穴与一第 四封装模穴 ,其中该第二封装模穴与该第三封装模穴的外观是相互对称且开 口尺寸大于该第一封装模穴的该模穴侧壁以分别组成于该模穴侧壁上,且 该第四封装模穴的开口口径小于该第一封装模穴的模穴底部以组成于该 第一封装模穴的模穴底部上,且该第一封装模穴的该模穴侧壁具有多数个
步阶以形成具有多数个阶台的阶梯状表面于该容置空间中;多数个特定布 局的第一线路,分别形成于该容置空间中的该封装模穴的表面上, 且该第 一线路可形成于该弧状交界区,其中该第一线路可与置入该容置空间的组 件电性耦合; 与多数个封装栽板, 该多数个封装载板可分别承载于该多数 个阶台上, 且该多数个封装载板分别具有组件于其表面上。
上述的弧状交界区的侧壁底端形成高度不一的步阶,以便于不同的垂 直平面上进行交错式焊线布局或打线制造工艺,且上述的多数个封装模穴 包含多数个第一导通孔,以便于该第一线路经该第一导通孔与外部电性耦 合, 其中上述的多数个封装模穴的外部表面包含多数个信号传输区, 该多 数个信号传输区经由该第一导通孔的该第一线路电性耦合以传输内外信 号, 且上述的多数个信号传输区可为模块测试区。 此外, 上述的多数个封 装载板具有多数个第二导通孔与多数个特定布局的第二线路,该多数个第 二线路分别形成于该多数个封装载板的表面上,并经由该多数个第二导通 孔电性耦合该封装载板的两表面的组件,且上述的封装模穴包含至少一个 散热通道, 以便于散热, 其中该至少一个散热通道可于封装模穴的外表面 外露至少一散热区。 再者,上述的封装模穴包含至少一个气孔, 以便与外 界空气交换, 借此形成空气型封装模块,其中,可以材料填充阻隔气孔, 并 于封装整体模穴时填充钝气或加热去湿气,借此可形成密封型封装模块之 用,其中上述的封装模穴的该容置空间可填充一低应力的液态材料以保护 内部组件与烊线。
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的 技术手段, 而可依照说明书的内容予以实施, 并且为了让本发明的上述和 其它目的、 特征和优点能够更明显易懂, 以下特举较佳实施例, 并配合附 图,详细说明如下。 附图的简要说明
图 1A图至图 1D图是为本发明的在先技术示意图;
图 2A图至图 2K图是为根据本发明的实施例的具有线路布局的预注成 形模穴式立体封装模块的示意图;
图 3A图至图 3D图是为根据本发明的实施例的具有线路布局的预注成 形模穴式立体封装模块的实作黑白相片。
200: 预注成形模穴式立体封装模块 200A/200B: II型封装模穴
200E/200F: 对称型封装模穴 200C/200D: H型封装模穴
21 OA:第一线路 210B:第二线路
220:封装模穴 22 OA:模穴底部
220B:模穴侧壁 220C:容置空间
225:阶台 230:组件
24 OA:第一导通孔 240B:第二导通孔
25 OA:第一信号传输区 250B:第二信号传输区
260:散热通道 265:散热区
27 OA:第一模穴载板 R :弧状交界区 实现发明的最佳方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效, 以下结合附图及较佳实施例,对依据本发明提出的具有线路布局的预注成 形模穴式立体封装模块, 其具有体实施方式、 结构、 特征及其功效, 详细 说明如后。
本发明在此所探讨的方向为立体封装模块,为了能彻底地了解本发 明, 将在下列的描述中提出详尽的结构及其组件与方法步骤。 显然地,本 发明的施行并未限定于封装模块的技艺者所熟习的特 田节。 另一方面,众 所周知的结构及其组件并未描述于细节中,以避免造成本发明不必要的限 制。 此外,为提供更清楚的描述及使熟悉该项技艺者能理解本发明的发明
求图示的简洁。
根据本发明的一实施例, 参阅图 2A所示, 本发明提供一种具线路布 局的预注成形模穴式立体封装模块 200, 该具有线路布局的预注成形模穴 式立体封装模块包括少一特定布局的第一线路 21 OA 与至少一封装模穴 220,且该至少一封装模穴 220是借由一模穴底部 220A与环绕该模穴底部 220A的一模穴侧壁 220B形成一容置空间 220C, 其中, 该第一线路 210是 预先制作于包含该模穴底部 220A与该模穴侧壁 220B的该封装模穴 220的 模穴表面上, 如图 2B所示。上述的容置空间 220C中可用以置入至少一组 件 230以便与该第一线路 210A电性耦合, 其中, 该组件 230若为封装组 件则可以接脚或锡球垫方式于特定位置上与该第一线路 210A电性耦合,
该组件 230 若为未封装组件则可直接以打线制造工艺于特定位置上与该 第一线路 21 OA电性耦合。
请阅图 2C所示,根据本发明的实施例, 该模穴侧壁 220B是与该模穴 底部 220A的垂直轴向形成大于 3° 的倾斜角, 且模穴侧壁 220B与模穴底 部 220A交界处是为一弧状交界区 R以便于该第一线路 210A 自模穴底部 220A经由该孤状交界区 R形成至模穴側壁 220B上, 其中, 上述的弧状交 界区 R的模穴侧壁 220B底端形成高度不一的步阶(Step ), 以便于不同的 垂直平面上进行交错式焊线布局或打线制造工艺, 如图 2D所示。 上述的 至少一封装模穴 220包含至少一第一导通孔 240A,以便于该第一线路 210A 经由该第一导通孔 240A与外部电性耦合。 此外, 上述的至少一封装模穴 220的外部表面包含至少一个第一信号传输区 250A,该至少一个第一信号 传输区 250A经由该第一导通孔 240A的该第一线路 210A电性耦合以传输 内外信号, 如图 2E所示, 其中, 第一信号传输区 250A可为模块测试区的 测试电极且 /或输出入电极, 且该封装模穴 220的外部表面可供封装曰期 或信息的盖印, 如图 2F所示。
请参阅图 2A所示,根据本发明的实施例,上述的至少一封装模穴 220 包含至少一个散热通道 260, 以便于散热, 其中,该至少一个散热通道 260 可于封装模穴的外表面外露至少一散热区 265。 上述的至少一封装模穴 220 包含至少一个气孔,以便与外界空气交换,借此可形成空气型封装模 块, 其中, 可以材料填充阻隔气孔,并于黏着封装整体模穴时以填充钝气 或加热去湿气, 借此可形成密封型封装模块的用。 此外, 上述的具有线路 布局的预注成形模穴式立体封装模块更包含至少一第一模穴载板 270A, 该 第一模穴载板 270A的长 ^^于等于该至少一封装模穴 220的开口宽度, 且 上述的第一模穴载板 270更包至少一特定布局的第二线路 210B与至少一 第二导通孔 240B, 该第二线路 210B形成于该第一模穴载板 270A的一表 面上,并经由该至少一第二导通孔 240B于该第一模穴载板 270A的另一表 面上形成至少一个第二信号传输区 250B, 如图 2G所示, 其中, 第二信号 传输区 250B可用以接着焊垫 /锡球等传导物。再者,上述的模穴侧壁 220B 具有至少一步阶以形成具有至少一阶台 225 的阶梯状表面于该容置空间 220C中, 如图 2C所示, 且上述的至少一第一模穴载板 270A可容置于该 阶台 225上, 以密合该容置空间 220C。 此外, 上述的至少一封装模穴 220 的该容置空间 220C可填充一低应力的液态材料以保护内部组件与焊线。
请参阅图 2H图所示, 据本发明的实施例, 上述的具有线路布局的 预注成形模穴式立体封装模块 200更包含 U型封装模穴 200A/200B、 一对 外观相互对称的对称型封装模穴 200E/200F、 H型封装模穴 200C/200D, 其中,该具有线路布局的预注成形模穴式立体封装模块 200的封装方式可 选择上述样态的一或其任意组合。 此外, 上述的 H型封装模穴 200C/200D 更包含相对两开口与两 H 型封装模穴载板, 且上述的对称型封装模穴 200E/200F 更包含至少一对称型封装模穴载板。 如上所述,本发明的组合 是为空间迭架的概念,如同积木的架构,此与传统的层架概念大为不同,例 如, 本发明可视需求采用不同模穴组合, 如: 200B/200C/200B、 200A/200C/200A等方式, 其运用组合的示意图如图 21所示。请参阅图 2J 所示, 则为本发明应用变形的一, 其单一封装模穴的模穴侧壁上具有多阶 台结构, 且搭配各适当尺寸的模穴载板予以搭载。
根据本发明的实施例,本发明的立体式封装或模块结构的模穴载板可 直接当成 PCB或 PVB , 因此本发明不仅可借由内部基板或印刷电路板作为 延展,还可借由相似且不同模块的模穴式基板焊接于基本的模块基板上进 行延展,如图 2K所示。 图 2K图的应用是以同一封装模块中具有不同厚度 的多数个封装模穴,各模穴的间可借由模穴侧壁上的线路直接 # ^而 it因 此, 能轻易地达成本发明的封装微缩化的应用目标, 其中, 每一封装模穴 区均能搭载一适用的模穴载板予以封装完全, 如图 2L所示, 上述的模穴 载板亦能以单一载板封装多数个模穴区。
根据本发明的实施例,图 3A图至图 3D图所示是为本发明实作的黑白 相片,其实现线路布局可设计于封装模穴的侧壁上,本发明的线路连接方 式可经由侧墙并不受平面的限制。 本发明亦实现了未封装组件得以直 接于封装模块中进行打线制造工艺。显然地,依照上面实施例中的描述,本发 明可能有许多的修正与差异。因此需在其附加的权利请求项的范围内加以 理解, 除上述详细描述外, 本发明还可以广泛地在其它的实施例中施行。
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式 上的限制,虽然本发明已以较佳实施例揭露如上, 然而并非用以限定本发 明,任何熟悉本专业的技术人员 ,在不脱离本发明技术方案范围内,当可利 用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例,但 凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例 所作的任何简单修改、等同变 ^^ , i物属于本发明技术方案的范围内。
工业应用 *!·生
本发明的立体式封装或模块结构是由预先成型的模穴式载板组成,并 且预先成型模穴载板的墙与垂直面间具有一含 30以上的夹角。 本发明的 立体式封装或模块结构的底部与側墙的交界处是圆弧的形状,以利于电路 布局的线路制作。本发明的立体式封装或模块结构外观可提供保护功能,并 且已封装或未封装组件仍可被保护于此立体式封装或模块结构内。 ^h,该 立体式封装或模块结构的外部可提供一平坦区域以供激光或油墨盖印,以 便于追踪整体模块封装日期。再者, 本发明的架构可提供焊垫或锡球做为 输出电极, 并借由底部穿孔预先制作测试焊垫, 以便于生产期间, 提供内 部组件功能测试, 如此即可提高产量。
Claims
1、 一种预注成形模穴式立体封装模块, 其特征在于该预注成形模穴 式立体封装模块包括:
至少一特定布局的第一线路; 与
至少一封装模穴, 该至少一封装模穴的模穴表面具有该第一线路, 且 该至少一封装模穴是借由一模穴底部与环绕该模穴底部的一模穴侧壁形 成一容置空间, 其中, 该模穴侧壁是与该模穴底部的垂直轴向形成大于 3° 的倾斜角, 且该容置空间可用以置入至少一组件以便与该第一线路电 性耦合。
2、 根据权利要求 1所述的预注成形模穴式立体封装模块, 其特征在 于上述的模穴侧壁与该模穴底部交界处是为一弧状交界区以便于该第一 线路自该模穴底部经由该弧状交界区形成至该模穴侧壁上。
3、 根据权利要求 2所述的预注成形模穴式立体封装模块, 其特征在 于上述的弧状交界区的侧壁底端形成高度不一的步阶,以便于不同的垂直 平面上进行交错式焊线布局或打线制造工艺。
4、 根据权利要求 1所述的预注成形模穴式立体封装模块, 其特征在 于上述的至少一封装模穴包含至少一第一导通孔,以便该第一线路经该第 一导通孔与外部电性耦合。
5、 根据权利要求 1所述的预注成形模穴式立体封装模块, 其特征在 于上述的至少一封装模穴的外部表面包含至少一个信号传输区,该至少一 个信号传输区经由该第一导通孔的该第一线路电性耦合以传输内外信号。
6、 根据权利要求 5所述的预注成形模穴式立体封装模块, 其特征在 于上述的至少一个信号传输区可为模块测试区。
7、 根据权利要求 1所述的预注成形模穴式立体封装模块, 其特征在 于上述的至少一封装模穴包含至少一个散热通道, 以便于散热, 其中, 该 至少一个散热通道可于封装模穴的外表面外露至少一散热区。
8、 根据权利要求 1所述的预注成形模穴式立体封装模块, 其特征在 于上述的至少一封装模穴包含至少一个气孔, 以便与外界空气交换,借此 可形成空气型封装模块, 其中, 可以材料填充阻隔该气孔, 并于组装该封 装模穴时以填充钝气或加热去湿气, 借此可形成密封型封装模块之用。
9、 根据权利要求 1所述的预注成形模穴式立体封装模块, 其特征在
于上述的具有线路布局的预注成形模穴式立体封装模块更包含至少一第 一模穴载板,该第一模穴载板的长度大于等于该至少一封装模穴的开口宽 度。
10、根据权利要求 9所述的预注成形模穴式立体封装模块, 其特征在 于上述的第一模穴载板更包含至少一特定布局的第二线路与至少一笫二 导通孔,该第二线路形成于该第一模穴载板的一表面上并经由该第二导通 孔于该第一模穴载板的另一表面上形成至少一信号传输区。
11、根据权利要求 1所述的预注成形模穴式立体封装模块, 其特征在 于上述的模穴侧壁具有至少一步阶以形成具有至少一阶台的阶梯状表面 于该容置空间中。
12、根据权利要求 1所述的预注成形模穴式立体封装模块,其特征在 于上述的具有线路布局的预注成形模穴式立体封装模块更包含至少一第 二模穴载板容置该阶台上。
13、 根据权利要求 12所述的预注成形模穴式立体封装模块, 其特征 在于上述的第二模穴载板更包至少一特定布局的第三线路与至少一第三 导通孔,该第三线路形成于该第二模穴载板的一表面上, 并经由该至少一 第三导通孔于该第二模穴载板的另一表面上形成电性耦合区。
14、根据权利要求 1所述的预注成形模穴式立体封装模块,其特征在 于上述的至少一封装模穴的该容置空间可填充一低应力的液态材料以保 护内部组件与焊线。
15、根据权利要求 1所述的预注成形模穴式立体封装模块,其特征在 于该预注成形模穴式立体封装模块更包含 U型封装模穴、一对外^ i互对 称的对称型封装模穴、 H型封装模穴, 其中, 该预注成形模穴式立体封装 模块的封装方式可选择上述结构的一或其任意组合。
16、 根据权利要求 15所述的预注成形模穴式立体封装模块, 其特征 在于上述的 H型封装模穴更包含相对两开口与两 H型封装模穴载板。
17、 根据权利要求 15所述的预注成形模穴式立体封装模块, 其特征 在于上述的对称型封装模穴更包含至少一对称型封装模穴载板。
18、一种预注成形模穴式立体封装模块, 其特征在于该预注成形模穴 式立体封装模块包含:
一封装模块, 该封装模块具有多数个封装模穴,每个封装模穴借由一 模穴底部与环绕该模穴底部的一模穴側壁形成一容置空间以置入至少一
组件, 其中, 该模穴侧壁是与该模穴底部的垂直轴向形成大于 3° 的倾斜 角,且该模穴侧壁与该模穴底部交界处是为一弧状交界区以便于形成该至 少一特定布局的线路于该弧状交界区;
至少一特定布局的第一线路,该第一线路形成并绕行于该模穴侧壁的 表面以电性耦合各封装模穴内部的该组件; 与
至少一模穴载板, 用以封装每个该封装模穴。
19、 根据权利要求 18所述的预注成形模穴式立体封装模块, 其特征 在于上述的弧状交界区的侧壁底端形成高度不一的步阶,以便于不同的垂 直平面上进行交错式焊线布局或打线制造工艺。
20、 根据权利要求 18所述的预注成形模穴式立体封装模块, 其特征 在于上述的封装模块包含至少一第一导通孔,以便于该第一线路经由该第 一导通孔与外部电性耦合。
21、 根据权利要求 20所述的预注成形模穴式立体封装模块, 其特征 在于上述的封装模块的外部表面包含至少一个信号传输区,该至少一个信 号传输区经由该第一导通孔的该第一线路电性耦合以传输内外信号。
22、 根据权利要求 21所述的预注成形模穴式立体封装模块, 其特征 在于上述的至少一个信号传输区可为至少一封装模块测试区。
23、 根据权利要求 18所述的预注成形模穴式立体封装模块, 其特征 在于上述的封装模块包含至少一个散热通道, 以便于散热, 其中, 该至少 一个散热通道可于封装模穴的外表面外露至少一散热区。
24、 根据权利要求 18所述的预注成形模穴式立体封装模块, 其特征 在于上述的封装模块包含至少一个气孔, 以便与外界空气交换,借此可形 成空气型封装模块, 其中, 可以材料填充阻隔该气孔, 并于组装该封装模 块时以填充钝气或加热去湿气, 借此可形成密封型封装模块的用。
25、 根据权利要求 18所述的预注成形模穴式立体封装模块, 其特征 在于上述的模穴载板更包至少一特定布局的第二线路与至少一第二导通 孔,该第二线路形成于该模穴载板的一表面上, 并经由该至少一第二导通 孔于该模穴载板的另一表面上形成电性耦合区。
26、 根据权利要求 18所述的预注成形模穴式立体封装模块, 其特征 在于上述的模穴側壁具有至少一步阶以形成具有至少一阶台的阶梯状表 面, 且该至少一阶台可用以承载该模穴载板。
27、 根据权利要求 18所述的预注成形模穴式立体封装模块, 其特征
在于上述的容置空间可填充一低应力的液态材料以保护内部组件与焊线。
28、 根据权利要求 18所述的预注成形模穴式立体封装模块, 其特征 在于上述的多数个模穴分别具有不同厚度的该模穴底部。
29、一种预注成形模穴式立体封装模块, 其特征在于该预注成形模穴 式立体封装模块包括:
一封装模穴 ,该封装模穴是借由一模穴底部与环绕该模穴底部的一模 穴側壁形成一容置空间, 其中, 该模穴側壁是与该模穴底部的垂直轴向形 成大于 3° 的倾斜角, 且该模穴侧壁与该模穴底部交界处是为一弧状交界 区,且该模穴侧壁具有多数个步阶以形成具有多数个阶台的阶梯状表面于 该容置空间中;
多数个特定布局的第一线路,形成于该容置空间中的该封装模穴的表 面上, 且该第一线路可形成于该弧状交界区, 其中, 该第一线路可与置入 该容置空间的组件电性耦合; 与
多数个封装载板, 可分别承载于该多数个阶台上, 且该多数个封装载 板分别具有组件于其表面上。
30、 根据权利要求 29所述的预注成形模穴式立体封装模块, 其特征 在于上述的弧状交界区的侧壁底端形成高度不一的步阶,以便于不同的垂 直平面上进行交错式焊线布局或打线制造工艺。
31、 根据权利要求 29所述的预注成形模穴式立体封装模块, 其特征 在于上述的封装模穴包含多数个第一导通孔,以便该第一线路经由该第一 导通孔与外部电性耦合。
32、 根据权利要求 31所述的预注成形模穴式立体封装模块, 其特征 在于上述的封装模穴的外部表面包含多数个信号传输区,该信号传输区经 由该第一导通孔的该第一线路电性耦合以传输内外信号。
33、 根据权利要求 32所述的预注成形模穴式立体封装模块, 其特征 在于上述的信号传输区可为模块测试区。
34、 根据权利要求 29所述的预注成形模穴式立体封装模块, 其特征 在于上述的多数个封装载板具有多数个第二导通孔与多数个特定布局的 第二线路, 该多数个第二线路分别形成于该多数个封装载板的表面上, 并 经由该多数个第二导通孔电性耦合该封装载板的两表面的组件。
35、 根据权利要求 29所述的预注成形模穴式立体封装模块, 其特征 在于上述的封装模穴包含至少一个散热通道, 以便于散热, 其中, 该至少
一个散热通道可于封装模穴的外表面外露至少一散热区。
36、 根据权利要求 29所述的预注成形模穴式立体封装模块, 其特征 在于上述的封装模穴包含至少一个气孔, 以便与外界空气交换,借此可形 成空气型封装模块, 其中, 可以材料填充阻隔该气孔, 并于组装该封装模 穴时以填充钝气或加热去湿气, 借此可形成密封型封装模块的用。
37、 根据权利要求 29所述的预注成形模穴式立体封装模块, 其特征 在于上述的封装模穴的该容置空间可填充一低应力的液态材料以保护内 部组件与焊线。
38、一种预注成形模穴式立体封装模块, 其特征在于该预注成形模穴 式立体封装模块包括:
多数个封装模穴,每一个该封装模穴是借由一模穴底部与环绕该模穴 底部的一模穴侧壁分别形成一容置空间, 其中, 该模穴側壁是与该模穴底 部的垂直轴向形成大于 3° 的倾斜角, 且该模穴侧壁与该模穴底部交界处 是为一弧状交界区;
多数个封装模穴更包括一第一封装模穴、一第二封装模穴、一第三封 装模穴与一第四封装模穴,其中该第二封装模穴与该第三封装模穴的外观 是相互对称且开口尺寸大于该第一封装模穴的该模穴侧壁以分别组成于 该模穴侧壁上,且该第四封装模穴的开口口径小于该第一封装模穴的模穴 底部以组成于该第一封装模穴的模穴底部上,且该第一封装模穴的该模穴 侧壁具有多数个步阶以形成具有多数个阶台的阶梯状表面于该容置空间 中;
多数个特定布局的第一线路,分别形成于该容置空间中的该封装模穴 的表面上, 且该第一线路可形成于该孤状交界区, 其中, 该第一线路可与 置入该容置空间的组件电性耦合; 与
多数个封装载板, 可分别承载于该多数个阶台上, 且该多数个封装载 板分别具有组件于其表面上。
39、 根据权利要求 38所述的预注成形模穴式立体封装模块, 其特征 在于上述的弧状交界区的侧壁底端形成高度不一的步阶,以便于不同的垂 直平面上进行交错式焊线布局或打线制造工艺。
40、 根据权利要求 38所述的预注成形模穴式立体封装模块, 其特征 在于上述的多数个封装模穴包含多数个第一导通孔,以便于该第一线路经 由该第一导通孔与外部电性耦合。
41、 根据权利要求 40所述的预注成形模穴式立体封装模块, 其特征 在于上述的多数个封装模穴的外部表面包含多数个信号传输区,该多数个 信号传输区经由该第一导通孔的该第一线路电性耦合以传输内外信号。
42、 根据权利要求 41所述的预注成形模穴式立体封装模块, 其特征 在于上述的多数个信号传输区为模块测试区。
43、 根据权利要求 38所述的预注成形模穴式立体封装模块, 其特征 在于上述的多数个封装载板具有多数个第二导通孔与多数个特定布局的 第二线路, 该多数个第二线路分別形成于该多数个封装载板的表面上, 并 经由该多数个第二导通孔电性耦合该封装载板的两表面的组件。
44、 根据权利要求 38所述的预注成形模穴式立体封装模块, 其特征 在于上述的封装模穴包含至少一个散热通道, 以便于散热, 其中, 该至少 一个散热通道可于封装模穴的外表面外露至少一散热区。
45、 根据权利要求 38所述的预注成形模穴式立体封装模块, 其特征 在于上述的封装模穴包含至少一个气孔, 以便与外界空气交换,借此可形 成空气型封装模块, 其中, 可以材料填充阻隔该气孔, 并于组装该封装模 穴时以填充钝气或加热去湿气, 借此可形成密封型封装模块的用。
46、 根据权利要求 38所述的预注成形模穴式立体封装模块, 其特征 在于上述的封装模穴的该容置空间可填充一氐应力的液态材料以保护内 部组件与焊线。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2012/000771 WO2013181768A1 (zh) | 2012-06-06 | 2012-06-06 | 具有线路布局的预注成形模穴式立体封装模块 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2012/000771 WO2013181768A1 (zh) | 2012-06-06 | 2012-06-06 | 具有线路布局的预注成形模穴式立体封装模块 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013181768A1 true WO2013181768A1 (zh) | 2013-12-12 |
Family
ID=49711255
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2012/000771 WO2013181768A1 (zh) | 2012-06-06 | 2012-06-06 | 具有线路布局的预注成形模穴式立体封装模块 |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2013181768A1 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107230641A (zh) * | 2016-03-24 | 2017-10-03 | 英飞凌科技股份有限公司 | 具有嵌入导电层和增强密封的模制腔封装体 |
CN107785275A (zh) * | 2017-11-23 | 2018-03-09 | 昌微系统科技(上海)有限公司 | 一种微器件的封装方法及利用该方法封装的微器件 |
CN110497473A (zh) * | 2019-07-26 | 2019-11-26 | 深圳市三利谱光电科技股份有限公司 | 一种异形刀模及其制备方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7262082B1 (en) * | 2000-10-13 | 2007-08-28 | Bridge Semiconductor Corporation | Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture |
CN101150081A (zh) * | 2006-09-21 | 2008-03-26 | 日月光半导体制造股份有限公司 | 立体式封装结构及其制造方法 |
CN101330075A (zh) * | 2007-06-20 | 2008-12-24 | 乾坤科技股份有限公司 | 立体封装结构 |
CN101996955A (zh) * | 2009-08-19 | 2011-03-30 | 精材科技股份有限公司 | 芯片封装体及其制造方法 |
CN102034778A (zh) * | 2009-10-07 | 2011-04-27 | 精材科技股份有限公司 | 芯片封装体及其制造方法 |
-
2012
- 2012-06-06 WO PCT/CN2012/000771 patent/WO2013181768A1/zh active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7262082B1 (en) * | 2000-10-13 | 2007-08-28 | Bridge Semiconductor Corporation | Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture |
CN101150081A (zh) * | 2006-09-21 | 2008-03-26 | 日月光半导体制造股份有限公司 | 立体式封装结构及其制造方法 |
CN101330075A (zh) * | 2007-06-20 | 2008-12-24 | 乾坤科技股份有限公司 | 立体封装结构 |
CN101996955A (zh) * | 2009-08-19 | 2011-03-30 | 精材科技股份有限公司 | 芯片封装体及其制造方法 |
CN102034778A (zh) * | 2009-10-07 | 2011-04-27 | 精材科技股份有限公司 | 芯片封装体及其制造方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107230641A (zh) * | 2016-03-24 | 2017-10-03 | 英飞凌科技股份有限公司 | 具有嵌入导电层和增强密封的模制腔封装体 |
CN107230641B (zh) * | 2016-03-24 | 2020-11-17 | 英飞凌科技股份有限公司 | 具有嵌入导电层和增强密封的模制腔封装体 |
CN107785275A (zh) * | 2017-11-23 | 2018-03-09 | 昌微系统科技(上海)有限公司 | 一种微器件的封装方法及利用该方法封装的微器件 |
CN107785275B (zh) * | 2017-11-23 | 2024-01-26 | 宁卡赛科技(上海)有限公司 | 一种微器件的封装方法及利用该方法封装的微器件 |
CN110497473A (zh) * | 2019-07-26 | 2019-11-26 | 深圳市三利谱光电科技股份有限公司 | 一种异形刀模及其制备方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101019793B1 (ko) | 반도체 장치 및 그 제조 방법 | |
KR100493063B1 (ko) | 스택 반도체 칩 비지에이 패키지 및 그 제조방법 | |
US7294928B2 (en) | Components, methods and assemblies for stacked packages | |
US6492726B1 (en) | Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection | |
TWI469309B (zh) | 積體電路封裝系統 | |
TWI505420B (zh) | 覆晶、面向上型及面向下型中心接合記憶體導線接合總成 | |
US7883936B2 (en) | Multi layer low cost cavity substrate fabrication for PoP packages | |
TWI495082B (zh) | 多層半導體封裝 | |
JP5346578B2 (ja) | 半導体アセンブリおよびその作製方法 | |
US9412714B2 (en) | Wire bond support structure and microelectronic package including wire bonds therefrom | |
TWI501373B (zh) | 具線路佈局之預注成形模穴式立體封裝模組 | |
US8269329B2 (en) | Multi-chip package | |
KR101227792B1 (ko) | 비대칭적으로 배열된 다이 및 몰딩을 포함하는 멀티패키지 모듈 | |
TWI416700B (zh) | 晶片堆疊封裝結構及其製造方法 | |
JP2007243196A (ja) | 複数のチップ構成を有する集積デバイス及びその製造方法 | |
WO2013181768A1 (zh) | 具有线路布局的预注成形模穴式立体封装模块 | |
US10515883B2 (en) | 3D system-level packaging methods and structures | |
US20090032946A1 (en) | Integrated circuit | |
KR100996982B1 (ko) | 다중 다이 집적회로 패키지 | |
TWI748189B (zh) | 系統模組封裝結構及系統模組封裝方法 | |
JP2003133516A (ja) | 積層型半導体装置 | |
WO2018072424A1 (zh) | 一种多芯片框架封装结构及其制造方法 | |
KR20240149904A (ko) | 집적 패키지 디바이스, 그 제조 방법 및 메모리 시스템 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12878606 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 12878606 Country of ref document: EP Kind code of ref document: A1 |