TWI505420B - 覆晶、面向上型及面向下型中心接合記憶體導線接合總成 - Google Patents

覆晶、面向上型及面向下型中心接合記憶體導線接合總成 Download PDF

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TWI505420B
TWI505420B TW101114247A TW101114247A TWI505420B TW I505420 B TWI505420 B TW I505420B TW 101114247 A TW101114247 A TW 101114247A TW 101114247 A TW101114247 A TW 101114247A TW I505420 B TWI505420 B TW I505420B
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Taiwan
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microelectronic
assembly
component
edge
lead
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TW101114247A
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English (en)
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TW201248812A (en
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Belgacem Haba
Richard Dewitt Crisp
Wael Zohni
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Tessera Inc
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Description

覆晶、面向上型及面向下型中心接合記憶體導線接合總成
本發明係關於堆疊式微電子總成及製作此等總成之方法，且係關於此等總成中有用之總成。
本申請案主張在2011年4月21號提出申請之美國臨時專利申請案序列號61/477,967及在2011年11月29日提出申請之美國專利申請案序列號13/306,099之申請日期之權益，該等專利申請案之揭示內容藉此以引用方式併入本文中。以下共同擁有之申請案藉此以引用方式併入本文中：均在2011年4月21日提出申請之美國臨時專利申請案序列號61/477,820、61/477,877及61/477,883。
將半導體晶片共同提供為個別的經預封裝之單元。一標準晶片具有一扁平矩形主體，該扁平矩形主體具有帶有連接至該晶片之內部電路的觸點之一大的前面。每一個別晶片通常安裝於一封裝中，該封裝又安裝於一電路面板(諸如一印刷電路板)上且將該晶片之觸點連接至電路面板之導體。在諸多習用設計中，該晶片封裝佔據相當大於該晶片自身之面積之電路面板之一面積。如在本發明中參考具有一前面之一扁平晶片所使用，應將「晶片之面積」理解為參考該前面之面積。在「覆晶」設計中，該晶片之前面面對一封裝基板(亦即，晶片載體)之面且該晶片上之觸點藉由焊料球或其他連接元件直接接合至該晶片載體之觸點。晶片載體又可透過上覆於該晶片之前面上之端子接合 至一電路面板。「覆晶」設計提供一相對緊密配置；每一晶片佔據等於或稍微大於晶片之前面之面積的電路面板之一面積，諸如(例如)共同受讓之美國專利5,148,265號；5,148,266號；及5,679,977號之某些實施例中所揭示，該等美國專利之全部揭示內容以引用之方式併入本文中。
某些新穎安裝技術提供接近或等於習用覆晶接合之緊密性之緊密性。可在等於或稍微大於晶片自身之面積之電路面板之一面積中容納一單個晶片之封裝通常稱作「晶片大小之封裝」。
除了最小化微電子總成所佔據之電路面板之平面面積之外，亦期望產生垂直於該電路面板之平面呈現一低的總高度或尺寸之一晶片封裝。此等薄微電子封裝允許緊靠近鄰近結構而放置其中安裝有該等封裝之一電路面板，從而產生併入該電路面板之產品之總大小。已改進了各種提議以用於在一單個封裝或模組中提供複數個晶片。在習用「多晶片模組」中，該等晶片並排地安裝於一單個封裝基板上，該單個封裝基板又可安裝至該電路面板。此方法僅提供該等晶片所佔據之電路面板之總計面積之有限減少。該總計面積仍大於該模組中個別晶片之總表面積。
亦已提出以一「堆疊」配置(亦即，其中複數個晶片放置於彼此頂部上之一配置)封裝複數個晶片。在一堆疊式配置中，數個晶片可安裝於小於該等晶片之總面積之電路面板之一面積中。舉例而言，前述美國專利5,679,977號；5,148,265號；及美國專利5,347,159號之某些實施例中揭示 了某些堆疊式晶片配置，該等美國專利之全部揭示內容以引用方式併入本文中。亦以引用方式併入本文中之美國專利4,941,033號揭示其中晶片堆疊於彼此之頂部上且藉由與該等晶片相關聯之所謂的「佈線膜」上之導體彼此互連之一配置。
儘管此項技術中有此等嘗試，但在晶片具有定位於該等晶片之實質上中心區中之觸點之多晶片封裝之情形中將期望進一步改良。某些半導體晶片(諸如某些記憶體晶片)通常經製作而具有實質上沿該晶片之一中心軸線定位之一或兩列觸點。
本發明係關於微電子總成及其製造方法。根據本發明之一態樣，一微電子總成可包括：一基板，其具有對置面對之第一表面及第二表面及在該第一表面與該第二表面之間延伸之一孔口；一第一微電子元件，其具有面對該基板之該第一表面之一前表面；及一第二微電子元件，其具有面對該第一微電子元件之一前表面。該基板可具有曝露於其該第二表面處之第一端子。該第一微電子元件亦可具有遠離該前表面之一後表面及在該前表面與該後表面之間延伸之一邊緣。該第一微電子元件可具有毗鄰該第一微電子元件之邊緣曝露於其前表面處之複數個觸點。該第二微電子元件可具有第一及第二對置邊緣。該第二微電子元件之前表面可在該第一邊緣與該第二邊緣之間延伸。
該第二微電子元件可具有安置於遠離該第一邊緣及該第 二邊緣之其該前表面之一中心區中之複數個觸點。該第二微電子元件之該前表面可突出超過該第一微電子元件之邊緣。該微電子總成亦可包括將該第一微電子元件之觸點電連接至第一端子之第一引線及將該第二微電子元件之觸點連接至該等第一端子之第二引線。該等第一引線及該等第二引線可具有與孔口對準之部分。該微電子總成亦可包括曝露於與該基板之該第二表面對置之該微電子總成之一表面處之第二端子。該等第二端子中之至少某些端子可上覆於該等微電子元件中之至少一者上。
在一項實施例中，該等第二端子中之至少某些端子可藉由導線接合而與曝露於該基板之該第一表面處之導電元件電連接。在一特定實例中，該微電子總成亦可包括至少部分覆蓋該第一微電子元件及該第二微電子元件以及該等導線接合之至少部分之一囊封劑。曝露該等第二端子之該微電子總成之表面可係該囊封劑之一表面。在一項實例中，該等導線接合可具有附接至該等導電元件之基底及遠離該等導電元件之未經囊封之端表面，以及在基底與未經囊封之端表面之間延伸之邊緣表面。未經囊封之端表面可不被囊封劑覆蓋。該等第二端子可與未經囊封之端表面電連接。在一實例性實施例中，該等導線接合中之至少一者之一邊緣表面之至少一部分可未經囊封且該等第二端子中之至少一者可與該等導線接合中之至少一者之未經囊封之邊緣表面及未經囊封之端表面電連接。
在一特定實施例中，該等導線接合可具有介於附接至該 等導電元件之導線接合之基底與遠離該等導電元件之導線接合之端之間的未經囊封之邊緣表面。該等第二端子可與未經囊封之邊緣表面電連接。在一項實施例中，該等微電子元件中之至少一者可包括一揮發性隨機存取記憶體(RAM)，且該等微電子元件中之至少一者可包括非揮發性快閃記憶體。在一實例性實施例中，該微電子總成亦可包括將該第一微電子元件之觸點與該第二微電子元件之觸點電互連之第三引線。該等第一引線、該等第二引線及該等第三引線可具有與孔口對準之部分。在一項實例中，該等第一引線或該等第二引線中之至少一者可包括自該第一微電子元件或該第二微電子元件中之至少一者之觸點延伸之導線接合。
在一特定實例中，與該孔口對準之該等第一引線與該等第二引線中之至少一者之部分可係具有沿該基板延伸至該等端子之第二部分之單體式導電元件之部分。在一實例性實施例中，該微電子總成亦可在該第二微電子元件之前表面與該基板之第一表面之間包括一間隔元件。在一項實例中，該第一微電子元件可包括經組態以主要執行一邏輯功能之一晶片。在一特定實施例中，該第二微電子元件可具有經組態以除任一其他功能外還提供記憶體儲存陣列功能之大量主動裝置。在一項實施例中，該第一微電子元件可具有經組態以除任一其他功能外還提供記憶體儲存陣列功能之大量主動裝置。在一實例性實施例中，該微電子總成亦可包括將該第一微電子元件之觸點電連接至該等端子之 第三引線。該等第一引線及該等第三引線可連接至該孔口之對置側上之端子。該等第一引線、該等第二引線及該等第三引線可具有與孔口對準之部分。
在一項實例中，該微電子總成亦可包括安置於該基板之第一表面與該第二微電子元件之前表面之間的一第三微電子元件，將該第三微電子元件之觸點電連接至該等端子之第三引線，及將該第一微電子元件及該第三微電子元件之該等觸點電互連之第四引線。該第三微電子元件可具有第一及第二對置邊緣，在該第一邊緣與該第二邊緣之間延伸之一前表面，以及毗鄰其第一邊緣而安置於其前表面上之複數個觸點。該第三微電子元件之前表面可面對該基板之該第一表面。該第一微電子元件及該第三微電子元件之該等觸點可位於該孔口之對置側上。該等第一引線、該等第二引線、該等第三引線及該等第四引線可具有與孔口對準之部分。在一實例性實施例中，該微電子總成亦可包括將該第一微電子元件及該第二微電子元件之觸點電互連之第五引線。在一特定實施例中，該微電子總成亦可包括將該第二微電子元件及該第三微電子元件之觸點電互連之第六引線。
在一項實施例中，一微電子總成可包括如上文所闡述之第一微電子總成及第二微電子總成。該第一微電子總成可至少部分地上覆於該第二微電子總成上。該第一微電子總成之第一端子可與該第二微電子總成之第二端子連結。在一實例性實施例中，該等第一微電子元件中之至少一者可 主要經組態以執行一邏輯功能。該等第二微電子元件中之至少一者可具有經組態以除任一其他功能外還提供記憶體儲存陣列功能之大量主動裝置。在一特定實施例中，該第一微電子總成之第一端子中之至少某些端子及該第二微電子總成之第二端子中之至少某些端子可配置成一面積陣列(area array)。可藉由係一接合金屬之導電塊之連結單元來連結該第一微電子總成與該第二微電子總成。
在一實例性實施例中，該等微電子總成可透過毗鄰微電子總成之一周邊而配置之連結單元彼此電連接。在一項實例中，該等連結單元可位於該微電子總成之一稀疏中心區(depopulated central region)外部。在一特定實例中，一系統可包括如上文所闡述之一微電子總成及電連接至該微電子總成之一或多個其他電子總成。在一特定實施例中，該等端子中之至少某些端子可電連接至一電路面板。在一項實例中，該系統亦可包括一外殼、該微電子總成及安裝至該外殼之其他電子總成。
根據本發明之另一態樣，一微電子總成可包括：一基板，其具有對置面對之第一表面及第二表面及在該第一表面與該第二表面之間延伸之一孔口；一第一微電子元件，其具有面對該基板之該第一表面之一前表面；及一第二微電子元件，其具有面對該第一微電子元件之一前表面。該基板可具有端子。該第一微電子元件亦可包括遠離該前表面之一後表面及在該前表面與該後表面之間延伸之一邊緣。該第一微電子元件可具有毗鄰該第一微電子元件之邊 緣曝露於其前表面處之複數個觸點。該第二微電子元件可具有第一及第二對置邊緣。該第二微電子元件之前表面可在該第一邊緣與該第二邊緣之間延伸。
該第二微電子元件可具有安置於遠離該第一邊緣及該第二邊緣之其該前表面之一中心區中之複數個觸點。該第二微電子元件之該前表面可突出超過該第一微電子元件之邊緣。該微電子總成亦可包括將該第一微電子元件之觸點電連接至該等端子之第一引線，將該第二微電子元件之觸點連接至該等端子之第二引線，及將該第一微電子元件之觸點與該第二微電子元件之觸點電互連之第三引線。該等第一引線、該等第二引線及該等第三引線可具有與孔口對準之部分。
在一實例性實施例中，該等第一引線或該等第二引線中之至少一者可包括自該第一微電子元件或該第二微電子元件中之至少一者之觸點延伸之導線接合。在一項實施例中，與該孔口對準之該等第一引線與該等第二引線中之至少一者之部分可係具有沿該基板延伸至該等端子之第二部分之單體式導電元件之部分。在一特定實施例中，該微電子總成亦可在該第二微電子元件之前表面與該基板之第一表面之間包括一間隔元件。在一特定實施例中，該第一微電子元件可包括經組態以主要執行一邏輯功能之一晶片。在一實例性實施例中，該第二微電子元件可具有經組態以除任一其他功能外還提供記憶體儲存陣列功能之大量主動裝置。在一項實施例中，該第一微電子元件可具有經組態 以除任一其他功能外還提供記憶體儲存陣列功能之大量主動裝置。
本發明之另外態樣可提供併入根據本發明之前述態樣之微電子總成連同電連接至其的其他電子總成之系統。舉例而言，該等端子可電連接至一電路面板。在另一實例中，該系統可安置於一單個外殼中及/或安裝至該單個外殼，該單個外殼可係一可攜式外殼。根據本發明之此態樣中之較佳實施例之系統可比相當的習用系統更緊密。
在一項實施例中，一微電子總成可包括如上文所闡述之第一微電子總成及第二微電子總成。該第一微電子總成可與該第二微電子總成電連接且可至少部分地上覆於該第二微電子總成上。在一實例性實施例中，該等微電子總成可透過毗鄰微電子總成之一周邊而配置之連結單元彼此電連接。在一特定實施例中，該等連結單元可位於該微電子總成之一稀疏中心區外部。在一項實施例中，該等微電子元件中之某些微電子元件可包括一揮發性隨機存取記憶體(RAM)，且該等微電子元件中之某些微電子元件可包括非揮發性快閃記憶體。在一特定實施例中，該等第一微電子元件中之至少一者可主要經組態以執行一邏輯功能，且該等第二微電子元件中之至少一者可具有經組態以除任一其他功能外還提供記憶體儲存陣列功能之大量主動裝置。
根據本發明之又另一態樣，一微電子總成可包括：一基板，其具有對置面對之第一表面及第二表面及在該第一表面與該第二表面之間延伸之一孔口；一第一微電子元件， 其具有面對該基板之該第一表面之一前表面；及一第二微電子元件，其具有面對該第一微電子元件之一前表面。該基板可具有端子。該第一微電子元件亦可包括遠離該前表面之一後表面及在該前表面與該後表面之間延伸之一邊緣。該第一微電子元件可具有毗鄰該第一微電子元件之邊緣曝露於其前表面處之複數個觸點。該第二微電子元件可具有第一及第二對置邊緣。該第二微電子元件之前表面可在該第一邊緣與該第二邊緣之間延伸。
該第二微電子元件可具有安置於遠離該第一邊緣及該第二邊緣之其該前表面之一中心區中之複數個觸點。該第二微電子元件之該前表面可突出超過該第一微電子元件之邊緣。該微電子總成亦可包括將該第一微電子元件之觸點電連接至該等端子之第一引線，將該第二微電子元件之觸點連接至該等端子之第二引線，及將該第一微電子元件之觸點電連接至該等端子之第三引線。該等第一引線及該等第三引線可連接至該孔口之對置側上之端子。該等第一引線、該等第二引線及該等第三引線可具有與孔口對準之部分。
在一特定實施例中，該第一微電子元件可包括經組態以主要執行一邏輯功能之一晶片。在一實例性實施例中，該第二微電子元件可具有經組態以除任一其他功能外還提供記憶體儲存陣列功能之大量主動裝置。在一項實施例中，該第一微電子元件可具有經組態以除任一其他功能外還提供記憶體儲存陣列功能之大量主動裝置。
根據本發明之又另一態樣，一微電子總成可包括：一基板，其具有對置面對之第一表面及第二表面及在該第一表面與該第二表面之間延伸之一孔口；一第一微電子元件，其具有面對該基板之該第一表面之一前表面；一第二微電子元件，其具有面對該第一微電子元件之一前表面，及一第三微電子元件，其安置於該基板之第一表面與該第二微電子元件之前表面之間。該基板可具有端子。
該第一微電子元件亦可包括遠離該前表面之一後表面及在該前表面與該後表面之間延伸之一邊緣。該第一微電子元件可具有毗鄰該第一微電子元件之邊緣曝露於其前表面處之複數個觸點。該第二微電子元件可具有第一及第二對置邊緣。該第二微電子元件之前表面可在該第一邊緣與該第二邊緣之間延伸。該第二微電子元件可具有安置於遠離該第一邊緣及該第二邊緣之其該前表面之一中心區中之複數個觸點。該第二微電子元件之該前表面可突出超過該第一微電子元件之邊緣。該第三微電子元件可具有第一及第二對置邊緣，在該第一邊緣與該第二邊緣之間延伸之一前表面，以及毗鄰其第一邊緣而安置於其前表面上之複數個觸點。該第三微電子元件之前表面可面對該基板之該第一表面。
該微電子總成亦可包括將該第一微電子元件之觸點電連接至該等端子之第一引線，將該第二微電子元件之觸點連接至該等端子之第二引線，將該第三微電子元件之觸點電連接至該等端子之第三引線，及將該第一微電子元件及該 第三微電子元件之觸點電互連之第四引線。該第一微電子元件及該第三微電子元件之該等觸點可位於該孔口之對置側上。該等第一引線、該等第二引線、該等第三引線及該等第四引線可具有與孔口對準之部分。
在一項實施例中，該微電子總成亦可包括將該第一微電子元件及該第二微電子元件之觸點電互連之第五引線。在一特定實施例中，該微電子總成亦可包括將該第二微電子元件及該第三微電子元件之觸點電互連之第六引線。在一特定實施例中，該第一微電子元件可包括經組態以主要執行一邏輯功能之一晶片。在一實例性實施例中，該第二微電子元件可具有經組態以除任一其他功能外還提供記憶體儲存陣列功能之大量主動裝置。在一項實施例中，該第一微電子元件可具有經組態以除任一其他功能外還提供記憶體儲存陣列功能之大量主動裝置。
現在將參考隨附圖式闡述本發明之各種實施例。將瞭解，此等圖式僅繪示本發明之某些實施例且因此不認為其限制本發明之範疇。
參考圖1A及圖2，根據本發明之一實施例之一堆疊式微電子總成10包括以一面向下型姿態面對一基板30之一第一微電子元件12及以一面向下型姿態上覆於第一微電子元件12之至少一部分上之一第二微電子元件14。在某些實施例中，第一微電子元件12及第二微電子元件14可係在其前表面16處具有觸點之一半導體晶片，或包括一半導體晶片之 一元件。該半導體晶片可係一半導體材料(諸如矽或砷化鎵)之一薄板，且可提供為個別預封裝之單元。該半導體晶片可係一半導體材料(諸如矽或砷化鎵)之一薄板，且可將其提供為個別預封裝之單元。該半導體晶片可體現為主動電路元件(例如，電晶體、二極體以及其他)或被動電路元件(諸如電阻器、電容器或電感器以及其他)或主動電路元件與被動電路元件之一組合。在一「主動」半導體晶片中，每一微電子元件中之主動電路元件通常一起電連接成一或多個「積體電路」。該第一微電子元件及該第二微電子元件均電連接至一基板30，如下文所詳細論述。基板30又可透過其一表面處之端子36電連接至一電路面板(諸如一印刷電路板)。在一特定實施例中，微電子總成10可係具有經組態以用於與一電路面板(諸如一印刷電路板)以及其他之一面上之對應觸點電連接之端子之一微電子「封裝」。
在特定實施例中，該基板可係(諸如)聚合材料或無機材料(諸如陶瓷或玻璃)之各種類型之構造之一介電元件，該基板其上具有諸如端子之導電元件及諸如，例如跡線、基板觸點之導電元件或與該等端子電連接之其他導電元件。在另一實例中，該基板可基本上係由一半導體材料(諸如矽)構成，或另一選擇為包括一半導體材料層及其一或多個介電層。此基板可具有小於每攝氏度百萬分之7(ppm/℃)之一熱膨脹係數。在又另一實施例中，該基板可係具有引線指部之一引線框架，其中該等端子可係該 等引線指部之部分，諸如該等引線指部之端部分。在又另一實施例中，該基板可係具有引線之一引線框架，其中該等端子可係該等引線之部分，諸如該等引線之端部分。
第一微電子元件12可包括經主要組態以執行一邏輯功能之一半導體晶片，諸如一微處理器、特殊應用積體電路(「ASIC」)、場可程式化閘陣列(「FPGA」)或其他邏輯晶片，以及其他。在一特定實施例中，微電子元件12可係主要提供邏輯功能但亦可包括一記憶體儲存陣列之一控制器或一系統單晶片(「SOC」)。在其他實例中，第一微電子元件12可包括或可係一記憶體晶片(諸如一快閃(NOR或NAND)記憶體晶片、動態隨機存取記憶體(「DRAM」)晶片或靜態隨機存取記憶體(「SRAM」)晶片)或經主要組態以執行某一其他功能。此記憶體晶片包括一記憶體儲存陣列且通常具有經組態以除該晶片之任一其他功能外還提供記憶體儲存陣列功能之大量主動電路元件(例如，主動裝置，諸如電晶體)。第一微電子元件12具有一前表面16、遠離該前表面之一後表面18及在該前表面與該後表面之間延伸之第一邊緣27及第二邊緣29。電觸點20毗鄰第二邊緣29而曝露於第一微電子元件12之前表面16處。如本發明中所使用，一導電元件「曝露於」一結構之一表面處之一陳述指示該導電元件可用於與在垂直於該表面之一方向上自該結構外部朝向該表面移動之一理論上點接觸。因此，曝露於一結構之一表面處之一觸點、端子或其他導電元件可自此表面突出；可與此表面齊平；或可相對於此表面凹入 且透過該結構中之一孔或凹坑曝露。電觸點20可係接合墊或其他導電結構，諸如凸塊、柱等等。該等接合墊可包括一或多個金屬，諸如銅、鎳、金或鋁，且可厚約0.5 μm。該等接合墊之大小可隨裝置類型而變化，但通常將在一側上量測為數十至數百微米。
第二微電子元件14具有一前表面22、遠離該前表面之一後表面24及在該前表面與該後表面之間延伸之第一邊緣35及第二邊緣37以及曝露於前表面22處之觸點26。如圖1A中所參見，第一微電子元件12與第二微電子元件14相對於彼此堆疊以使得第二微電子元件14之至少一部分上覆於第一微電子元件12之至少一部分上。在一特定實施例中，諸如圖1A中所展示，第二微電子元件14之前表面22包括第一端區21及第二端區23以及在第一端區21與第二端區23之間延伸之一中心區19。第一端區21在中心區19與第一邊緣35之間延伸，且第二端區23在中心區19與第二邊緣37之間延伸。該中心區可延伸第二微電子元件14之第一邊緣35與第二邊緣37之間的距離之三分之一，且該第一端區及第二端區可各自延伸邊緣35、37之間的距離之三分之一。電觸點26曝露於第二微電子元件14之前表面22處。舉例而言，觸點26可毗鄰第一表面22之中心配置成一或兩個平行列。第二微電子元件14可包括或可係一DRAM晶片。此DRAM晶片包括一記憶體儲存陣列且通常具有經組態以除任一其他功能外還提供記憶體儲存陣列功能之大量主動電路元件(例如，主動裝置，諸如電晶體)。第二微電子元件14之中 心區19之至少一部分突出超過第一微電子元件12之第二邊緣29以使得第二微電子元件14之觸點26曝露超過第一微電子元件12之第二邊緣29。如上文所論述，在一項實施例中，基板30可包括具有對置面對之第一表面34及第二表面32之一介電層。一或多個導電元件或端子36曝露於基板30之第二表面32處。在一特定實施例中，端子36中之某些或全部端子可相對於第一微電子元件12及/或第二微電子元件14移動。
基板30進一步包括在其第一對置表面與第二對置表面之間(諸如，例如一介電元件30之對置面對第一表面與第二表面之間)延伸之一或多個孔口。在圖1A中所繪示之實施例中，基板30包括一孔口39且至少某些觸點26與基板30之孔口39對準。複數個引線將第二微電子元件之觸點26與微電子總成之端子36電連接。該等引線具有與孔口39對準之部分。舉例而言，該等引線可包括接合至該等基板觸點之導線接合50，該等基板觸點又透過該等引線(諸如沿一半導體元件或介電元件30延伸之金屬跡線)之其他部分連接至端子36，或若該基板包括一引線框架，則該等引線可包括其引線指部之部分。
介電元件30之第一表面34可與第一微電子元件12之前表面16並列。如圖1A中所參見，基板30可延伸超過第一微電子元件12之第一邊緣27及第二微電子元件14之第二邊緣35。在一實例中，包括一介電材料之一基板可稱作一「介電元件」30，不管部分還是全部係由任一合適介電材料製 成。基板30可部分或全部係由任一合適介電材料製成。舉例而言，基板30可包含一撓性材料層，諸如一個聚醯亞胺層、BT樹脂或共同用於製成膠帶自動接合(「TAB」)膠帶之其他介電材料。另一選擇為，基板30可包含一相對剛性板狀材料，諸如一纖維加固環氧樹脂厚層，諸如Fr-4板或Fr-5板。不管所運用之材料如何，基板30可係由一單個層或多層組成。
返回至圖1A，一間隔元件或支撐元件31可定位於第二微電子元件14之第一端區21與介電元件30之一部分之間。間隔元件31可幫助在基板30上方支撐第二微電子元件。此一間隔元件31可係由(例如)一介電材料(諸如二氧化矽或其他材料)、一半導體材料(諸如矽)或一或多個黏合劑層或其他聚合材料。在一特定實施例中，該間隔元件可包括金屬或可係由金屬製成。若該間隔元件包括黏合劑，則該黏合劑可將第二微電子元件14連接至基板30。在一項實施例中，間隔元件31在實質上垂直於該基板之第一表面34之一垂直方向上可具有與第一微電子元件12在其前表面16與後表面18之間的厚度基本上相同之厚度。若間隔元件31包括一黏合劑，則該黏合劑可將第二微電子元件14連接至介電元件30。
如圖1A及圖2中所參見，基板30亦可包括曝露於第二基板32上之導電元件或基板觸點40及導電跡線25。導電跡線25將基板觸點40電耦合至端子36。跡線25及基板觸點40可係使用共同受讓之美國申請公開案2005/0181544號中所圖 解說明之方法形成，該美國申請公開案之全部揭示內容以引用方式併入本文中。
返回至圖1A，一間隔元件或支撐元件31(諸如一黏合劑層)可定位於第二微電子元件14之第一端區21與基板30之一部分之間。若間隔元件31包括一黏合劑，則該黏合劑可將第二微電子元件14連接至基板30。如圖1A中所展示，第二微電子元件14之第二端區23可藉助一接合材料60(諸如一黏合劑，其可係導熱的)接合至第一微電子元件12之第二端區17。同樣，一接合材料61(例如，視情況導熱之一黏合劑)可將第二微電子元件之第一端區與間隔元件31接合。一接合材料71可安置於第一微電子元件之前表面16之一顯著部分與基板30之第一表面34之一部分之間。在一特定實施例中，接合材料60、61及/或71可部分或全部係由一晶粒附接黏合劑製成，且在一特定實例中可係由一低彈性模數材料(諸如矽樹脂彈性體)構成。然而，在一特定實施例中，若兩個微電子元件12及14係由相同材料形成之習用半導體晶片，則接合材料60、61及/或71可全部或部分係由一高彈性模數黏合劑或焊料製成，此乃因該等微電子元件將往往回應於溫度改變而一致膨脹及收縮。不管所運用之材料如何，間隔元件31可包括一單個層或多層。如下文關於圖4至圖8所詳細論述，間隔元件31可被一或多個微電子元件取代。
參考圖1A及圖2，微電子總成可包括將第一微電子元件之觸點20與至少某些端子36電連接之引線70。引線70具有 與基板30之孔口39對準之部分。在一項實施例中，該等引線可包括延伸穿過孔口39且接合至微電子元件之觸點20、40及基板之接合元件70(諸如導線接合)。跡線(未展示)可沿基板在觸點40與端子36之間延伸。在一個變型中，接合導線70可包括延伸穿過孔口39且電連接至基板觸點40之導線接合72。導線接合72中之每一者將一觸點20電耦合至基板30之一對應基板觸點40。導線接合70可包括於2010年10月19日提出申請且標題為「Enhanced Stacked Microelectronic Assemblies with Central Contacts and Improved Thermal Characteristics」之美國專利申請案12/907,522號中所闡述之一多導線接合結構，該美國專利申請案之全部揭示內容以引用方式併入本文中。如上文所論述且如圖2中所展示，跡線25將基板觸點40電連接至端子36。因此，引線50可包括導線接合52、至少某些基板觸點40及至少某些跡線25。所有此等元件有助於在第一微電子元件12之觸點20與端子36之間建立一電連接。
如圖1B中所參見，另一選擇為或另外，引線(諸如引線接合76)可如展示沿基板30之第一表面34或沿第二表面延伸且延伸至孔口39中以連接至觸點20。引線接合76可電連接至導通體83或自第一表面34延伸至基板30之第二表面32處之一或多個端子36之任一其他類型之導電元件。因此，引線70可包括引線接合76及導通體83。如圖1B中所進一步展示，微電子總成10可包括將第二微電子元件14之觸點26與該基板之第二表面32之基板觸點40電互連之引線接合 85。
微電子總成10進一步包括將第二微電子元件12之觸點26電連接至基板30之第二表面32處之至少某些端子36之引線50。引線50具有與孔口39對準之部分且可包括將第二微電子元件之觸點26電連接至基板30之第二表面32處之基板觸點40之多個導線接合52。導線接合52可延伸穿過孔口39。導線接合52中之每一者將一觸點26電耦合至基板30之一對應基板觸點40。引線50可包括於2010年10月19日提出申請且標題為「Enhanced Stacked Microelectronic Assemblies with Central Contacts and Improved Thermal Characteristics」之美國專利申請案12/907,522號中所闡述之一多導線接合結構，該美國專利申請案之全部揭示內容以引用方式併入本文中。如圖2中所展示，跡線25將基板觸點40電連接至端子36。因此，引線50可包括導線接合52、至少某些基板觸點40及至少某些跡線25。所有此等元件有助於在第二微電子元件14之觸點26與端子36之間建立一電連接。另一選擇為或另外，引線50可包括將觸點26與基板30之第一表面34處或該基板之第二表面32處之某些電基板觸點電耦合之引線接合。該等引線接合不一定延伸穿過基板30之孔口39，而是至少部分與該孔口對準。
微電子總成10可進一步包括覆蓋至少第一微電子元件12及第二微電子元件14之一外模製件或囊封劑11。如圖1A中所參見，外模製件11亦可覆蓋延伸超過第一微電子元件12之第一邊緣27及第二微電子元件14之第一邊緣35之基板30 之部分。因此，外模製件11可至少接觸第一微電子元件12之第一邊緣27，第二微電子元件14之第一邊緣35及基板30之第一表面34。外模製件11可係由任一合適材料(包括環氧樹脂及諸如此類)製成。
微電子總成10可另外包括附接至第一微電子元件12或第二微電子元件14中之一或多者之後表面之一散熱器或散熱片，如於2010年10月19日提出申請且標題為「Enhanced Stacked Microelectronic Assemblies with Central Contacts and Improved Thermal Characteristics」之美國專利申請案12/907,522號中所闡述，該美國專利申請案之全部揭示內容藉此以引用方式併入本文中。在某些實施例中，微電子總成10包括在第一微電子元件12及/或第二微電子元件14之後面18、24中之一或多者處及可能在邊緣表面27、35、37處熱耦合至第一微電子元件12及/或第二微電子元件14之一散熱器。該散熱器可佔據圖1A中所展示之外模製件11所佔據之面積之某些部分。
另外，微電子總成10可進一步包括附接至介電元件30之第二表面32上之端子36之連結單元81。連結單元81可係焊料球或其他接合塊及金屬(例如，錫、銦或其一組合)，且經調適以將微電子總成10連結並電耦合至一電路面板(諸如一印刷電路板)。
如圖1C中所參見，微電子總成10之引線50可另外或替代性地包括電連接第一微電子元件12之至少某些觸點20與位於孔口39之對置側上之至少某些基板觸點40之導線接合 53。因此，導線接合53可橫跨基板30之孔口。另外，引線70可替代性地或另外包括電連接第一微電子元件12之觸點20中之至少某些觸點與第二微電子元件14之觸點26中之至少某些觸點之導線接合73。
圖3A繪示圖1A中所展示之微電子總成10之一變型10'。在此變型中，替代(或除了)表面16'處之觸點20，第一微電子元件12'可包括遠離基板30'而面對之表面18處之觸點20'。此表面18'可係第一微電子元件12'之前面。表面18'可具有毗鄰第一微電子元件12'之第一邊緣27'之一第一端部分82，毗鄰第二邊緣29'之一第二端部分84，及第一端部分82與第二端部分84之間的一中心部分86。觸點20'可安置於毗鄰第一邊緣27'之表面18'之第一端部分82內，表面18'之中心部分86內或第一端部分及中心部分兩者內。在一項實施例中，觸點20'可在表面18'之中心部分86處配置成一或兩個平行列。
微電子總成10'可包括與表面18'處之觸點20'及端子36電連接之引線88。在一項實例中，引線88之部分(諸如導線接合)可延伸超過第一微電子元件12'之第一邊緣27至觸點40'，該等觸點又可(諸如)透過跡線(未展示)或其他導電元件連接至端子。引線88可包括自觸點20'延伸超過第一微電子元件之第一邊緣27'，且至基板30'之第一表面34'處之觸點40'之導線接合90，且可包括該基板之其他導電結構，諸如觸點與端子36之間的導電跡線。如圖3B中所展示，引線部分52'(例如，導線接合)可將微電子元件14'之觸點26連接 至孔口39'之任一側或兩側上之觸點40'。
圖4及圖5繪示圖1A中所展示之微電子總成10之一變型。圖1A中所展示之微電子總成100在具有以一面向上型姿態之一第一微電子元件101方面類似於圖3A中所展示之微電子總成10。在此變型中，以一覆晶姿態之一第三微電子元件112被間隔元件31取代。然而，在所展示之特定視圖中，第一微電子元件101出現在該圖之右邊且第三微電子元件112出現在該圖之左邊。第三微電子元件112在其一前表面116處包括複數個觸點120。第三微電子元件112之觸點120與基板130之第二表面132處之至少某些端子136連接。
覆晶互連件143透過金屬凸塊(例如，諸如焊料之一接合金屬)將第一微電子元件112之前表面116上之電觸點120電連接至基板30之第一表面134上之至少某些觸點141。然後反轉該微電子元件，因此金屬凸塊提供該微電子元件之觸點(例如，接合墊)與該基板之間的電路徑以及該微電子元件至該基板的機械附接。存在覆晶過程之諸多變型，但一個共同組態係針對該等金屬凸塊使用焊料且使用該焊料之熔接作為將其緊固至接合墊及基板之方法。當該焊料融化時，其可流動以形成經截頂球體。
與經由導線接合連接至介電元件之其他微電子元件作比較，該覆晶互連件給第一微電子元件112提供較大數目個(輸入/輸出)I/O。另外，該覆晶互連件最小化第二微電子元件114與基板30之間的導線接合路徑，從而減小該等導 線接合之阻抗。
在圖4及圖5中所繪示之實施例中，倒裝互連件143可包括安置於第一微電子元件112與基板130之間的複數個固體金屬凸塊145(諸如焊料球)。金屬凸塊145可係導電球體或柱。每一固體金屬凸塊145可安置於第一微電子元件112之一觸點120與基板130之一基板觸點141之間(且與其兩者接觸)，從而在電觸點120與導電元件141之間提供電連接。金屬凸塊145可基本上係由連結金屬或任一其他合適材料構成。
一底填充物147可圍繞固體金屬凸塊145以將第一微電子元件112黏附至基板130。底填充物147可特定安置於第一微電子元件112之前表面116與基板130之第一表面134之間以將第一微電子元件112耦合至基板130。舉例而言，底填充147可整體或部分地係由一聚合材料(諸如環氧樹脂)製成。然而在某些實施例中，全部省略底填充147。
圖6圖解說明圖4中所展示之微電子總成100之一變型。微電子總成200類似於微電子總成100，但其不包括將第一微電子元件電連接至基板觸點之一覆晶互連件。而是，第一微電子元件212係以面向上型姿態且包括毗鄰其第一邊緣227之一或多個觸點220平行列。引線270將觸點220電連接至基板230之第二表面236上之端子236。
引線270可包括自觸點220延伸超過第一微電子元件212之第一邊緣227，且至基板230之第二表面234處之基板觸點240之打線272。另外，引線270可包括導通體283或將基 板觸點240與至少某些端子236電連接之任一其他合適導電元件。導通體283可自第一表面234延伸穿過基板230至基板230之第二表面232。
微電子總成200進一步包括將第二微電子元件214之前表面222處之觸點226電連接至至少某些端子236之引線250。引線250之部分與基板230之孔口239對準。在此變型中，引線270包括自觸點226延伸且穿過孔口239之多個導線接合252。導線接合252可電連接至位於基板230之第二表面232處且在孔口239之對置側上之基板觸點240。
圖7繪示圖6中所展示之微電子總成200之一變型。圖7中所展示之微電子總成300實質上類似於圖1A或圖1B中所展示之微電子總成200，其中一第三微電子元件301取代間隔元件31，該第三微電子元件具有類似於第一微電子元件12(圖1A)之電互連件之與該基板之一電互連件。
圖8繪示圖7中所展示之微電子總成300之一變型。在此變型中，展示微電子總成400安裝於諸如電路面板900(諸如一印刷電路板)之一外部總成上，且包括額外電連接或引線。雖然僅圖8圖解說明電安裝於一電路面板(諸如一印刷電路板)上之一微電子總成，但本文中上文所闡述之微電子總成中之任一者可安裝至一電路面板或該微電子總成外部之其他總成。
微電子總成400可包括延伸跨越孔口439且將第一微電子元件412之一觸點320與第三微電子元件401之一觸點490電連接之電連接或引線474。引線474可包括導線接合及/或 引線接合。另一組電連接或引線476可與基板430之孔口439至少部分對準且將第一微電子元件412之至少某些觸點420與第二微電子元件414之至少某些觸點426電連接。引線476可包括導線接合及/或引線接合。又另一組電連接或引線478與基板430之孔口430至少部分對準且將第二微電子元件414之至少某些觸點426與第三微電子元件401之至少某些觸點490電連接。引線478可包括導線接合及/或引線接合。
圖9A展示圖1A中所展示之圖解性側剖面視圖之一堆疊式變型。一微電子總成500可具有堆疊式第一微電子總成510a及第二微電子總成510b(統稱微電子總成510)。微電子總成510可各自係上文參考圖1A到圖8所闡述之微電子總成中之任一者，且該等微電子總成可彼此相同或不同。該堆疊中可存在任一數目個微電子總成510，包括(例如)圖9A中所展示之兩個微電子總成510a及510b。
連結單元581(諸如焊料球)可將第一微電子總成510a與第二微電子總成510b彼此連結並電耦合。此等連結單元581可附接至曝露於第一微電子總成510a之基板530之第二表面532處之端子536及曝露於第二微電子總成510b之基板530之第一表面534處之端子536'。包括堆疊式微電子總成510之微電子總成500可使用曝露於微電子總成500之一頂部表面501或一底部表面502處之連結單元581而附接至一電路面板(諸如一印刷電路板)。
如圖9B中所展示，微電子總成500可包括毗鄰該微電子 總成之一周邊503而配置之連結單元581。連結單元581可位於微電子總成500之一稀疏中心區590外部。在此一實施例中，連結單元581可經配置以使得其不上覆於微電子總成510之第一微電子元件512及第二微電子元件514上。相比於微電子總成500在中心區590內包括連結單元581之情形，此一實施例可允許複數個微電子總成510在連結在一起時具有一較小堆疊高度。
如圖9A中所展示，微電子總成500可具有至少部分覆蓋微電子總成510之第一微電子元件512及第二微電子元件514之一單個囊封劑511。在此一實施例中，微電子總成510可在沒有一囊封劑之情形下彼此連結，且然後可形成覆蓋經連結之微電子總成內之微電子元件之單個囊封劑511。囊封劑511可覆蓋未經組態以用於與該微電子總成外部之一或多個總成電連接之微電子總成500之部分。
在一替代性實施例中，微電子總成510中之每一者可單獨形成，每一者具有一各別囊封劑，類似於圖10中所展示之實施例。在針對每一微電子總成510具有一單獨形成之囊封劑之此一實施例中，此等經囊封之微電子總成然後可(例如)以諸如圖10中所展示之一組態彼此堆疊並連結，以提供其間的電連通。
在一特定實例中，微電子總成500可經組態以用作(例如)用於一智慧型電話應用之非均質記憶體。在此一實例中，微電子總成510內之微電子元件512及514中之某些微電子元件可包括諸如揮發性RAM之一記憶體儲存元件，且 微電子元件512及514中之某些微電子元件可包括諸如非揮發性快閃記憶體之記憶體儲存元件。
圖10展示圖9A中所展示之圖解性側剖面視圖之一堆疊式變型。一微電子總成600可具有堆疊式第一微電子總成610a及第二微電子總成610b(統稱微電子總成610)。微電子總成610可各自係上文參考圖1A到圖8所闡述之微電子總成中之任一者，且該等微電子總成可彼此相同或不同。該堆疊中可存在任一數目個微電子總成610，包括(例如)圖9A中所展示之兩個微電子總成610a及610b。
除了連結單元681中之至少某些連結單元上覆於微電子元件612及614上，且微電子總成610a及610b中之每一者可單獨形成，其每一者具有一各別囊封劑611a及610b之外，微電子總成600與圖9A及圖9B中所展示之微電子總成500相同。在一替代性實施例中，微電子總成600可具有至少部分覆蓋微電子總成610之第一微電子元件612及第二微電子元件614之一單個囊封劑，其類似於圖9A中所展示之單個囊封劑511。
如圖10中所展示，連結單元681可將微電子總成610彼此連結並電耦合。此等連結單元681可附接至曝露於第一微電子總成610a之基板630之第二表面632處之端子636及曝露於第二微電子總成610b之囊封劑611b之一頂部表面603處之端子682。端子682可藉由導線接合604與曝露於基板630之第一表面634處之導電元件636'電連接。曝露於囊封劑611a或611b之頂部表面603處之端子682中之某些端子可 上覆於微電子元件612及614中之至少一者上。在具有帶有上覆於微電子元件612及614中之至少一者上之端子682之微電子總成610之此等微電子總成600中，每一微電子總成610之端子682及636可配置成一面積陣列，這可允許微電子總成610之面積陣列堆疊。
曝露於囊封劑611a或611b之頂部表面603處之端子682可延伸於該頂部表面上方，可與該頂部表面齊平，或可凹入於該頂部表面下方。此等端子682可具有任一形狀，包括(例如)一墊狀或球狀形狀。於2011年5月3日提出申請之同在申請中且共同擁有之韓國專利申請案10-2011-0041843號中展示且闡述端子682及導線接合604之形狀及組態之其他實例，該韓國專利申請案藉此以引用方式併入本文中。
導線接合604在其一基底607處連結至導電元件636'且可延伸至遠離各別基底607且遠離基板630之一自由端608。導線接合604之自由端608係表徵為自由，此乃因其不電連接或以其他方式連結至微電子元件612、614或微電子總成610a內之任一其他導電特徵，該任一其他導電特徵又連接至微電子元件612、614。換言之，自由端608可用於至微電子總成610a外部之一導電特徵的電子連接(或直接或透過一焊料球或本文所論述之其他特徵間接)。自由端608可藉由(例如)囊封劑611a固持於一預定位置中或以其他方式連結或電連接至另一導電特徵之事實不意指其如本文所闡述係「自由的」，只要任一此特徵不電連接至微電子元件612、614。相反，基底607不自由，此乃因其或直接或間 接電連接至微電子元件612、614，如本文所闡述。
導線接合604可係由一導電材料製成，諸如銅、金、鎳、焊料、鋁或諸如此類。另外，導線接合604可係由材料組合製成，諸如係由一導電材料(諸如銅或鋁)之一核心製成，(例如)其中一塗層施塗於該核心上方。該塗層可係一第二導電材料，諸如鋁、鎳或諸如此類。另一選擇為，該塗層可係一絕緣材料，諸如一絕緣護套。在一實施例中，用以形成導線接合604之導線可具有約15 μm與150 μm之間的一厚度，亦即，橫貫該導線之長度之一尺寸。
導線接合604之自由端608具有一端表面638。端表面638可形成由複數個導線接合604之各別端表面638形成之一陣列中之一觸點之至少一部分。導線接合604之一部分可保持不被囊封劑611a覆蓋，這亦可稱作未經囊封，從而使得該導線接合可用於至位於該囊封劑外部之一特徵或元件的電連接。在一實施例中，導線接合604之端表面638保持不被囊封劑611a覆蓋且可曝露於該囊封劑之頂部表面603處。可能有其他實施例，其中除了或替代使端表面638保持不被囊封劑覆蓋，導線接合604之邊緣表面605之一部分不被囊封劑611a覆蓋。換言之，除了導線接合604之一部分(諸如端表面638、邊緣表面605或該兩者之組合)之外，囊封劑611a可覆蓋自第一表面634及上方之所有微電子總成610a。
在一項實施例中，端表面638及邊緣表面605之一部分可不被囊封劑611a覆蓋。此一組態可藉由允許焊料沿邊緣表 面605行進且除了連結至端表面638之外還連結至邊緣表面605來提供(諸如)藉由一焊料球或諸如此類至另一導電元件的一連接。在該等圖中所展示之實施例中，囊封劑611a之一表面(諸如頂部表面603)可與基板630之第一表面634分隔開足夠大以覆蓋微電子元件612、614之一距離。因此，其中導線接合604之端638與頂部表面603齊平之微電子總成610a之實施例可包括延伸至基板630上方比微電子元件612、614之高度更大之導線接合604。
包括堆疊式微電子總成610之微電子總成600可使用曝露於微電子總成600之一頂部表面601或一底部表面602處之連結單元681而附接至一電路面板(諸如一印刷電路板)。
在一特定實例中，微電子總成600可經組態以用作(例如)用於一智慧型電話應用之非均質記憶體。在此一實例中，微電子總成610內之微電子元件612及614中之某些微電子元件可包括諸如揮發性RAM之一記憶體儲存元件，且微電子元件612及614中之某些微電子元件可包括諸如非揮發性快閃記憶體之記憶體儲存元件。
雖然圖9A、圖9B及圖10中所展示之實施例展示微電子元件透過導線接合電連接至基板之觸點，但在其他實施例中，此等微電子元件可透過其他連接組態(包括，例如一或多個微電子元件至該基板之觸點的引線接合及覆晶安裝)電連接至該基板之觸點。
可在如圖11中所展示之多種電子系統之構造中利用上文所闡述之微電子總成。舉例而言，根據本發明之一另外實 施例之一系統1100包括上文結合其他電子總成1108及1110所闡述之一微電子總成1106。在所繪示之實例中，總成1108係一半導體晶片，而總成1110係一顯示螢幕，但可使用任何其他總成。當然，雖然出於清晰圖解說明起見在圖11中僅繪示兩個額外總成，但該系統可包括任一數目個此等總成。微電子總成1106可係上文所闡述之總成中之任一者。在一另外變型中，可使用任一數目個此等微電子總成。
微電子總成1106以及總成1108及1110安裝於以虛線示意性繪示之一共同外殼1101中，且在必要時彼此電互連以形成期望電路。在所展示之實例性系統中，該系統包括一電路面板1102(諸如一撓性印刷電路板)，且該電路面板包括使該等總成彼此互連之若干導體1104(圖11中僅繪示其中之一者)。然而，此僅係實例性的；可使用用於進行電連接之任一合適結構。將外殼1101繪示為(例如)可用於一蜂巢式電話或個人數位助理中之類型之一可攜式外殼，且螢幕1110曝露於該外殼之表面處。在結構1106包括一光敏元件(諸如一成像晶片)處，亦可提供一透鏡1111或其他光學裝置以用於將光路由至該結構。再次，圖11中所展示之簡化系統僅係實例性的；可使用上文所論述之結構製成其他系統，包括共同被視為固定結構之系統，諸如桌上型電腦、路由器及諸如此類。
雖然本文已參考特定實施例闡述了本發明，但應理解，此等實施例僅圖解說明本發明之原理及應用。因此應理 解，可對圖解說明性實施例做出若干修改且可設想出其他配置，而並不背離隨附申請專利範圍所界定之本發明之精神及範疇。
將瞭解，可以不同於起始請求項中所呈現之方式組合各個隨附請求項及其中所陳述之特徵。亦將瞭解，可與其他所闡述之實施例共用結合個別實施例所闡述之特徵。
10‧‧‧堆疊式微電子總成
10'‧‧‧變型
11‧‧‧外模製件/囊封劑
12‧‧‧第一微電子元件
12'‧‧‧第一微電子元件
14‧‧‧第二微電子元件
14'‧‧‧微電子元件
16‧‧‧前表面
16'‧‧‧表面
17‧‧‧第二端區
18‧‧‧後表面/後面
18'‧‧‧表面
19‧‧‧中心區
20‧‧‧電觸點/觸點
20'‧‧‧觸點
21‧‧‧第一端區
22‧‧‧前表面/第一表面
23‧‧‧第二端區
24‧‧‧後表面/後面
25‧‧‧導電跡線/跡線
26‧‧‧電觸點/觸點
27‧‧‧第一邊緣/邊緣表面
27'‧‧‧第一邊緣
29‧‧‧第二邊緣
29'‧‧‧第二邊緣
30‧‧‧基板/半導體元件/介電元件
30'‧‧‧基板
31‧‧‧間隔元件/支撐元件
32‧‧‧第二表面
34‧‧‧第一表面
35‧‧‧第一邊緣/邊緣表面
36‧‧‧端子
37‧‧‧邊緣表面/第二邊緣/邊緣
39‧‧‧孔口
39'‧‧‧孔口
40‧‧‧基板觸點
40'‧‧‧觸點
50‧‧‧引線
52‧‧‧導線接合
52'‧‧‧引線部分
53‧‧‧導線接合
60‧‧‧接合材料
61‧‧‧接合材料
70‧‧‧引線/接合元件
71‧‧‧接合材料
72‧‧‧導線接合
73‧‧‧導線接合/第三引線
76‧‧‧引線接合
81‧‧‧連結單元
82‧‧‧第一端部分
83‧‧‧導通體
84‧‧‧第二端部分
85‧‧‧引線接合
86‧‧‧中心部分
88‧‧‧引線
90‧‧‧導線接合
100‧‧‧微電子總成
101‧‧‧第一微電子元件
112‧‧‧第三微電子元件/第一微電子元件
114‧‧‧第二微電子元件
116‧‧‧前表面
120‧‧‧電觸點/觸點
130‧‧‧基板
132‧‧‧第二表面
134‧‧‧第一表面
136‧‧‧端子
141‧‧‧基板觸點/導電元件
143‧‧‧覆晶互連件
145‧‧‧金屬凸塊
147‧‧‧底填充物
200‧‧‧微電子總成
212‧‧‧第一微電子元件
220‧‧‧觸點
222‧‧‧前表面
226‧‧‧觸點
227‧‧‧第一邊緣
230‧‧‧基板
232‧‧‧第二表面
234‧‧‧第一表面
236‧‧‧端子
239‧‧‧孔口
240‧‧‧基板觸點
250‧‧‧引線
252‧‧‧導線接合
270‧‧‧引線
283‧‧‧導通體
300‧‧‧微電子總成
301‧‧‧第三微電子元件
320‧‧‧觸點
400‧‧‧微電子總成
401‧‧‧第三微電子元件
412‧‧‧第一微電子元件
414‧‧‧第二微電子元件
420‧‧‧觸點
426‧‧‧觸點
439‧‧‧孔口
474‧‧‧電連接/引線
476‧‧‧電連接/引線
478‧‧‧電連接/引線
490‧‧‧觸點
900‧‧‧電路面板
500‧‧‧微電子總成
501‧‧‧頂部表面
502‧‧‧底部表面
503‧‧‧周邊
510a‧‧‧第一微電子總成
510b‧‧‧第二微電子總成
511‧‧‧囊封劑
512‧‧‧微電子元件
514‧‧‧微電子元件
530‧‧‧基板
532‧‧‧第二表面
534‧‧‧第一表面
536‧‧‧端子
536'‧‧‧端子
581‧‧‧連結單元
590‧‧‧稀疏中心區
600‧‧‧微電子總成
601‧‧‧頂部表面
602‧‧‧底部表面
603‧‧‧頂部表面
604‧‧‧導線接合
605‧‧‧邊緣表面
607‧‧‧基底
608‧‧‧自由端
610a‧‧‧第一微電子總成/微電子總成
610b‧‧‧第二微電子總成/微電子總成
611a‧‧‧囊封劑
611b‧‧‧囊封劑
612‧‧‧微電子元件
614‧‧‧微電子元件
630‧‧‧基板
632‧‧‧第二表面
634‧‧‧第一表面
636‧‧‧端子
636'‧‧‧導電元件
638‧‧‧端表面
681‧‧‧連結單元
682‧‧‧端子
1100‧‧‧系統
1101‧‧‧外殼
1102‧‧‧電路面板
1104‧‧‧導體
1106‧‧‧微電子總成/結構
1108‧‧‧電子總成/總成
1110‧‧‧電子總成/總成
1111‧‧‧透鏡
圖1A係根據本發明之一實施例之一堆疊式微電子總成之一圖解性剖面正視圖；圖1B係根據本發明之一實施例之一堆疊式微電子總成之圖解性剖面正視圖；圖1C係根據本發明之一實施例之一堆疊式微電子總成之部分剖面視圖；圖2係圖1A中所展示之微電子總成之一平面視圖；圖3A係根據本發明之另一實施例之一堆疊式微電子總成之一圖解性剖面正視圖；圖3B係進一步圖解說明圖3A中所繪示之實施例之一部分剖面視圖。
圖4係根據本發明之一另外實施例之一堆疊式微電子總成之一圖解性剖面正視圖；圖5係圖解說明圖4中所展示之堆疊式微電子總成之一部分之一剖面視圖；圖6係根據本發明之一實施例之一堆疊式微電子總成之一圖解性剖面正視圖； 圖7係根據本發明之另一實施例之一堆疊式微電子總成之一圖解性剖面正視圖；圖8係根據本發明之一另外實施例之一堆疊式微電子總成之一圖解性剖面正視圖；圖9A係根據本發明之另一實施例之一堆疊式微電子總成之一圖解性剖面正視圖；圖9B係圖9A中所展示之堆疊式微電子總成之一俯視圖；圖10係根據本發明之又另一實施例之一堆疊式微電子總成之一圖解性剖面正視圖；及圖11係根據本發明一項實施例之一系統之一示意性繪圖。
400‧‧‧微電子總成
401‧‧‧第三微電子元件
412‧‧‧第一微電子元件
414‧‧‧第二微電子元件
420‧‧‧觸點
426‧‧‧觸點
439‧‧‧孔口
474‧‧‧電連接/引線
476‧‧‧電連接/引線
478‧‧‧電連接/引線
490‧‧‧觸點
900‧‧‧電路面板

Claims (47)

  1. 一種微電子總成，其包含：一基板，其具有對置面對之第一表面及第二表面以及在該第一表面與該第二表面之間延伸之一孔口，該基板具有曝露於其該第二表面處之第一端子；一第一微電子元件，其具有面對該基板之該第一表面之一前表面、遠離該前表面之一後表面及在該前表面與該後表面之間延伸之一邊緣，該第一微電子元件具有毗鄰該第一微電子元件之該邊緣曝露於其該前表面處之複數個觸點；一第二微電子元件，其具有第一及第二對置邊緣、在該第一邊緣與該第二邊緣之間延伸之一前表面及安置於遠離該第一邊緣及該第二邊緣之其該前表面之一中心區中之複數個觸點，該第二微電子元件之該前表面面對該第一微電子元件且突出超過該第一微電子元件之該邊緣；第一引線，其等將該第一微電子元件之該等觸點電連接至該等第一端子；第二引線，其等將該第二微電子元件之該等觸點連接至該等第一端子，該等第一引線及該等第二引線具有與該孔口對準之部分；及第二端子，其等曝露於與該基板之該第二表面對置之該微電子總成之一表面處，其中該等第二端子中之至少某些端子上覆於該等微電子元件中之至少一者上，以及 其中該等第二端子中之至少某些端子藉由導線接合而與曝露於該基板之該第一表面處之導電元件電連接。
  2. 如請求項1之微電子總成，其進一步包含至少部分覆蓋該第一微電子元件及該第二微電子元件以及該等導線接合之至少部分之一囊封劑，其中曝露該等第二端子之該微電子總成之該表面係該囊封劑之一表面。
  3. 如請求項2之微電子總成，其中該等導線接合具有附接至該等導電元件之基底及遠離該等導電元件之未經囊封之端表面以及在該等基底與該等未經囊封之端表面之間延伸之邊緣表面，該等未經囊封之端表面未被該囊封劑覆蓋，其中該等第二端子與該等未經囊封之端表面電連接。
  4. 如請求項3之微電子總成，其中該等導線接合中之至少一者之一邊緣表面之至少一部分未經囊封且該等第二端子中之至少一者與該等導線接合中之該至少一者之該未經囊封之邊緣表面及該未經囊封之端表面電連接。
  5. 如請求項2之微電子總成，其中該等導線接合具有介於附接至該等導電元件之該等導線接合之基底與遠離該等導電元件之該等導線接合之端之間的未經囊封之邊緣表面，其中該等第二端子與該等未經囊封之邊緣表面電連接。
  6. 如請求項1之微電子總成，其中該等微電子元件中之至少一者包括一揮發性隨機存取記憶體(RAM)，且該等微電子元件中之至少一者包括非揮發性快閃記憶體。
  7. 如請求項1之微電子總成，其進一步包含將該第一微電子元件之該等觸點與該第二微電子元件之該等觸點電互連之第三引線，該等第一引線、該等第二引線及該等第三引線具有與該孔口對準之部分。
  8. 如請求項1之微電子總成，其中該等第一引線或該等第二引線中之至少一者包括自該第一微電子元件或該第二微電子元件中之至少一者之該等觸點延伸之導線接合。
  9. 如請求項1之微電子總成，其中與該孔口對準之該等第一引線及該等第二引線中之至少一者之該等部分係具有沿該基板延伸至該等端子之第二部分之單體式導電元件之部分。
  10. 如請求項1之微電子總成，其進一步包含介於該第二微電子元件之該前表面與該基板之該第一表面之間的一間隔元件。
  11. 如請求項1之微電子總成，其中該第一微電子元件包括經組態以主要執行一邏輯功能之一晶片。
  12. 如請求項1之微電子總成，其中該第二微電子元件具有經組態以除任何其他功能外還提供記憶體儲存陣列功能之大量主動裝置。
  13. 如請求項1之微電子總成，其中該第一微電子元件具有經組態以除任何其他功能外還提供記憶體儲存陣列功能之大量主動裝置。
  14. 如請求項1之微電子總成，其進一步包含將該第一微電子元件之該等觸點電連接至該等端子之第三引線，該等 第一引線及該等第三引線連接至該孔口之對置側上之端子，該等第一引線、該等第二引線及該等第三引線具有與該孔口對準之部分。
  15. 如請求項1之微電子總成，其進一步包含：一第三微電子元件，其安置於該基板之第一表面與該第二微電子元件之該前表面之間，該第三微電子元件具有第一及第二對置邊緣、在該第一邊緣與該第二邊緣之間延伸之一前表面以及毗鄰其該第一邊緣而安置於其該前表面上之複數個觸點，該第三微電子元件之該前表面面對該基板之該第一表面；第三引線，其等將該第三微電子元件之該等觸點電連接至該等端子；及第四引線，其等將該第一微電子元件及該第三微電子元件之該等觸點電互連，該第一微電子元件及該第三微電子元件之該等觸點位於該孔口之對置側上，該等第一引線、該等第二引線、該等第三引線及該等第四引線具有與該孔口對準之部分。
  16. 如請求項15之微電子總成，其進一步包含將該第一微電子元件及該第二微電子元件之該等觸點電互連之第五引線。
  17. 如請求項16之微電子總成，其進一步包含將該第二微電子元件及該第三微電子元件之該等觸點電互連之第六引線。
  18. 一種微電子總成，其包括第一微電子總成及第二微電子 總成，每一微電子總成係如請求項1中所請求，該第一微電子總成至少部分上覆於該第二微電子總成上，且該第一微電子總成之該等第一端子與該第二微電子總成之該等第二端子連結。
  19. 如請求項18之微電子總成，其中該等第一微電子元件中之至少一者經組態以主要執行一邏輯功能，且該等第二微電子元件中之至少一者具有經組態以除任何其他功能外還提供記憶體儲存陣列功能之大量主動裝置。
  20. 如請求項18之微電子總成，其中該第一微電子總成之該等第一端子中之至少某些端子與該第二微電子總成之該等第二端子中之至少某些端子配置成一面積陣列，且其中該第一微電子總成與該第二微電子總成藉由係一接合金屬之導電塊之連結單元連結。
  21. 如請求項18之微電子總成，其中該等微電子總成透過毗鄰該微電子總成之一周邊而配置之連結單元彼此電連接。
  22. 如請求項21微電子總成，其中該等連結單元位於該微電子總成之一稀疏中心區外部。
  23. 一種包含如請求項1之微電子總成及電連接至該微電子總成之一或多個其他電子總成之系統。
  24. 如請求項23之系統，其中該等端子中之至少某些端子電連接至一電路面板。
  25. 如請求項24之系統，其進一步包含一外殼，該微電子總成及該等其他電子總成係安裝至該外殼。
  26. 一種微電子總成，其包含：一基板，其具有對置面對之第一表面及第二表面以及在該第一表面與該第二表面之間延伸之一孔口，該基板具有端子；一第一微電子元件，其具有面對該基板之該第一表面之一前表面、遠離該前表面之一後表面及在該前表面與該後表面之間延伸之一邊緣，該第一微電子元件具有毗鄰該第一微電子元件之該邊緣曝露於其該前表面處之複數個觸點；一第二微電子元件，其具有第一及第二對置邊緣、在該第一邊緣與該第二邊緣之間延伸之一前表面及安置於遠離該第一邊緣及該第二邊緣之其該前表面之一中心區中之複數個觸點，該第二微電子元件之該前表面面對該第一微電子元件且突出超過該第一微電子元件之該邊緣；第一引線，其等將該第一微電子元件之該等觸點電連接至該等端子；第二引線，其等將該第二微電子元件之該等觸點電連接至該等端子；及第三引線，其等將該第一微電子元件之該等觸點與該第二微電子元件之該等觸點電互連，該等第一引線、該等第二引線及該等第三引線具有與該孔口對準之部分，其中與該孔口對準之該等第一引線及該等第二引線中之至少一者之該等部分係具有沿該基板延伸至該等端子 之第二部分之單體式導電元件之部分。
  27. 如請求項26之微電子總成，其中該等第一引線或該等第二引線中之至少一者包括自該第一微電子元件或該第二微電子元件中之至少一者之該等觸點延伸之導線接合。
  28. 如請求項26之微電子總成，其進一步包含介於該第二微電子元件之該前表面與該基板之該第一表面之間的一間隔元件。
  29. 如請求項26之微電子總成，其中該第一微電子元件包括經組態以主要執行一邏輯功能之一晶片。
  30. 如請求項26之微電子總成，其中該第二微電子元件具有經組態以除任何其他功能外還提供記憶體儲存陣列功能之大量主動裝置。
  31. 如請求項26之微電子總成，其中該第一微電子元件具有經組態以除任何其他功能外還提供記憶體儲存陣列功能之之大量主動裝置。
  32. 一種包含如請求項26之微電子總成及電連接至該微電子總成之一或多個其他電子總成之系統。
  33. 如請求項32之系統，其中該等端子電連接至一電路面板。
  34. 如請求項33之系統，其進一步包含一外殼，該微電子總成及該等其他電子總成係安裝至該外殼。
  35. 一種包括第一微電子總成及第二微電子總成之微電子總成，每一微電子總成係如請求項26中所請求，該第一微電子總成與該第二微電子總成電連接且至少部分上覆於 該第二微電子總成上。
  36. 如請求項35之微電子總成，其中該等微電子總成透過毗鄰該微電子總成之一周邊而配置之連結單元彼此電連接。
  37. 如請求項36之微電子總成，其中該等連結單元位於該微電子總成之一稀疏中心區外部。
  38. 如請求項35之微電子總成，其中該等微電子元件中之至少某些微電子元件包括一揮發性隨機存取記憶體(RAM)，且該等微電子元件中之至少某些微電子元件包括非揮發性快閃記憶體。
  39. 如請求項35之微電子總成，其中該等第一微電子元件中之至少一者經組態以主要執行一邏輯功能，且該等第二微電子元件中之至少一者具有經組態以除任何其他功能外還提供記憶體儲存陣列功能之大量主動裝置。
  40. 一種微電子總成，其包含：一基板，其具有對置面對之第一表面及第二表面以及在該第一表面與該第二表面之間延伸之一孔口，該基板具有端子；一第一微電子元件，其具有面對該基板之該第一表面之一前表面、遠離該前表面之一後表面、及在該前表面與該後表面之間延伸之一邊緣，該第一微電子元件具有毗鄰該第一微電子元件之該邊緣曝露於其該前表面處之複數個觸點；一第二微電子元件，其具有第一及第二對置邊緣、在 該第一邊緣與該第二邊緣之間延伸之一前表面、及安置於遠離該第一邊緣及該第二邊緣之其該前表面之一中心區中之複數個觸點，該第二微電子元件之該前表面面對該第一微電子元件且突出超過該第一微電子元件之該邊緣；第一引線，其等將該第一微電子元件之該等觸點電連接至該等端子；第二引線，其等將該第二微電子元件之該等觸點電連接至該等端子；及第三引線，其等將該第一微電子元件之該等觸點電連接至該等端子，該等第一引線及該等第三引線連接至該孔口之對置側上之端子，該等第一引線、該等第二引線及該等第三引線具有與該孔口對準之部分。
  41. 如請求項40之微電子總成，其中該第一微電子元件包括經組態以主要執行一邏輯功能之一晶片。
  42. 如請求項40之微電子總成，其中該第二微電子元件具有經組態以除任何其他功能外還提供記憶體儲存陣列功能之大量主動裝置。
  43. 如請求項40之微電子總成，其中該第一微電子元件具有經組態以除任何其他功能外還提供記憶體儲存陣列功能之大量主動裝置。
  44. 一種微電子總成，其包含：一基板，其具有對置面對之第一表面及第二表面以及在該第一表面與該第二表面之間延伸之一孔口，該基板 具有端子；一第一微電子元件，其具有面對該基板之該第一表面之一前表面、遠離該前表面之一後表面及在該前表面與該後表面之間延伸之一邊緣，該第一微電子元件具有毗鄰該第一微電子元件之該邊緣曝露於其該前表面處之複數個觸點；一第二微電子元件，其具有第一及第二對置邊緣、在該第一邊緣與該第二邊緣之間延伸之一前表面、及安置於遠離該第一邊緣及該第二邊緣之其該前表面之一中心區中之複數個觸點，該第二微電子元件之該前表面面對該第一微電子元件且突出超過該第一微電子元件之該邊緣；一第三微電子元件，其安置於該基板之第一表面與該第二微電子元件之該前表面之間，該第三微電子元件具有第一及第二對置邊緣、在該第一邊緣與該第二邊緣之間延伸之一前表面、以及毗鄰其該第一邊緣安置於其該前表面上之複數個觸點，該第三微電子元件之該前表面面對該基板之該第一表面；第一引線，其等將該第一微電子元件之該等觸點電連接至該等端子；第二引線，其等將該第二微電子元件之該等觸點連接至該等端子；第三引線，其等將該第三微電子元件之該等觸點電連接至該等端子； 第四引線，其等將該第一微電子元件及該第三微電子元件之該等觸點電互連，該第一微電子元件及該第三微電子元件之該等觸點位於該孔口之對置側上，該等第一引線、該等第二引線、該等第三引線及該等第四引線具有與該孔口對準之部分；第五引線，其等將該第一微電子元件及該第二微電子元件之該等觸點電互連；以及第六引線，其等將該第二微電子元件及該第三微電子元件之該等觸點電互連。
  45. 如請求項44之微電子總成，其中該第一微電子元件包括經組態以主要執行一邏輯功能之一晶片。
  46. 如請求項44之微電子總成，其中該第二微電子元件具有經組態以除任何其他功能外還提供記憶體儲存陣列功能之大量主動裝置。
  47. 如請求項44之微電子總成，其中該第一微電子元件具有經組態以除任何其他功能外還提供記憶體儲存陣列功能之大量主動裝置。
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US8928153B2 (en) 2015-01-06
BR112013027142A2 (pt) 2017-01-10
TW201248812A (en) 2012-12-01
US20180025967A1 (en) 2018-01-25
WO2012145201A1 (en) 2012-10-26
US20150115477A1 (en) 2015-04-30

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