CN103620778B - 倒装芯片、正面和背面中心键合存储线键合组件 - Google Patents

倒装芯片、正面和背面中心键合存储线键合组件 Download PDF

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Publication number
CN103620778B
CN103620778B CN201280030801.1A CN201280030801A CN103620778B CN 103620778 B CN103620778 B CN 103620778B CN 201280030801 A CN201280030801 A CN 201280030801A CN 103620778 B CN103620778 B CN 103620778B
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microelectronic element
micromodule
lead
microelectronic
edge
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CN103620778A (zh
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贝尔加桑·哈巴
理查德·德威特·克里斯普
韦勒·佐尼
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Abstract

一种微电子组件10可以包括具有第一表面34、第二表面58、在其间延伸的孔39以及端子36的衬底30。组件10还可以包括具有面对第一表面34的前表面16的第一微电子元件12、具有突出于第一微电子元件的边缘29之外的前表面22的第二微电子元件14、将微电子元件的触点20、52电连接到端子的第一引线70和第二引线76、以及将第一微电子元件的触点和第二微电子元件的触点电互连的第三引线73。第一微电子元件的触点20可以设置为邻近边缘29。第二微电子元件14的触点26可以设置在其前表面22的中心区域19中。引线70、76、99可以具有与孔39对齐的部分。

Description

倒装芯片、正面和背面中心键合存储线键合组件
相关申请的交叉引用
本申请要求2011年4月21日申请的美国临时专利申请号No.61/477,967以及2011年11月29日申请的美国专利申请号No.13/306,099的权益，其公开内容通过引用并入本文。以下通过引用并入本文的共同所有的申请包括：2011年4月21日申请的美国临时专利申请号No.61/477,820、No.61/477,877以及No.61/477,883。
技术领域
本发明涉及堆叠微电子组件以及制造这种组件的方法，以及用于这种组件的部件。
背景技术
半导体芯片通常设为单独的预封装单元。标准芯片具有带有大的前面的扁平矩形体，该前面具有连接到芯片的内部电路的触点。每个单独的芯片典型地安装在封装中，封装再安装在电路板例如印刷电路板上，封装将芯片的触点连接到电路板的导体。在很多常规的设计中，芯片封装在电路板中占用的面积比芯片本身的面积大很多。如参考具有前面的扁平芯片的本公开中所使用的，“芯片的面积”应被理解为指的是所述前面的面积。在“倒装芯片”设计中，芯片的前面面对封装衬底的面，即，通过焊球或其他连接元件将芯片载体与芯片上的触点直接键合到芯片载体的触点。通过覆盖芯片的前面的端子又可以将芯片载体键合到电路板。“倒装芯片”设计提供相对紧凑的布置；每个芯片占用的电路板的面积等于或稍大于芯片的前面的面积，例如在共同转让的美国专利5,148,265、5,148,266和5,679,977中的某些实施例中所公开的，其全部公开内容通过引用并入本文。
某些创新的安装技术提供的紧密度接近或等于常规倒装芯片键合的紧密度。可以在等于或稍大于芯片本身的面积的、电路板的面积中容置单个芯片的封装通常被称为“芯片级封装”。
除了最小化被微电子组件占用的电路板的平面面积，还需要生产一种垂直于电路板平面的整体高度或尺寸较小的芯片封装。这种薄的微电子封装允许将其中安装有封装的电路板紧挨着相邻结构放置，由此产生包含电路板的产品的整体尺寸。已经提出用于在单个封装或模块中设置多个芯片的多种提议。在常规的“多芯片模块”中，芯片并排地安装在单个封装衬底上，然后可以将该封装衬底安装至电路板。这种方法只是提供芯片所占用的电路板的总面积的有限减小。总面积仍然大于模块中各个芯片的总表面积。
还已经提出将多个芯片封装在“堆叠”布置(即多个芯片放置成一个在另一个之上的布置)中。在堆叠布置中，可以将多个芯片安装在比芯片的总面积小的电路板的面积中。例如，在上述的美国专利5,679,977、5,148,265以及5,347,159的某些实施例中公布了一些堆叠芯片布置，其全部公开内容通过引用并入本文。也通过引用并入本文的美国专利No.4,941,033公开一种布置，其中芯片一个在另一个之上地堆叠，且通过与芯片相关联的所谓的“布线膜”上的导体彼此互连。
除了现有技术的这些努力，需要对用于具有基本位于芯片的中心区域的触点的芯片的多芯片封装的情况进一步改进。某些半导体芯片，例如一些存储芯片，通常具有基本沿芯片的中心轴设置的一行或两行触点。
发明内容
本发明涉及微电子组件和制造这种组件的方法。根据本发明的方面，微电子组件可以包括：具有相对地面对的第一表面和第二表面以及在第一表面和第二表面之间延伸的孔的衬底；具有面对衬底第一表面的前表面的第一微电子元件；以及具有面对第一微电子元件的前表面的第二微电子元件。衬底可以具有暴露在其第二表面的第一端子。第一微电子元件还可以具有远离前表面的后表面，以及在前表面和后表面之间延伸的边缘。第一微电子元件可以具有暴露在其前表面处且邻近第一微电子元件的边缘的多个触点。第二微电子元件可以具有相对的第一边缘和第二边缘。第二微电子元件的前表面可以在第一边缘和第二边缘之间延伸。
第二微电子元件可以具有设置在其前表面的中心区域且远离第一边缘和第二边缘的多个触点。第二微电子元件的前表面可以突出于第一微电子元件的边缘之外。微电子组件还可以包括将第一微电子元件的触点电连接到第一端子的第一引线以及将第二微电子元件的触点连接到第一端子的第二引线。第一引线和第二引线可以具有与孔对齐的部分。微电子组件还可以包括暴露在与衬底的第二表面相对的微电子组件的表面处的第二端子。至少一些第二端子可以覆盖至少一个微电子元件。
在一个实施例中，至少一些第二端子可以通过线键合与暴露在衬底的第一表面处的导电元件电连接。在特定示例中，微电子组件还可以包括至少部分覆盖第一微电子元件和第二微电子元件以及至少部分的线键合的密封剂。第二端子暴露在其处的微电子组件的表面可以是密封剂的表面。在一个示例中，线键合可以具有附接至导电元件的基座和远离导电元件的未密封端表面，以及在基座和未密封端表面之间延伸的边缘表面。未密封端表面可以不被密封剂覆盖。第二端子可以与未密封端表面电连接。在示例性实施例中，至少一个线键合的至少部分边缘表面可以是未密封的，至少一个第二端子可以与至少一个线键合的未密封边缘表面和未密封端表面电连接。
在特定的实施例中，线键合可以具有位于附接至导电元件的线键合的基座和远离导电元件的线键合的端部之间的未密封边缘表面。第二端子可以与未密封边缘表面电连接。在一个实施例中，至少一个微电子元件可以包括易失性随机存取存储器(RAM)，至少一个微电子元件可以包括非易失性闪存。在示例性实施例中，微电子组件还可以包括将第一微电子元件的触点与第二微电子元件的触点电互连的第三引线。第一引线、第二引线和第三引线可以具有与孔对齐的部分。在一个示例中，第一引线或第二引线中的至少一个可以包括从第一微电子元件或第二微电子元件中的至少一个的触点延伸的线键合。
在特定的示例中，第一引线和第二引线的至少一个的与孔对齐的部分可以是单片导电元的部分，单片导电元件具有沿衬底延伸到端子的第二部分。在示例性实施例中，微电子组件还可以包括第二微电子元件的前表面和衬底的第一表面之间的间隔元件。在一个示例中，第一微电子元件可以包括用于主要执行逻辑功能的芯片。在特定的实施例中，第二微电子元件可以具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。在一个实施例中，第一微电子元件可以具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。在示例性实施例中，微电子组件还可以包括将第一微电子元件的触点电连接到端子的第三引线。第一引线和第三引线可以连接到孔的相对侧上的端子。第一引线、第二引线和第三引线可以具有与孔对齐的部分。
在一个示例中，微电子组件还可以包括设置在衬底的第一表面和第二微电子元件的前表面之间的第三微电子元件，将第三微电子元件的触点电连接到端子的第三引线，以及将第一微电子元件的触点和第三微电子元件的触点电互连的第四引线。第三微电子元件可以具有相对的第一边缘和第二边缘、在第一边缘和第二边缘之间延伸的前表面，以及设置在其前表面上且邻近其第一边缘的多个触点。第三微电子元件的前表面可以面对衬底的第一表面。第一微电子元件的触点和第三微电子元件的触点可以位于孔的相对侧上。第一引线、第二引线、第三引线和第四引线可以具有与孔对齐的部分。在示例性实施例中，微电子组件还可以包括将第一微电子元件的触点和第二微电子元件的触点电互连的第五引线。在特定的实施例中，微电子组件还可以包括将第二微电子元件的触点和第三微电子元件的触点电互连的第六引线。
在一个实施例中，微电子部件可以包括如上所述的第一微电子组件和第二微电子组件。第一微电子组件可以至少部分地覆盖第二微电子组件。第一微电子组件的第一端子可以与第二微电子组件的第二端子接合。在示例性实施例中，至少一个第一微电子元件可以主要用于执行逻辑功能。至少一个第二微电子元件可以具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。在特定的实施例中，第一微电子组件的至少一些第一端子和第二微电子组件的至少一些第二端子可以布置成面阵。第一微电子组件和第二微电子组件可以通过接合单元接合，接合单元是烧结金属的导电块。
在示例性实施例中，微电子组件可以通过邻近微电子部件的外围布置的接合单元彼此电互连。在一个示例中，接合单元可以位于微电子部件的非密集中心区域的外侧。在特定的实例中，系统可以包括如上所述的微电子组件以及电连接到微电子组件的一个或多个其他电子部件。在特定的实施例中，至少一些端子可以电连接到电路板。在一个示例中，系统还可以包括壳体，微电子组件和其他电子部件安装到该壳体。
根据本发明的另一方面，微电子组件可以包括衬底，该衬底具有相对地面对的第一表面和第二表面以及在第一表面和第二表面之间延伸的孔；第一微电子元件，该第一微电子元件具有面对衬底第一表面的前表面；以及第二微电子元件，该第二微电子元件具有面对第一微电子元件的前表面。衬底可以具有端子。第一微电子元件还可以包括远离前表面的后表面以及在前表面和后表面之间延伸的边缘。第一微电子元件可以具有暴露在其前表面处且邻近第一微电子元件的边缘的多个端子。第二微电子元件可以具有相对的第一边缘和第二边缘。第二微电子元件的前表面可以在第一边缘和第二边缘之间延伸。
第二微电子元件可以具有设置在其前表面的中心区域且远离第一边缘和第二边缘的多个触点。第二微电子元件的前表面可以突出于第一微电子元件的边缘之外。微电子组件还可以包括将第一微电子元件的触点电连接到端子的第一引线，将第二微电子元件的触点电连接到端子的第二引线以及将第一微电子元件的触点与第二微电子元件的触点电互连的第三引线。第一引线、第二引线和第三引线可以具有与孔对齐的部分。
在示例性实施例中，第一引线或第二引线中的至少一个可以包括从第一微电子元件或第二微电子元件中的至少一个的触点延伸的线键合。在一个实施例中，第一引线和第二引线中的至少一个的与孔对齐的部分可以是单片导电元件的部分，单片导电元件具有沿衬底延伸到端子的第二部分。在特定的实施例中，微电子组件还可以包括第二微电子元件的前表面和衬底的第一表面之间的间隔元件。在特定的实施例中，第一微电子元件可以包括用于主要执行逻辑功能的芯片。在示例性实施例中，第二微电子元件可以具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。在一个实施例中，第一微电子元件可以具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。
本发明的另外的方面可以提供将根据本发明的上述方面的微电子组件与电连接至其的其它电子部件相结合的系统。例如，端子可以电连接到电路板。在另一示例中，系统可以设置在单个壳体中和/或安装到单个壳体，该壳体可以是便携式壳体。根据本发明的这个方面的优选实施例的系统可以比可比较的常规系统更紧凑。
在一个实施例中，微电子部件可以包括如上所述的第一微电子组件和第二微电子组件。第一微电子组件可以与第二微电子组件电连接并可以至少部分地覆盖第二微电子组件。在示例性实施例中，微电子组件可以通过布置在邻近微电子部件的外围处的接合单元彼此电连接。在特定的实施例中，接合单元可以位于微电子部件的非密集中心区域的外侧。在一个实施例中，一些微电子元件可以包括易失性随机存取存储器(RAM)，一些微电子元件可以包括非易失性闪存。在特定的实施例中，第一微电子元件的至少一个可以主要用于执行逻辑功能，第二微电子元件的至少一个可以具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。
根据本发明的又另一方面，微电子组件可以包括：衬底，该衬底具有相对地面对的第一表面和第二表面以及在第一表面和第二表面之间延伸的孔；第一微电子元件，该第一微电子元件具有面对衬底的第一表面的前表面；以及第二微电子元件，该第二微电子元件具有面对第一微电子元件的前表面。衬底可以具有端子。第一微电子元件还可以包括远离前表面的后表面以及在前表面和后表面之间延伸的边缘。第一微电子元件可以具有暴露在其前表面处且邻近第一微电子元件的边缘的多个触点。第二微电子元件可以具有相对的第一边缘和第二边缘。第二微电子元件的前表面可以在第一边缘和第二边缘之间延伸。
第二微电子元件可以具有设置在其远离第一边缘和第二边缘的前表面的中心区域中的多个触点。第二微电子元件的前表面可以突出于第一微电子元件的边缘之外。微电子组件还可以包括将第一微电子元件的触点电连接到端子的第一引线，将第二微电子元件的触点连接到端子的第二引线，以及将第一微电子元件的触点电连接到端子的第三引线。第一引线和第三引线可以连接到孔的相对侧上的端子。第一引线、第二引线和第三引线可以具有与孔对齐的部分。
在特定的实施例中，第一微电子元件可以包括用于主要执行逻辑功能的芯片。在示例性实施例中，第二微电子元件可以具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。在一个实施例中，第一微电子元件可以具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。
根据本发明的再另一方面，微电子组件可以包括：衬底，该衬底具有相对地面对的第一表面和第二表面以及在第一和第二表面之间延伸的孔；第一微电子元件，该第一微电子元件具有面对衬底的第一表面的前表面；第二微电子元件，该第二微电子元件具有面对第一微电子元件的前表面；以及第三微电子元件，该第三微电子元件设置在衬底的第一表面和第二微电子元件的前表面之间。衬底可以具有端子。
第一微电子元件还可以包括远离前表面的后表面以及在前表面和后表面之间延伸的边缘。第一微电子元件可以具有暴露在其前表面处且邻近第一微电子元件的边缘的多个触点。第二微电子元件可以具有相对的第一边缘和第二边缘。第二微电子元件的前表面可以在第一边缘和第二边缘之间延伸。第二微电子元件可以具有设置在其前表面的远离第一边缘和第二边缘的中心区域中的多个触点。第二微电子元件的前表面可以突出于第一微电子元件的边缘之外。第三微电子元件可以具有相对的第一边缘和第二边缘、在第一边缘和第二边缘之间延伸的前表面以及设置在前表面处且邻近其第一边缘的多个触点。第三微电子元件的前表面可以面对衬底的第一表面。
微电子组件还可以包括将第一微电子元件的触点电连接到端子的第一引线，将第二微电子元件的触点连接到端子的第二引线，将第三微电子元件的触点电连接到端子的第三引线以及将第一微电子元件的触点和第三微电子元件的触点电互连的第四引线。第一微电子元件的触点和第三微电子元件的触点可以位于孔的相对侧上。第一引线、第二引线、第三引线和第四引线可以具有与孔对齐的部分。
在一个实施例中，微电子组件还可以包括将第一微电子元件的触点和第二微电子元件的触点电互连的第五引线。在特定的实施例中，微电子组件还可以包括将第二微电子元件的触点和第三微电子元件的触点电互连的第六引线。在特定的实施例中，第一微电子元件可以包括用于主要执行逻辑功能的芯片。在示例性的实施例中，第二微电子元件可以具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。在一个实施例中，第一微电子元件可以具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。
附图说明
现在将参考附图描述本发明的各个实施例。需要理解的是，这些附图仅描述本发明的一些实施例，因此不应作为对本发明范围的限制。
图1A是根据本发明的实施例的堆叠微电子组件的示意性截面正视图；
图1B是根据本发明的实施例的堆叠微电子组件的示意性截面正视图；
图1C是根据本发明的实施例的堆叠微电子组件的部分剖视图；
图2是图1A所示的微电子组件的俯视图；
图3A是根据本发明的另一实施例的堆叠微电子组件的示意性截面正视图；
图3B是进一步示出图3A中描述的实施例的部分剖视图；
图4是根据本发明的又一实施例的堆叠微电子组件的示意性截面正视图；
图5是示出图4所示的堆叠微电子组件的部分的剖视图；
图6是根据本发明的实施例的堆叠微电子组件的示意性截面正视图；
图7是根据本发明的另一实施例的堆叠微电子组件的示意性截面正视图；
图8是根据本发明的又一实施例的堆叠微电子组件的示意性截面正视图；
图9A是根据本发明的另一实施例的堆叠微电子组件的示意性截面正视图；
图9B是图9A所示的堆叠微电子组件的俯视图；
图10是根据本发明的又另一实施例的堆叠微电子组件的示意性截面正视图；以及
图11是根据本发明的一个实施例的系统的示意图。
具体实施方式
参考图1A和图2，根据本发明的实施例的堆叠微电子组件10包括第一微电子元件12和第二微电子元件14，第一微电子元件12背面放置且面对衬底30，第二微电子元件14背面放置且覆盖第一微电子元件12的至少部分。在一些实施例中，第一微电子元件12和第二微电子元件14可以是半导体芯片，或是包括半导体芯片的元件，该半导体芯片具有在其前表面16处的触点。半导体芯片可以是半导体材料(例如硅或砷化镓)的薄片，并且可被设置为独立的预封装单元。半导体芯片可以是半导体材料(例如硅或砷化镓)的薄片，并且可被设置为独立的预封装单元。半导体芯片可以配备有有源电路元件(例如，晶体管、二极管等)，或无源电路元件(例如电阻、电容或电感等)，或有源和无源电路元件的结合。在“有源”半导体芯片中，每个微电子元件中的有源电路元件典型地在一个或多个“集成电路”中电连接在一起。第一微电子元件和第二微电子元件都可如下文中讨论的电连接至衬底30。衬底30可再通过其表面处的端子36电连接至电路板，例如印刷电路板。在特定实施例中，微电子组件10可为具有用于与电路板(例如印刷电路板等)的面上的相应触点电连接的端子的微电子“封装”。
在特定实施例中，衬底可为各种结构的介质元件，例如聚合材料或无机材料(例如陶瓷或玻璃)的介质元件，衬底具有在其上的导电元件，例如端子以及与端子电连接的导电元件(例如迹线、衬底触点或与其他导电元件)。在另一示例中，衬底可基本由半导体材料(例如硅)组成，或者可选地包括半导体材料层及其一个或多个介质层。这种衬底可具有低于百万分之七每摄氏度(“7ppm/℃”)的热膨胀系数。在又一个实施例中，衬底可为具有引脚的引线框架，其中端子可以为引脚的部分，例如引脚的端部。在又一个实施例中，衬底可为具有引线的引线框架，其中端子可为引线的部分，例如引线的端部。
第一微电子元件12可以包括主要用于执行逻辑功能的半导体芯片，例如微处理器、特定用途集成电路(ASIC)、现场可编程门阵列(FPGA)或其他逻辑芯片等。在特定的实施例中，微电子元件12可以是控制器或主要提供逻辑功能但也可以包括存储器存储阵列的芯片上系统(SOC)。在其他示例中，第一微电子元件12可以包括或是存储芯片(例如，闪存(“或非”或“与非”)芯片、动态随机存取存储(DRAM)芯片或静态随机存取存储(SRAM)芯片)，或是主要用于执行一些其他功能。这种存储芯片包括存储器存储阵列，并典型地具有比提供任何其它功能的有源电路元件更多的有源电路元件(例如，有源装置，如晶体管)以提供存储器存储阵列功能。第一微电子元件12具有前表面16，远离前表面的后面18，以及在前表面和后表面之间延伸的第一边缘27和第二边缘29。电触点20暴露在第一微电子元件12的前表面处且邻近第二边缘29。如本发明所使用的，导电元件“暴露在”结构的表面处的描述表示导电元件可用于与在与介质结构的表面垂直的方向上从介质结构的外部朝介质结构的表面移动的理论点接触。因此，暴露在结构的表面处的端子或其他导电元件可从这样的表面突出；可与这样的表面平齐；或者可相对于这样的表面凹入并通过介质结构中的孔或凹入部暴露。电触点20可包括键合焊盘或其他导电结构(例如凸点、接线柱等)。键合焊盘可以包括一种或多种金属(例如铜、镍、金或铝)，并且可以为大约0.5μm厚。键合焊盘的大小可随着装置类型的改变而改变，但其一侧将典型地为几十微米到几百微米。
第二微电子元件14具有前表面22，远离前表面的后表面24，在前表面和后表面之间延伸的第一边缘35和第二边缘37以及暴露在前表面22处的触点26。如图1A所示，第一微电子元件12和第二微电子元件14相互堆叠，以便第二微电子元件14的至少部分覆盖第一微电子元件12的至少部分。在特定的实施例中，如图1A所示，第二微电子元件14的前表面22包括第一端区域21和第二端区域23以及在第一端区域21和第二端区域23之间延伸的中心区域19。第一端区域21在中心区域19和第一边缘35之间延伸，第二端区域23在中心区域19和第二边缘37之间延伸。中心区域可延伸第二微电子元件14的第一边缘35和第二边缘37之间的距离的三分之一，第一端区域和第二端区域可分别延伸边缘35和边缘37之间的距离的三分之一。电触点26暴露在第二微电子元件14的前表面22处。例如，触点26可布置成邻近前表面22的中心的一行或平行的两行。第二微电子元件14可包括或者可为DRAM芯片。这种DRAM芯片包括存储器存储阵列，并典型地具有比提供任何其它功能的有源电路元件更多的有源电路元件(例如，有源装置，如晶体管)以提供存储器存储阵列功能。第二微电子元件14的中心区域19的至少部分突出于第一微电子元件12的第二边缘29之外，以便第二微电子元件14的触点26暴露在第一微电子元件12的第二边缘29之外。如上所讨论的，在一个实施例中，衬底30可包括具有相对地面对的第一表面34和第二表面32的介质层。一个或多个导电元件或端子36暴露在衬底30的第二表面32处。在特定实施例中，一些或全部端子36可以关于第一微电子元件12和/或第二微电子元件14是可移动的。
衬底30进一步包括在其相对的第一表面和第二表面之间(例如，在介质元件30的相对面对的第一表面和第二表面之间)延伸的一个或多个孔。在图1A所示的实施例中，衬底30包括孔39和与衬底30的孔39对齐的至少一些触点26。多条引线将第二微电子元件的触点26与微电子组件的端子36电连接。引线具有与孔39对齐的部分。例如，引线可包括键合至衬底触点的线键合52，衬底触点再通过引线的其他部分(例如，沿半导体元件或介质元件30延伸的金属迹线)连接至端子36，或者如果衬底包括引线框架，引线可包括其引脚的部分。
介质元件30的第一表面34可以与第一微电子元件12的前表面16并列。如图1A所示，衬底30可以延伸至第一微电子元件12的第一边缘27和第二微电子元件14的第二边缘35之外。在示例中，包括介质材料的衬底可称作“介质元件”30，无论其是部分地还是全部地由任何合适的介质材料制成。衬底30可以部分地或全部地由任何合适的介质材料制成。例如，衬底30可以包括柔性材料层，例如聚酰亚胺层、BT树脂层或通常用于制造带式自动键合(TAB)带的其他介质材料层。可选地，衬底30可包括相对刚性的板状材料，例如纤维增强环氧树脂的厚层，例如，Fr-4板或Fr-5板。不论使用何种材料，衬底30可由单个层或多个层组成。
返回图1A，间隔元件或支撑元件31可放置在第二微电子元件14的第一端区域21和介质元件30的一部分之间。间隔元件31可帮助将第二微电子元件支撑在衬底30的上方。这种间隔元件31可以由例如介质材料(例如硅二极管或其他材料)、半导体材料(例如硅)、或一层或多层的粘合剂或其他聚合材料制成。在特定实施例中，间隔元件可以包括金属或由金属制成。如果间隔元件包括粘合剂，粘合剂可以将第二微电子元件14连接至衬底30。在一个实施例中，间隔元件31在基本垂直于衬底的第一表面34的竖直方向可具有与第一微电子元件12的前表面16和后表面18之间的第一微电子元件12的厚度基本相等的厚度。如图1所示，如果间隔元件31包括粘合剂，该粘合剂可将第二微电子元件14连接至介质元件30。
如图1A和图2所示，衬底30还可以包括导电元件或衬底触点40以及暴露在第二表面32上的导电迹线25。导电迹线25将衬底触点40电联接至端子36。可以使用共同转让的美国申请公开No.2005/0181544中示出的方法来产生迹线25和衬底触点40，其公开内容通过引用并入本文。
回到图1A，间隔元件或支撑元件31(如粘合层)可以放置在第二微电子元件14的第一端区域21和衬底30的一部分之间。如果间隔元件31包括粘合剂，该粘合剂可以将第二微电子元件14连接到衬底30。如图1A所示，第二微电子元件14的第二端区域23可以通过键合材料60(例如可热传导的粘合剂60)键合到第一微电子元件12的第二端区域17。同样地，键合材料61，例如粘合剂(可选地，热传导的粘合剂)，可将第二微电子元件的第一端区域与间隔元件31键合。键合材料71可以设置在第一微电子元件的前表面16的大部分和衬底30的第一表面34的一部分之间。在特定的实施例中，键合材料60、61和/或71可以部分地或全部地由衬底焊接粘合剂制成，且在特定的示例中，可由低弹性模量材料(例如硅弹性体)制成。然而，在特定的实施例中，如果两个微电子元件12、14是由相同材料形成的常规半导体芯片，那么键合材料60、61和/或71可以全部地或部分地由高弹性模量粘合剂或焊料制成，这是因为，响应于温度变化，微电子元件将趋于一致地扩张或收缩。不论采用何种材料，间隔元件31可以包括单个层或多层。如下结合图4-8详细讨论的，间隔元件31可以替换为一个或多个微电子元件。
参考图1A和图2，微电子组件可以包括将第一微电子元件的触点20与至少一些端子36电连接的引线70。引线70具有与衬底30的孔39对齐的部分。在一个实施例中，引线可以包括键合元件70，如延伸穿过孔39并键合到微电子元件和衬底的触点20、40的线键合。迹线(未示出)可以沿触点40和端子36之间的衬底延伸。在一个变型中，键合线70可以包括延伸穿过孔39并电连接到衬底触点40的线键合72。线键合72的每个将触点20电联接到衬底30的相应衬底触点40。线键合70可以包括2010年10月19日申请的、发明名称为“EnhancedStacked Microelectronic Assemblies with Central Contacts and Improved ThermalCharacteristics”的美国专利申请No.12/907,522中描述的多线键合结构，其全部公开内容通过引用并入本文。如上所述以及如图2所示，迹线25将衬底触点40电连接到端子36。因此，引线50可以包括线键合52、至少一些衬底触点40，以及至少一些迹线25。所有这些元件均对第一微电子元件12的触点20和端子36之间的电连接的建立有贡献。
如图1B所示，可选地或额外地，引线(如引线键合76)可以沿如图所示的衬底30的第一表面34延伸或沿第二表面延伸进入孔39以连接到触点20。引线键合76可以电连接到通孔83，或电连接到从第一表面34延伸到衬底30的第二表面处的一个或多个端子36的任何其他类型的导电元件。因此，引线70可以包括引线键合76和通孔83。如图1B进一步所示，微电子组件10可以包括将第二微电子元件14的触点26与衬底的第二表面32的衬底触点40电互连的引线键合85。
微电子组件10进一步包括将第二微电子元件12的触点26电连接到衬底30的第二表面32处的至少一些端子36的引线50。引线50具有与孔39对齐的部分，并可以包括将第二微电子元件的触点26电连接到衬底30的第二表面32处的衬底触点40的多线键合52。线键合52可以延伸穿过孔39。每个线键合52将触点26电联接到衬底30的相应衬底触点40。引线50可以包括如2010年10月19日申请的、发明名称为“Enhanced Stacked MicroelectronicAssemblies with Central Contacts and Improved Thermal Characteristics”的美国专利申请No.12/907,522中描述的多线键合结构，其全部公开内容通过引用并入本文。如图2所示，迹线25将衬底触点40电连接到端子36。因此，引线50可以包括线键合52、至少一些衬底触点40以及至少一些迹线25。所有这些元件均对第二微电子元件14的触点26和端子36之间的电连接的建立有贡献。可选地或额外地，引线50可以包括将触点26与衬底30的第一表面34处或衬底的第二表面32处的一些衬底触点电联接的引线键合。引线键合不必延伸穿过衬底30的孔39，但是至少部分地与孔对齐。
微电子组件10还可以包括至少覆盖第一微电子元件12和第二微电子元件14的包胶模(overmold)或密封剂11。如图1A所示，包胶模11还可以覆盖延伸于第一微电子元件的第一边缘27和第二微电子元件14的第一边缘35之外的衬底30的部分。因此，包胶模11可以至少接触第一微电子元件12的第一边缘27、第二微电子元件14的第一边缘35以及衬底30的第一表面34。包胶模11可以由任何合适的材料制成，包括环氧树脂等。
如2010年10月19日申请的、发明名称为“Enhanced Stacked MicroelectronicAssemblies with Central Contacts and Improved Thermal Characteristics”的美国专利申请No.12/907,522所描述的，微电子组件10可额外地包括附接至一个或多个第一微电子元件12或第二微电子元件14的后表面的散热器或散热板，其全部公开内容通过引用并入本文。在一些实施例中，微电子组件10包括热耦合到第一微电子元件12和/或第二微电子元件14的一个或多个后面18、24(可能热耦合到边缘表面27、35、37)的散热器。散热器可以占据图1A所示的包胶模11所占据的区域的一些部分。
另外，微电子组件10还可以包括附接至介质元件30的第二表面32上的端子36的接合单元81。接合单元81可以是焊球或其他键合块和金属(例如锡、铟或其组合)块，并适用于将微电子组件10接合和电联接到电路板(例如印刷电路板)。
如图1C所示，微电子组件10的引线50可以额外地或可选地包括将第一微电子元件12的至少一些触点20与位于孔39的相对侧上的至少一些衬底触点40电连接的线键合53。因此，线键合53可以跨过衬底30的孔。此外，引线70可以可选地或额外地包括将第一微电子元件12的至少一些触点20与第二微电子元件14的至少一些触点26电连接的线键合73。
图3A描述了图1A所示的微电子组件10的变型10’。在这个变型中，替换表面16’处的触点20(或者除了表面16’处的触点20之外)，第一微电子元件12’可以包括背向衬底30’的表面18’处的触点20’。这种表面18’可以是第一微电子元件12’的前表面。表面18’可以具有邻近第一微电子元件12’的第一边缘27’的第一端部分82、邻近第二边缘29’的第二端部分84，以及第一端部分82和第二端部分84之间的中心部分86。触点20’可以设置在邻近第一边缘27’的表面18’的第一端部分82中，在表面18’的中心部分86中，或在第一端部分和中心部分中。在一个实施例中，触点20’可以布置为表面18’的中心部分86处的一行或平行的两行。
微电子组件10’可以包括与表面18’处的触点20’以及端子36电连接的引线88。在一个示例中，引线88的部分(例如线键合)可以延伸超过第一微电子元件12’的第一边缘27’到达触点40’，触点40’可以再例如通过迹线(未示出)或其他导电元件连接到端子。引线88可以包括线键合90，线键合90从触点20’开始延伸，超过第一微电子元件的第一边缘27’，到达衬底30’的第一表面处的触点40’，并且引线88可以包括衬底的其他导电结构，例如触点和端子36之间的导电迹线。如图3B所示，引线部分52’，例如线键合，可以将微电子元件14’的触点26连接到孔39’的任一侧或两侧上的触点40’。
图4和图5描述了图1A所示的微电子组件10的变型。图1A中所示的微电子组件10类似于图3A中所示的微电子组件10’，二者都具有正面放置的第一微电子元件(12，12’)。在这个变型中，使用倒装芯片放置的第三微电子元件112替换间隔元件31。但是，在所示的特定视图中，第一微电子元件101出现在图的右侧，第三微电子元件112出现在图的左侧。第三微电子元件112包括在其前表面116处的多个触点120。第三微电子元件112的触点120与衬底130的第二表面132处的至少一些触点136连接。
倒装芯片互连143将第三微电子元件112的前表面116上的触点120通过金属凸点(例如，如焊料的键合金属)电连接到衬底30的第一表面134上的至少一些触点141。然后反转微电子元件，以便金属凸点提供微电子元件的触点(例如，键合焊盘)和衬底之间的电通路以及微电子元件至衬底的机械附接。倒装芯片工艺有很多变型，但是一种常用的配置是使用焊料作为金属凸点以及使用焊料的熔融作为将其固定至键合焊盘和衬底的方法。当焊料熔化时，它可流动以形成截球体。
倒装芯片互连为第三微电子元件112提供比通过线键合连接至介质元件的其他微电子元件多的I/O(输入/输出)。此外，倒装芯片互连将第二微电子元件114和介质元件30之间的线键合路径最小化，从而减小线键合的阻抗。
在图4和图5所示的实施例中，倒装芯片互连143可以包括设置在第三微电子元件112和衬底130之间的多个实心金属凸点145，例如焊球。金属凸点145可以是导电球或导电接线柱。每个实心金属凸点145可以设置在第三微电子元件112的触点120和衬底130的衬底触点141之间(并与它们接触)，从而提供电触点120和导电元件141之间的电连接。金属凸点145可以基本由接合金属或任何其他合适的材料组成。
底充胶147可以围绕实心金属凸点145以将第三微电子元件112粘合到衬底130。底充胶147可以特别地设置在第三微电子元件112的前表面116和衬底130的第一表面134之间，以将第三微电子元件112联接到衬底130。例如，底充胶147可以全部地或部分地由聚合材料(例如环氧树脂)制成。但是，在一些实施例中，底充胶被完全省略。
图6示出了图4所示的微电子组件100的变型。微电子组件200类似于微电子组件100，但是不包括将第一微电子元件电连接到衬底触点的倒装芯片互连。相反，第一微电子元件212正面放置，且包括邻近其第一边缘227的一行或平行的多行的触点220。引线270将触点220电连接到衬底230的第二表面236上的端子236。
引线270可以包括线键合，线键合从触点220开始延伸，超过第一微电子元件212的第一边缘227，到达衬底230的第二表面234处的衬底触点240。此外，引线270可以包括通孔283或将衬底触点240和至少一些端子236电连接的任何其他合适的导电元件。通孔283可以从第一表面234延伸穿过衬底230到达衬底230的第二表面232。
微电子组件200还包括将第二微电子元件214的前表面222处的触点226电连接到至少一些端子236的引线250。引线250的部分与衬底230的孔239对齐。在这个变型中，引线270包括从触点226延伸穿过孔239的多线键合252。线键合252可以电连接到位于衬底230的第二表面处和孔239的相对侧上的衬底触点240。
图7描述了图6所示的微电子组件200的变型。图7所示的微电子组件300基本类似于图1A或1B所示的微电子组件200，但微电子组件300具有替换间隔元件31的第三微电子元件301，第三微电子元件具有类似于第一微电子元件12的电互连(如图1A)的与衬底的电互连。
图8描述了图7所示的微电子组件300的变型。在这个变型中，所示的微电子组件400安装在外部部件(例如电路板900，例如印刷电路板)上，并包括额外的电连接或引线。虽然只有图8示出了电安装在电路板(例如印刷电路板)上的微电子组件，但是本文上述的任何微电子组件可以安装至电路板或微电子组件外部的其他部件。
微电子组件400可以包括延伸跨过孔439并将第一微电子元件412的触点420与第三微电子元件401的触点490电连接的电连接或引线474。引线474可以包括线键合和/或引线键合。另一组电连接或引线476可以至少部分地与衬底430的孔439对齐，并将第一微电子元件412的至少一些触点420与第二微电子元件414的至少一些触点426电连接。引线476可以包括线键合和/或引线键合。又另一组电连接或引线478至少部分地与衬底430的孔430对齐，并将第二微电子元件414的至少一些触点426与第三微电子元件401的至少一些触点490电连接。引线478可以包括线键合和/或引线键合。
图9A示出了图1A所示的示意性侧剖视图的堆叠变型。微电子部件500可以具有堆叠的第一微电子组件510a和第二微电子组件510b(统称为微电子组件510)。每个微电子组件510可以是上面参考图1A至图8描述的任何微电子组件，且微电子组件可以彼此相同或不同。堆叠中可以有任意数量的微电子组件510，例如，如图9A所示，包括两个微电子组件510a和510b。
接合单元581例如焊球可以将第一微电子组件510a和第二微电子组件510b彼此接合和彼此电联接。这种接合单元581可以附接到暴露在第一微电子组件510a的衬底530的第二表面532处的端子536以及暴露在第二微电子组件510b的衬底530的第一表面534处的端子536’。包括堆叠微电子组件510的微电子部件500可以通过暴露在微电子部件500的顶表面501或底表面502处的接合单元581附接到电路板(例如印刷电路板)。
如图9B所示，微电子部件500可以包括邻近微电子部件的外围503布置的接合单元581。接合单元581可以位于微电子部件500的非密集(稀疏，depopulated)中心区域590的外侧。在这种实施例中，接合单元可以布置为不覆盖微电子组件510的第一微电子元件512和第二微电子元件514。这种实施例可以允许接合在一起的多个微电子组件510具有比在中心区域590中包括接合单元581的微电子部件500更低的堆叠高度。
如图9A所示，微电子部件500可以具有至少部分覆盖微电子组件510的第一微电子元件512和第二微电子元件514的单个密封剂511。在这种实施例中，微电子组件510可以不通过密封而彼此接合，然后，可以形成覆盖接合的微电子部件中的微电子元件的单个密封剂511。密封剂511可以覆盖微电子部件500的不用于与微电子部件外部的一个或多个部件电连接的部分。
在可选的实施例中，每个微电子组件510可以单独形成，每个具有各自的密封剂，类似于图10所示的实施例。在这种每个微电子组件510具有单独形成的密封剂的实施例中，这些密封的微电子组件可以彼此堆叠与接合，例如堆叠成如图10所示的结构，从而提供彼此的电连通。
在特定的示例中，微电子部件500可以用作非均匀存储器，例如，可用于智能手机应用。在这种示例中，微电子组件510中的一些微电子元件512、514可以包括如易失性RAM的存储器存储元件，一些微电子元件512、514可以包括如非易失性闪存的存储器存储元件。
图10示出了图9A所示的示意性侧剖视图的堆叠变型。微电子部件600可以具有堆叠的第一微电子组件610a和第二微电子组件610b(统称为微电子组件610)。每个微电子组件可以是上面参考图1A至图8描述的微电子组件的任一个，且微电子组件可以彼此相同或不同。堆叠中可以有任意数量的微电子组件610，例如，包括如图9A所示的两个微电子组件610a和610b。
除了至少一些接合单元681覆盖微电子组件612和614以及微电子组件610a和610b的每个可以单独形成且具有各自的密封剂611a和610b之外，微电子部件600与图9A和图9B中所示的微电子部件500相同。在可选的实施例中，微电子部件600可以具有至少部分地覆盖微电子组件610的第一微电子元件612和第二微电子元件614的单个密封剂，类似于图9A所示的单个密封剂511。
如图10所示，接合单元681可以将微电子组件610彼此接合并彼此电联接。这种接合单元681可以附接至暴露在第一微电子组件610a的衬底630的第二表面632处的端子636以及暴露在第二微电子组件610b的密封剂611b的顶表面603处的端子682。端子682可以通过线键合604与暴露在衬底630的第一表面634处的导电元件636’电连接。暴露在密封剂611a或611b的顶表面603处的端子682的一些可以覆盖微电子元件612和614的至少一个。在这种具有端子682覆盖微电子元件612和614中的至少一个的微电子组件610的微电子部件600中，每个微电子组件610的端子682和636可以布置成面阵，从而可以允许微电子组件610的面阵堆叠。
暴露在密封剂611a或611b的顶表面603处的端子682可以在顶表面上延伸，可以与顶面齐平，或可以凹入到顶表面下。这种端子682可以是任何形状，包括例如盘状(pad-like)或球状的形状。2011年5月3日申请的同时待审且共同所有的韩国专利申请No.10-2011-0041843中示出并描述了端子682和线键合604的其他形状与结构的示例，其公开内容通过引用并入本文。
线键合604在其基座607处接合到导电元件636’，并可延伸到远离各个基座607和衬底630的自由端608。线键合604的自由端608的特征为自由的，因为它们不与微电子组件610a中的微电子元件612、614或(再连接至微电子元件612、614的)任何其他导电特征电连接或以其他方式接合。换言之，自由端608可用于通过焊球或本文讨论的其他特征直接或间接地电连接到微电子组件610a外部的导电特征。通过例如密封剂611或与另一导电特征电连接或以其他方式接合而将自由端608保持在预定位置的事实不意味着它们不是如本文描述的“自由”的，只要任何这种特征不与微电子元件612、614电连接即可。相反地，基座607不是自由的，因为它如本文所描述地直接或间接地电连接到微电子元件612、614。
线键合604可以由导电材料(如铜、金、镍、焊料、铝等)制成。额外地，线键合604可以由组合材料制成，例如由具有导电材料(例如，铜或铝)的核芯(例如，具有涂覆到核芯上的涂层)制成。涂层可以是由第二导电材料(例如，铝、镍等)制成的。可选地，涂层可以是由绝缘材料制成的，例如绝缘夹套。在实施例中，用于形成线键合604的导线可以具有约15μm至150μm的厚度(即，垂直于导线的长度的尺寸)。
线键合604的自由端608具有端表面638。端表面638可以形成由多个线键合604的各个端表面形成的阵列中的触点的至少一部分。部分的线键合604可以保持不被密封剂611a覆盖(也可称为未密封)，从而使线键合可用于与位于密封剂外侧的特征或元件电连接。在实施例中，线键合604的端表面638保持不被密封剂611a覆盖，且可以暴露在密封剂的顶表面603处。其他实施例是可行的，其中除了端表面638不被密封剂覆盖之外，或者替换不被密封剂覆盖的端表面638，线键合604的边缘表面605的一部分不被密封剂611a覆盖。换言之，密封剂611a可以覆盖从第一表面开始及其之上的所有微电子组件610a，除了线键合604的一部分，例如端表面638、边缘表面605或二者的结合。
在一个实施例中，端表面638和部分的边缘表面605可以不被密封剂611a覆盖。通过允许焊料沿边缘表面605镀锡(wick)以及与边缘表面605和端表面638接合，这种配置可以提供与另一导电元件的连接(例如通过焊球等)。在图示的实施例中，表面(如密封剂611a的顶表面603)可以与衬底630的第一表面634间隔开足够大的距离以覆盖微电子元件612、614。相应地，线键合604的端部638与顶表面630平齐的微电子组件610a的实施例可以包括在衬底630上延伸至比微电子元件612、614高的高度的线键合604。
包括堆叠微电子组件610的微电子部件600可以使用暴露在微电子部件600的顶表面601或底表面602处的接合单元681附接到电路板(如印刷电路板)。
在特定示例中，微电子部件600可以用作非均匀存储器，如用于智能手机应用。在这样的实例中，微电子组件610中的一些微电子元件612、614可以包括如易失性RAM的存储器存储元件，一些微电子元件612、614可以包括如非易失性闪存的存储器存储元件。
虽然图9A、图9B和图10所示的实施例示出了通过线键合电连接到衬底的触点的微电子元件，但在其他实施例中，这种微电子元件可以通过其他连接配置(包括，例如引线键合以及倒装芯片安装至衬底的触点的一个或多个微电子元件)电连接到衬底的触点。
如图11所示，上述微电子组件可以用于构建各种电子系统。例如，根据本发明进一步实施例的系统1100包括与其他电子部件1108和1110相结合的上述微电子组件1106。在示出的示例中，部件1108是半导体芯片，而部件1110是显示屏，但是可以使用任何其他部件。当然，尽管为了说明的清楚性，图11中只示出了两个额外的部件，但系统可以包括任意数量的这种部件。微电子组件1106可以是上述组件的任一个。在进一步的变型中，可以使用任何数量的这种微电子组件。
微电子组件1106和部件1108、1110安装在共用壳体1101(以虚线示意性地示出)中且在必要时彼此电互连以形成期望的电路。在示出的示例性系统中，系统包括电路板1102(例如柔性印刷电路板)，电路板包括将部件彼此互连的许多个导体1104，图11仅示出一个导体。然而，这仅是示例性的，可以使用用于制作电连接的任何适当的结构。壳体1101被示为在例如移动电话或个人数字助理中可用的类型的便携式壳体，屏幕1110暴露在壳体的表面处。在结构1106包括感光元件(例如，成像芯片)的情况下，还可以设置用于将光导向到该结构的透镜1111或其他光学装置。此外，图11所示的简化的系统仅仅是示例性的；可以使用上述的结构形成其他系统，包括通常被认为是固定结构的系统，例如台式电脑，路由器等。
尽管此处已经参考特定具体实施例描述了本发明，应该理解的是这些实施例仅仅是对本发明的原理和应用的说明。因此，应理解的是，在不脱离通过所附权利要求限定的本发明的精神和范围的情况下，可以对上述说明性实施例进行各种修改以及可以设计其他布置。
应理解的是，此处阐述的各个从属权利要求与特征可以以与原始权利要求呈现的方式不同的方式组合。还应理解的是，结合各个实施例描述的特征可与所述实施例的其他特征共享。

Claims (42)

1.一种微电子组件，包括：
衬底，所述衬底具有相对地面对的第一表面、第二表面以及在所述第一表面和第二表面之间延伸的孔，所述衬底具有暴露在其第二表面处的第一端子；
第一微电子元件，所述第一微电子元件具有面对所述衬底的第一表面的前表面、远离所述前表面的后表面，以及在所述前表面和后表面之间延伸的边缘，所述第一微电子元件具有暴露在其所述前表面处且邻近所述第一微电子元件的所述边缘的多个触点；
第二微电子元件，所述第二微电子元件具有相对的第一边缘和第二边缘、在所述第一边缘和第二边缘之间延伸的前表面，以及设置在其前表面的中心区域且远离所述第一边缘和第二边缘的多个触点，所述第二微电子元件的前表面面对所述第一微电子元件并突出于所述第一微电子元件的边缘之外；
第一引线，所述第一引线将所述第一微电子元件的所述触点电连接到所述第一端子；
第二引线，所述第二引线将所述第二微电子元件的所述触点连接到所述第一端子，所述第一引线和第二引线具有与所述孔对齐的部分；
第二端子，所述第二端子暴露在与所述衬底的所述第二表面相对的所述微电子组件的表面处，其中至少一些所述第二端子覆盖所述第一微电子元件和所述第二微电子元件的至少一个并且通过线键合与暴露在所述衬底的所述第一表面处的导电元件电连接；以及
密封剂，所述密封剂至少部分地覆盖所述第一微电子元件和第二微电子元件以及至少部分的所述线键合，其中所述第二端子暴露在其处的所述微电子组件的所述表面为所述密封剂的表面，
其中所述线键合具有未密封边缘表面，所述未密封边缘表面位于附接至所述导电元件的所述线键合的基座与远离所述导电元件的所述线键合的端部之间，其中所述第二端子与所述未密封边缘表面电连接。
2.根据权利要求1所述的微电子组件，其中所述线键合具有远离所述导电元件的未密封端表面，所述边缘表面在所述基座和所述未密封端表面之间延伸，所述密封剂未覆盖所述未密封端表面，其中所述第二端子与所述未密封端表面和所述未密封边缘表面电连接。
3.根据权利要求1所述微电子组件，其中所述第一微电子元件和所述第二微电子元件的至少一个包括易失性随机存取存储器，且所述第一微电子元件和所述第二微电子元件的至少一个包括非易失性闪存。
4.根据权利要求1所述的微电子组件，进一步包括将所述第一微电子元件的所述触点与所述第二微电子元件的所述触点电互连的第三引线，所述第一引线、第二引线和第三引线具有与所述孔对齐的部分。
5.根据权利要求1所述的微电子组件，其中所述第一引线或第二引线中的至少一个包括从所述第一微电子元件或第二微电子元件中的至少一个的所述触点延伸的线键合。
6.根据权利要求1所述的微电子组件，其中所述第一引线和第二引线中的至少一个的与所述孔对齐的所述部分是单片导电元件的部分，所述单片导电元件具有沿所述衬底延伸到所述第一端子的第二部分。
7.根据权利要求1所述的微电子组件，进一步包括在所述第二微电子元件的所述前表面和所述衬底的所述第一表面之间的间隔元件。
8.根据权利要求1所述的微电子组件，其中所述第一微电子元件包括用于主要执行逻辑功能的芯片。
9.根据权利要求1所述的微电子组件，其中所述第二微电子元件具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。
10.根据权利要求1所述的微电子组件，其中所述第一微电子元件具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。
11.根据权利要求1所述的微电子组件，进一步包括将所述第一微电子元件的所述触点电连接到所述第一端子的第三引线，所述第一引线和第三引线连接到所述孔的相对侧上的第一端子，所述第一引线、第二引线和第三引线具有与所述孔对齐的部分。
12.根据权利要求1所述的微电子组件，进一步包括：
第三微电子元件，所述第三微电子元件设置在所述衬底的第一表面与所述第二微电子元件的所述前表面之间，所述第三微电子元件具有相对的第一边缘和第二边缘、在所述第一边缘和第二边缘之间延伸的前表面，以及设置在其所述前表面上且邻近所述第一边缘的多个触点，所述第三微电子元件的前表面面对所述衬底的所述第一表面；
第三引线，所述第三引线将所述第三微电子元件的所述触点电连接到所述第一端子；以及
第四引线，所述第四引线将所述第一微电子元件和第三微电子元件的所述触点电互连，所述第一微电子元件和第三微电子元件的所述触点位于所述孔的相对侧上，所述第一引线、第二引线、第三引线和第四引线具有与所述孔对齐的部分。
13.根据权利要求12所述的微电子组件，进一步包括第五引线，所述第五引线将所述第一微电子元件和第二微电子元件的所述触点电互连。
14.根据权利要求13所述的微电子组件，还包括第六引线，所述第六引线将所述第二微电子元件和第三微电子元件的所述触点电互连。
15.根据权利要求4所述的微电子组件，其中所述第一引线或第二引线中的至少一个包括从所述第一微电子元件或第二微电子元件中的至少一个的所述触点延伸的第二线键合。
16.根据权利要求4所述的微电子组件，其中所述第一引线或所述第二引线中的至少一个的与所述孔对齐的所述部分是单片导电元件的部分，所述单片导电元件具有沿所述衬底延伸到所述端子的第二部分。
17.根据权利要求4所述的微电子组件，进一步包括在所述第二微电子元件的所述前表面和所述衬底的所述第一表面之间的间隔元件。
18.根据权利要求4所述的微电子组件，其中所述第一微电子元件包括用于主要执行逻辑功能的芯片。
19.根据权利要求4所述的微电子组件，其中所述第二微电子元件具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。
20.根据权利要求4所述的微电子组件，其中所述第一微电子元件具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。
21.根据权利要求11所述的微电子组件，其中所述第一微电子元件包括用于主要执行逻辑功能的芯片。
22.根据权利要求11所述的微电子组件，其中所述第二微电子元件具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。
23.根据权利要求11所述的微电子组件，其中所述第一微电子元件具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。
24.根据权利要求12所述的微电子组件，其中所述第一微电子元件包括用于主要执行逻辑功能的芯片。
25.根据权利要求12所述的微电子组件，其中所述第二微电子元件具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。
26.根据权利要求12所述的微电子组件，其中所述第一微电子元件具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。
27.一种微电子部件，包括第一微电子组件和第二微电子组件，所述第一微电子组件和所述第二微电子组件均为根据权利要求1所述的微电子组件，所述第一微电子组件至少部分地覆盖所述第二微电子组件，且所述第一微电子组件的所述第一端子与所述第二微电子组件的所述第二端子接合。
28.根据权利要求27所述的微电子部件，其中至少一个所述第一微电子元件主要用于执行逻辑功能，至少一个所述第二微电子元件具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。
29.根据权利要求27所述的微电子部件，其中所述第一微电子组件的至少一些所述第一端子和所述第二微电子组件的至少一些所述第二端子布置成面阵，且其中所述第一微电子组件和第二微电子组件通过接合单元相接合，所述接合单元是烧结金属的导电块。
30.根据权利要求27所述的微电子部件，其中所述微电子组件通过邻近所述微电子部件的外围布置的接合单元彼此电连接。
31.根据权利要求30所述的微电子部件，其中所述接合单元位于所述微电子部件的非密集中心区域的外侧。
32.一种系统，包括根据权利要求1所述的微电子组件和电连接到所述微电子组件的一个或多个其他电子部件。
33.根据权利要求32所述的系统，其中至少一些所述第一端子电连接到电路板。
34.根据权利要求33所述的系统，进一步包括壳体，所述微电子组件和所述其他电子部件安装到所述壳体。
35.一种系统，包括根据权利要求4所述的微电子组件和电连接到所述微电子组件的一个或多个其他电子部件。
36.根据权利要求35所述的系统，其中所述第一端子电连接到电路板。
37.根据权利要求36所述的系统，进一步包括壳体，所述微电子组件和所述其他电子部件安装到所述壳体。
38.一种微电子部件，包括第一微电子组件和第二微电子组件，所述第一微电子组件和所述第二微电子组件均为根据权利要求4所述的微电子组件，所述第一微电子组件与所述第二微电子组件电连接，并且所述第一微电子组件至少部分地覆盖所述第二微电子组件。
39.根据权利要求38所述的微电子部件，其中所述微电子组件通过邻近所述微电子部件的外围布置的接合单元彼此电连接。
40.根据权利要求39所述的微电子部件，其中所述接合单元位于所述微电子部件的非密集中心区域的外侧。
41.根据权利要求38所述的微电子部件，其中所述第一微电子组件和所述第二微电子组件中的微电子元件的一些包括易失性随机存取存储器，所述第一微电子组件和所述第二微电子组件中的微电子元件的一些包括非易失性闪存。
42.根据权利要求38所述的微电子部件，其中至少一个所述第一微电子元件主要用于执行逻辑功能，至少一个所述第二微电子元件具有比提供任何其它功能的有源装置更多的有源装置以提供存储器存储阵列功能。
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