JP4086068B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4086068B2 JP4086068B2 JP2005370199A JP2005370199A JP4086068B2 JP 4086068 B2 JP4086068 B2 JP 4086068B2 JP 2005370199 A JP2005370199 A JP 2005370199A JP 2005370199 A JP2005370199 A JP 2005370199A JP 4086068 B2 JP4086068 B2 JP 4086068B2
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2224/732—Location after the connecting process
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- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
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- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Description
図1は本発明になる半導体装置の第1の実施の形態の断面構造図を示す。同図中、図7と同一構成部分には同一符号を付してある。図1において、中継基板1の上に各々同一チップサイズのLSIチップ2が4層積層されており、各LSIチップ2には各LSIチップ2の間を電気的に接続する貫通電極3が形成されており、また、はんだバンプ4で互いに機械的及び電気的に接続されている。中継基板1は、LSIチップ2の積層構造を外部のPWB(Printed Wiring Board)に実装するときに、PWBのピッチに対応させるために、パッドピッチの拡大やPWBとLSIとの熱膨張係数の差を緩和するために使用されるもので、LSIパッケージとしてハンドリングできるという作用も有する。
次に、本発明の第2の実施の形態について説明する。図2(A)は本発明になる半導体装置の第2の実施の形態の断面構造図を示す。同図中、図1と同一構成部分には同一符号を付し、その説明を省略する。図2(A)に示す構造の第2の実施の形態は、基本的構成は上記の第1の実施の形態と同様であるが、LSIチップ2の下面の放熱構造について、さらに工夫している。
次に、本発明の第3の実施の形態について説明する。図3は本発明になる半導体装置の第3の実施の形態の断面構造図を示す。同図中、図1と同一構成部分には同一符号を付し、その説明を省略する。図3において、中継基板1の上に半導体チップサイズが上部に行くほど小さくなるように、下から上に順にLSIチップ2a、2b、2cが3層積層されている。各LSIチップ2a、2b、2cには隣接するLSIチップ2a、2b、2cを電気的に接続するための貫通電極3が形成されており、また、各LSIチップ2a、2b、2c間は、はんだバンプ4で互いに機械的、及び、電気的に接続されている。
次に、本発明の第4の実施の形態について説明する。図4(A)は本発明になる半導体装置の第4の実施の形態の断面図を示す。同図中、図3と同一構成部分には同一符号を付し、その説明を省略する。図4(A)に示す構造の第4の実施の形態は、基本的構成は上記の第3の実施の形態と同様であるが、LSIチップ2a〜2cの下面の放熱構造について、さらに工夫している。
次に、本発明の第5の実施の形態について説明する。図5は本発明になる半導体装置の第5の実施の形態の断面図を示す。同図中、図3と同一構成部分には同一符号を付し、その説明を省略する。図5において、中継基板1上にLSIチップが3層積層された構造であり、かつ、それらLSIチップは、半導体チップサイズが上部に行くほど小さくなるように積層されている点は、第3及び第4の実施の形態と同様であるが、本実施の形態では、最上部のLSIチップが2つのLSIチップ2dと2eとからなる点に特徴がある。
次に、本発明の第6の実施の形態について説明する。図6は本発明になる半導体装置の第6の実施の形態の断面図を示す。同図中、図5と同一構成部分には同一符号を付し、その説明を省略する。図6に示す実施の形態は、第5の実施の形態では最上部のLSIチップであったLSIチップ2eの更に上部に、LSIチップ2eとチップサイズが同一か小さなLSIチップ2fを積層した点に特徴がある。
2、2a〜2c LSIチップ
3 貫通電極
4 はんだバンプ
5、9、14、18、19 放熱シート
6、8、13、17、20 ヒートシンク
7 はんだボール
10 熱伝導性アンダーフィル樹脂
11、15 LSI下放熱シート
12、16 開口部
Claims (8)
- 互いにチップサイズが異なる複数のLSIチップが、チップサイズが大きいものから順に基板上に順次積層され、最上部のLSIチップは最もチップサイズが小さなLSIチップである積層構造の半導体装置であって、
上下に隣接する2つの前記LSIチップとの間又は最下部の前記LSIチップの下面と前記基板との間に設けられた熱伝導性部材と、
前記複数のLSIチップのうち、最上部のLSIチップの表面、及び上下に隣接するLSIチップのうち上部に隣接するLSIチップの範囲より外側に現れた下部側のLSIチップの表面と、前記複数のLSIチップの各側面と、前記熱伝導性部材の側面にそれぞれ接触し、かつ、被覆する放熱シートと、
前記放熱シートの前記LSIチップ側面の反対側表面が内面に接触され、かつ、前記積層構造の全体を覆うように、該積層構造に対応した階段状の掘り込みが底面に形成されたヒートシンクと
を有することを特徴とする半導体装置。 - 前記最上部のLSIチップは、同じ最上層に設けられた2つ以上のLSIチップからなることを特徴とする請求項1記載の半導体装置。
- 前記熱伝導性部材は、熱伝導性アンダーフィル樹脂であることを特徴とする請求項1又は2記載の半導体装置。
- 複数のLSIチップが基板上に積層された積層構造の半導体装置において、
上下に隣接する前記LSIチップとの間又は最下部の前記LSIチップの下面と前記基板との間に設けられており、上下に隣接する前記複数のLSIチップ間の電気的接続及び機械的接続を行うはんだバンプを逃がす開口部が穿設された低弾性係数の高分子材料からなる第1の放熱シートと、
前記複数のLSIチップのうち、最上部のLSIチップの表面及び前記複数のLSIチップの各側面と前記第1の放熱シートの端部をそれぞれ被覆する第2の放熱シートと、
前記第2の放熱シートの前記LSIチップに接する面と反対側表面が内面に接触され、かつ、前記積層構造の全体を覆うヒートシンクと
を有することを特徴とする半導体装置。 - 互いにチップサイズが異なる複数のLSIチップが、チップサイズが大きいものから順に基板上に順次積層され、最上部のLSIチップは最もチップサイズが小さなLSIチップである積層構造の半導体装置であって、
上下に隣接する2つの前記LSIチップとの間又は最下部の前記LSIチップの下面と前記基板との間に設けられた第1の放熱シートと、
前記複数のLSIチップのうち、最上部のLSIチップの表面、及び上下に隣接するLSIチップのうち上部に隣接するLSIチップの範囲より外側に現れた下部側のLSIチップの表面と、前記複数のLSIチップの各側面と、前記熱伝導性部材の側面にそれぞれ接触し、かつ、被覆する第2の放熱シートと、
前記第2の放熱シートの前記LSIチップ側面の反対側表面が内面に接触され、かつ、前記積層構造の全体を覆うように、該積層構造に対応した階段状の掘り込みが底面に形成されたヒートシンクと
を有することを特徴とする半導体装置。 - 前記最上部のLSIチップは、同じ最上層に設けられた2つ以上のLSIチップからなることを特徴とする請求項4又は5記載の半導体装置。
- 前記第1の放熱シートは、上下に隣接する前記複数のLSIチップ間の電気的接続及び機械的接続を行うはんだバンプを逃がす開口部が穿設された低弾性係数の高分子材料からなることを特徴とする請求項5又は6記載の半導体装置。
- 前記LSIチップに替えて積層可能な電子部品が積層されてなることを特徴とする請求項1乃至7のうちいずれか一項記載の半導体装置。
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JP2005370199A JP4086068B2 (ja) | 2004-12-27 | 2005-12-22 | 半導体装置 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102280418A (zh) * | 2010-06-09 | 2011-12-14 | 海力士半导体有限公司 | 带有散热装置的半导体封装 |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
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US7429792B2 (en) * | 2006-06-29 | 2008-09-30 | Hynix Semiconductor Inc. | Stack package with vertically formed heat sink |
KR100809696B1 (ko) | 2006-08-08 | 2008-03-06 | 삼성전자주식회사 | 사이즈가 상이한 복수의 반도체 칩이 적층된 멀티 칩패키지 및 그 제조방법 |
KR100807050B1 (ko) * | 2006-08-23 | 2008-02-25 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조방법 |
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US8970028B2 (en) | 2011-12-29 | 2015-03-03 | Invensas Corporation | Embedded heat spreader for package with multiple microelectronic elements and face-down connection |
US9153520B2 (en) | 2011-11-14 | 2015-10-06 | Micron Technology, Inc. | Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods |
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Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3207138B2 (ja) * | 1997-07-29 | 2001-09-10 | 三菱電機株式会社 | 水蒸発式冷却装置 |
JP4381533B2 (ja) * | 1999-12-14 | 2009-12-09 | 株式会社ケミトロニクス | 冷却器付半導体集積回路装置及びその製造方法 |
JP2001189412A (ja) * | 1999-12-27 | 2001-07-10 | Mitsubishi Electric Corp | 半導体装置および半導体実装方法 |
JP2002176135A (ja) * | 2000-12-07 | 2002-06-21 | Toshiba Corp | 積層型の半導体装置とその製造方法 |
JP2002261232A (ja) * | 2001-03-01 | 2002-09-13 | Hitachi Ltd | 半導体装置 |
JP4079604B2 (ja) * | 2001-05-30 | 2008-04-23 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP3944898B2 (ja) * | 2001-12-19 | 2007-07-18 | ソニー株式会社 | 半導体装置 |
JP2003283144A (ja) * | 2002-03-27 | 2003-10-03 | Minolta Co Ltd | 回路基板の放熱構造 |
JP2004111656A (ja) * | 2002-09-18 | 2004-04-08 | Nec Electronics Corp | 半導体装置及び半導体装置の製造方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102280418A (zh) * | 2010-06-09 | 2011-12-14 | 海力士半导体有限公司 | 带有散热装置的半导体封装 |
KR101394205B1 (ko) * | 2010-06-09 | 2014-05-14 | 에스케이하이닉스 주식회사 | 반도체 패키지 |
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