JP5115200B2 - 電子素子、それを有するパッケージ及び電子装置 - Google Patents
電子素子、それを有するパッケージ及び電子装置 Download PDFInfo
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- JP5115200B2 JP5115200B2 JP2007545125A JP2007545125A JP5115200B2 JP 5115200 B2 JP5115200 B2 JP 5115200B2 JP 2007545125 A JP2007545125 A JP 2007545125A JP 2007545125 A JP2007545125 A JP 2007545125A JP 5115200 B2 JP5115200 B2 JP 5115200B2
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- heat
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
Description
(付記2) 前記放熱線は前記回路素子と電気的に絶縁されていることを特徴とする、付記1記載の電子素子。
(付記4) 前記外部基板と接続される複数のバンプを更に有し、前記信号線と前記放熱線は異なるバンプに接続されていることを特徴とする付記2記載の電子素子。
(付記6) 前記放熱線に接続され、前記放熱線からの熱を分散する分散部材を更に有することを特徴とする付記1記載の電子素子。(4)
(付記7) 前記分散部材は前記信号線の配線層のうち前記回路素子から最も遠い配線層に形成されることを特徴とする付記4記載の電子素子。(5)
(付記8) 前記回路素子を搭載し、当該回路素子からの熱を放熱するサブストレートと、前記サブストレートを貫通して前記放熱線に接続される熱伝導部とを更に有することを特徴とする付記1記載の電子素子。(6)
(付記9) 前記放熱線は前記信号線の積層方向とは垂直に延在して外部に露出することを特徴とする付記1記載の電子素子。(7)
(付記10) 回路素子と、前記回路素子と熱的に接触し、前記回路素子で発生する熱を放熱する放熱線とを有する電子素子と、前記回路素子が搭載され、前記回路素子と少なくとも電気的に接続する基板と、前記基板に設けられ、外部との電気的接続をなすピンと、を備えることを特徴とする回路パッケージ。(8)
(付記11) 前記回路パッケージは、前記電子素子と熱的に接続され、前記電子素子で発生した熱を外部に導く熱伝導部をさらに備えることを特徴とする、付記8に記載の回路パッケージ。(9)
(付記12) 回路素子と、前記回路素子で発生した熱を放熱する放熱配線と、前記回路素子と電気的に接続される信号配線とを備えた電子回路と、前記電子回路が電気的に接続するように搭載される回路基板と、を備えたことを特徴とする、電子装置。(10)
Claims (8)
- 外部基板と信号を送受信する回路素子と、
複数の配線層と、
前記配線層に形成され、前記外部基板と前記回路素子とを電気的に接続する複数の信号線と、
前記配線層に設けられ、前記回路素子から離れて当該回路素子の表面に平行に延在する部分を含み、前記回路素子と熱的に接触し、前記回路素子を放熱する放熱線と、
前記配線層に設けられ、前記放熱線に接続され、前記放熱線からの熱を分散するメッシュ部材と、を有し、
前記複数の信号線のうち少なくとも1つは、前記メッシュ部材の中を絶縁された状態で通過することを特徴とする電子素子。 - 前記電子素子は、前記外部基板と接続されるバンプを有し、
前記放熱線は前記バンプに熱的に接続されていることを特徴とする請求項1記載の電子素子。 - 前記メッシュ部材は前記信号線の配線層のうち前記回路素子から最も遠い配線層に形成されることを特徴とする請求項1記載の電子素子。
- 前記回路素子に対して前記配線層とは反対側に配置され、前記回路素子を搭載し、当該回路素子からの熱を放熱するサブストレートと、
前記サブストレートを貫通して前記放熱線に接続される熱伝導部とを更に有することを特徴とする請求項1記載の電子素子。 - 前記放熱線は前記信号線の積層方向とは垂直に延在して外部に露出することを特徴とする請求項1記載の電子素子。
- 請求項1から5のいずれか1つに記載の電子素子と、
前記回路素子が搭載され、前記回路素子と少なくとも電気的に接続する基板と、
前記基板に設けられ、外部との電気的接続をなすピンと、を備えることを特徴とする回路パッケージ。 - 前記回路パッケージは、前記電子素子と熱的に接続され、前記電子素子で発生した熱を外部に導く熱伝導部をさらに備えることを特徴とする、請求項6に記載の回路パッケージ。
- 請求項1から5のいずれか1つに記載の電子素子と、
前記電子素子が電気的に接続するように搭載される回路基板と、を備えたことを特徴とする、電子装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2005/021053 WO2007057952A1 (ja) | 2005-11-16 | 2005-11-16 | 電子素子、それを有するパッケージ及び電子装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2007057952A1 JPWO2007057952A1 (ja) | 2009-04-30 |
JP5115200B2 true JP5115200B2 (ja) | 2013-01-09 |
Family
ID=38048344
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007545125A Expired - Fee Related JP5115200B2 (ja) | 2005-11-16 | 2005-11-16 | 電子素子、それを有するパッケージ及び電子装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7643302B2 (ja) |
EP (1) | EP1950805A4 (ja) |
JP (1) | JP5115200B2 (ja) |
WO (1) | WO2007057952A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5512992B2 (ja) * | 2009-03-27 | 2014-06-04 | 国立大学法人 鹿児島大学 | ヒートシンク一体化パッケージ及びその製造方法 |
US9538633B2 (en) * | 2012-12-13 | 2017-01-03 | Nvidia Corporation | Passive cooling system integrated into a printed circuit board for cooling electronic components |
US10061364B2 (en) * | 2014-10-28 | 2018-08-28 | Hitachi, Ltd. | Method for cooling storage device |
US9832876B2 (en) * | 2014-12-18 | 2017-11-28 | Intel Corporation | CPU package substrates with removable memory mechanical interfaces |
RU179613U1 (ru) * | 2017-10-13 | 2018-05-21 | Акционерное общество "Ордена Трудового Красного Знамени научно-исследовательский институт автоматической аппаратуры им. академика В.С. Семенихина" (АО "НИИАА") | Портативное защищенное электронно-вычислительное устройство с резистентной системой принудительного охлаждения |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03278539A (ja) * | 1990-03-28 | 1991-12-10 | Nec Corp | 半導体装置 |
JP2000306998A (ja) * | 1999-04-20 | 2000-11-02 | Nec Corp | 半導体装置及びその製造方法 |
JP2004072017A (ja) * | 2002-08-09 | 2004-03-04 | Ricoh Co Ltd | 半導体集積回路装置及びその製造方法 |
JP2005158777A (ja) * | 2003-11-20 | 2005-06-16 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3047986B2 (ja) * | 1990-07-25 | 2000-06-05 | 株式会社日立製作所 | 半導体装置 |
JP3375224B2 (ja) * | 1995-02-03 | 2003-02-10 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
FR2735648B1 (fr) * | 1995-06-13 | 1997-07-11 | Bull Sa | Procede de refroidissement d'un circuit integre monte dans un boitier |
JPH11238734A (ja) * | 1998-02-20 | 1999-08-31 | Nec Corp | 半導体集積回路 |
JP3446818B2 (ja) | 1999-05-10 | 2003-09-16 | 日本電気株式会社 | 半導体装置の実装構造、及びその製造方法 |
JP2000331835A (ja) * | 1999-05-21 | 2000-11-30 | Taiyo Yuden Co Ltd | 積層電子部品及び回路モジュール |
JP2002011902A (ja) | 2000-06-27 | 2002-01-15 | Sharp Corp | 画像形成装置 |
TW462121B (en) * | 2000-09-19 | 2001-11-01 | Siliconware Precision Industries Co Ltd | Heat sink type ball grid array package |
JP2002110902A (ja) | 2000-10-04 | 2002-04-12 | Toshiba Corp | 半導体素子及び半導体装置 |
TW490820B (en) * | 2000-10-04 | 2002-06-11 | Advanced Semiconductor Eng | Heat dissipation enhanced ball grid array package |
US6867493B2 (en) * | 2000-11-15 | 2005-03-15 | Skyworks Solutions, Inc. | Structure and method for fabrication of a leadless multi-die carrier |
US7161239B2 (en) * | 2000-12-22 | 2007-01-09 | Broadcom Corporation | Ball grid array package enhanced with a thermal and electrical connector |
JP2003017494A (ja) | 2001-07-04 | 2003-01-17 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US6552907B1 (en) * | 2001-10-11 | 2003-04-22 | Lsi Logic Corporation | BGA heat ball plate spreader, BGA to PCB plate interface |
EP1351301B1 (en) * | 2002-04-03 | 2009-06-17 | Panasonic Corporation | Semiconductor built-in millimeter-wave band module |
US6657311B1 (en) * | 2002-05-16 | 2003-12-02 | Texas Instruments Incorporated | Heat dissipating flip-chip ball grid array |
JP2004071670A (ja) * | 2002-08-02 | 2004-03-04 | Fuji Photo Film Co Ltd | Icパッケージ、接続構造、および電子機器 |
US6657864B1 (en) * | 2002-12-16 | 2003-12-02 | International Business Machines Corporation | High density thermal solution for direct attach modules |
US6753600B1 (en) * | 2003-01-28 | 2004-06-22 | Thin Film Module, Inc. | Structure of a substrate for a high density semiconductor package |
US7345364B2 (en) | 2004-02-04 | 2008-03-18 | Agere Systems Inc. | Structure and method for improved heat conduction for semiconductor devices |
US7269017B2 (en) * | 2004-11-19 | 2007-09-11 | Delphi Technologies, Inc. | Thermal management of surface-mount circuit devices on laminate ceramic substrate |
US7148554B2 (en) * | 2004-12-16 | 2006-12-12 | Delphi Technologies, Inc. | Discrete electronic component arrangement including anchoring, thermally conductive pad |
-
2005
- 2005-11-16 WO PCT/JP2005/021053 patent/WO2007057952A1/ja active Application Filing
- 2005-11-16 EP EP05806818A patent/EP1950805A4/en not_active Withdrawn
- 2005-11-16 JP JP2007545125A patent/JP5115200B2/ja not_active Expired - Fee Related
-
2008
- 2008-05-15 US US12/121,444 patent/US7643302B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03278539A (ja) * | 1990-03-28 | 1991-12-10 | Nec Corp | 半導体装置 |
JP2000306998A (ja) * | 1999-04-20 | 2000-11-02 | Nec Corp | 半導体装置及びその製造方法 |
JP2004072017A (ja) * | 2002-08-09 | 2004-03-04 | Ricoh Co Ltd | 半導体集積回路装置及びその製造方法 |
JP2005158777A (ja) * | 2003-11-20 | 2005-06-16 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP1950805A1 (en) | 2008-07-30 |
US7643302B2 (en) | 2010-01-05 |
WO2007057952A1 (ja) | 2007-05-24 |
US20080218965A1 (en) | 2008-09-11 |
EP1950805A4 (en) | 2010-03-03 |
JPWO2007057952A1 (ja) | 2009-04-30 |
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