CN113632218A - 电子装置 - Google Patents
电子装置 Download PDFInfo
- Publication number
- CN113632218A CN113632218A CN202080023587.1A CN202080023587A CN113632218A CN 113632218 A CN113632218 A CN 113632218A CN 202080023587 A CN202080023587 A CN 202080023587A CN 113632218 A CN113632218 A CN 113632218A
- Authority
- CN
- China
- Prior art keywords
- layer
- electronic device
- diffusion layer
- package
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000009792 diffusion process Methods 0.000 claims abstract description 84
- 239000002184 metal Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000011347 resin Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- 238000000465 moulding Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 description 11
- 230000017525 heat dissipation Effects 0.000 description 10
- 229910000679 solder Inorganic materials 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- XVIZMMSINIOIQP-UHFFFAOYSA-N 1,2-dichloro-3-(2-chlorophenyl)benzene Chemical compound ClC1=CC=CC(C=2C(=CC=CC=2)Cl)=C1Cl XVIZMMSINIOIQP-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 101100369785 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) TIM18 gene Proteins 0.000 description 2
- 101100277764 Schizosaccharomyces pombe (strain 972 / ATCC 24843) sdh4 gene Proteins 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
本发明提供电子装置,具备:上封装件(10),具备上芯片(10a);下封装件(12),具备下芯片(12a);印刷基板(16),在上部层叠设置上述上封装件和上述下封装件;以及热扩散层(26、30),在上述下封装件中,配置于下芯片附近。
Description
相关申请的交叉引用:本申请基于在2019年3月28日申请的日本申请号2019-063313号,此处引用其记载内容。
技术领域
本公开涉及电子装置。
背景技术
已知有在印刷基板上安装有PoP(Package on Package:叠层封装)的电子装置,其中,PoP是层叠两个IC封装件而形成的。
专利文献1:美国专利第9746889号说明书
专利文献2:美国专利申请公开第2017/0294422号说明书
发明内容
在上述电子装置的情况下,存在在下侧的IC封装件中产生的热量无法充分散热的问题。特别是,在下侧的IC封装件产生的热量大于上侧的IC封装件产生的热量的情况下,该课题变得显著。
本公开是鉴于上述课题而完成的,其目的在于提供一种通过提高散热性而使可靠性提高的电子装置。
在本公开的一个方式中,电子装置具备:上封装件,具备上芯片;下封装件,具备下芯片;印刷基板,在上部层叠设置上述上封装件和上述下封装件;以及热扩散层,在上述下封装件,配置于下芯片附近。
根据本公开的一个方式的电子装置,由于热量从下芯片高效地向热扩散层传导,所以可高效地实施从下芯片的热量释放。由此,能够提高电子装置整体的散热性,因此能够提供可靠性提高的电子装置。
附图说明
通过参照附图进行下述的详细描述,有关本公开的上述目的以及其它目的、特征、优点变得更加明确。
图1是表示第一实施方式的电子装置的简要结构的纵剖视图。
图2是从上方观察电子装置的俯视图,且是表示散热面积的简要结构的概念图。
图3是表示第二实施方式的电子装置的简要结构的纵剖视图。
图4是表示第二实施方式的电子装置的简要结构的纵剖视图,且是放大图3的区域S后的图。
具体实施方式
以下,参照附图对本公开的实施方式所涉及的电子装置进行说明。在以下的说明中,对于与前面出现相同的要素标注相同的附图标记,并省略其说明。另外,在附图中,将电子装置1的金属外壳14侧设为上方,将印刷基板16侧设为下方。
(第一实施方式)
如图1和图2所示,第一实施方式的电子装置1是层叠两个IC封装件而成的所谓的PoP。电子装置1具备印刷基板16(Printed Circuit Board,以下称为PCB)、下封装件12、上封装件10以及覆盖这些部件的金属外壳14。电子装置1形成为平板大致矩形形状。电子装置1所具备的上封装件10以及下封装件12也形成为平板大致矩形形状。
在PCB16的上部层叠配置下封装件12和上封装件10。在上封装件10与下封装件12之间,配置有多个焊锡球20。上封装件10和下封装件12通过多个焊锡球20连接。在下封装件12与PCB16之间配置有多个焊锡球22。下封装件12和PCB16通过多个焊锡球22连接。
在上封装件10的上表面与金属外壳14的内侧顶面之间设置有热界面材料18(Thermal Interface Material,以下称为TIM)。TIM18由热导率较高的物质构成,例如包含硅、石墨而构成。TIM18与上封装件10的上表面和金属外壳14的内侧顶面接触,使来自上封装件10的热量传导到金属外壳14。
上封装件10具备上芯片10a、上层10b以及下层10c。上芯片10a配置在下层10c上。上芯片10a被上层10b覆盖上表面以及侧面。此外,上芯片10a也可以为被上层10b覆盖上表面以及侧面的一部分的结构。上芯片10a是在未图示的半导体基板上搭载有多个晶体管以及布线等的集成电路,下层10c例如是印刷基板,上层10b例如是模制树脂。上芯片10a形成为平板大致矩形形状。
下封装件12具备下芯片12a、上层12b、中间层12c、下层12d以及热扩散层26。下芯片12a配置在下层12d上,通过热扩散层26接触并覆盖下芯片12a的上表面以及侧面的一部分。热扩散层26至少配置于下芯片12a附近。热扩散层26的横向尺寸大于下芯片12a的横向尺寸,热扩散层26的上表面的面积大于下芯片12a的上表面的面积。下芯片12a以及热扩散层26形成为平板大致矩形形状。
中间层12c与下芯片12a的侧面以及热扩散层26的下半部分接触并覆盖下芯片12a和热扩散层26的侧面以及热扩散层26的下表面的一部分。另外,上层12b位于中间层12c之上,覆盖热扩散层26的上表面以及侧面的一部分。中间层12c具备堆叠导通孔24,该堆叠导通孔24位于下芯片12a以及热扩散层26的横向,且与上层12b和下层12d接触。
堆叠导通孔24例如是由焊锡构成的焊锡球。作为堆叠导通孔24,也可以使用以铅和锡为主要成分的材料,也可以使用还添加有铜的材料、或者不包含铅的无铅焊锡。或者,也可以构成为在中间层12c设置贯通孔,并向贯通孔内埋入例如铜等金属而形成的埋入金属。
热扩散层26构成为使用热导率较高的物质,热导率高于周围的材料、例如模制树脂的热导率。作为热扩散层26,例如由铜等金属、石墨等构成。热扩散层26通过与下芯片12a接触来传导从下芯片12a产生的热量,并进一步从热扩散层26的表面散热。从热扩散层26散发的热量的大部分以具有规定角度的宽度向上方扩散并传导。该扩散的热量传导到金属外壳14。
此时,如图1和图2所示,将从下芯片12a向热扩散层26传导,并且能够不会较大地损伤该热量地将该热量传递到金属外壳14的面积称为散热面积A。在图1和图2中,将散热面积A表示为位于金属外壳14的下表面。若热量按照下芯片12a→热扩散层26→金属外壳14传导,则传导热量的面积也变大。从电子装置1的上方观察,散热面积A至少比下芯片12a的平面面积大。另外,从电子装置1的上方观察,散热面积A大于热扩散层26的面积。此外,热量从热扩散层26扩散至金属外壳14的角度根据存在于热扩散层26与金属外壳14之间的材质等不同。在该情况下,散热面积A的平面形状反映将热量传递到金属外壳14的热扩散层26的形状,形成为大致矩形形状。
下芯片12a是在未图示的半导体基板上形成有多个晶体管以及布线等的集成电路,上层12b以及下层12d例如是印刷基板,中间层12c例如是模制树脂。热扩散层26的热导率构成为至少高于中间层12c的热导率,即高于模制树脂的热导率。
根据上述说明的第一实施方式的电子装置1,起到以下的效果。
热扩散层26配置于下芯片12a附近,接触并覆盖下芯片12a的上表面,另外,热扩散层26的热导率高于构成中间层12c的模制树脂的热导率。在该情况下,从下芯片12a产生的热量向热扩散层26传导,从热扩散层26热扩散到达金属外壳14并向外部散发,根据上述结构,热扩散层26的热导率构成为大于模制树脂的热导率。因此,热量从下芯片12a向热扩散层26高效地传导。由此,可高效地实施从下芯片12a的热量释放。
另外,热扩散层26的上表面的面积大于下芯片12a的上表面的面积,且热扩散层26配置于上封装件10与金属外壳14之间。根据该结构,在下芯片12a中产生的热量向热扩散层26传导。也就是说,在下芯片12a中产生的热量被传递到覆盖下芯片12a的上方、且上表面的面积大于下芯片12a的面积的热扩散层26,进一步,传导到热扩散层26的热量从该热扩散层26的上表面散发。
而且,来自热扩散层26的热量在散热面积A扩展并传导到金属外壳14。通过设为这样的结构,由于下芯片12a产生的热量经由热扩散层26高效地传导到金属外壳14,因此能够提高电子装置1整体的散热性。由此,能够提供可靠性提高的电子装置。
(第二实施方式)
接下来,参照图3和图4对第二实施方式进行说明。在第二实施方式中,电子装置1具备与第一实施方式大致相同的结构,但在以下的方面不同。
下封装件12具备下芯片12a,并从上方开始具备上层12e、中间层12f以及下层12g。下芯片12a配置在下层12d上。热扩散层30以及热扩散部32配置于下芯片12a附近。
如图3和图4所示,热扩散层30设置于配置下芯片12a的中间层12f的正上方的上层12e。作为热扩散层30,使用热导率较高的物质,例如由铜等金属等构成。
上层12e是PCB,如图4所示,在内部包括多个布线层13和热扩散层30。布线层13是构成作为PCB的上层12e的电路的布线层。布线层13和热扩散层30由相同的材质形成。热扩散层30的膜厚大于布线层13的膜厚。另外,热扩散层30在设置于上层12e的布线层中设置于最下层。也就是说,热扩散层30由与布线层13相同的材料形成,构成为设置于上层12e的多个布线层的最下层。另外,在该情况下,热扩散层30构成为厚度比布线层13厚。通过增大热扩散层30的厚度,提高热传导效率。由于热扩散层30的平面的大小构成为大于下芯片12a的上表面的面积,因此能够使从下芯片12a传导的热量高效地传导到热扩散层30。
另外,在第二实施方式中,具备以在上下即厚度方向上贯通中间层12f的方式设置的多个热扩散部32。热扩散部32例如是由焊锡构成的焊锡球。作为热扩散部32,可以使用以铅和锡为主要成分的材料,也可以使用还添加有铜的材料、或者不包含铅的无铅焊锡。或者,热扩散部32也可以构成为在中间层12f设置贯通孔,并向贯通孔内埋入例如铜等金属而形成的贯通电极。热扩散层30以及热扩散部32构成为热导率高于热扩散层30以及热扩散部32的周围的材料、例如模制树脂的热导率。
根据上述说明的第二实施方式的电子装置1,起到以下的效果。
根据第二实施方式的电子装置1,获得与第一实施方式的电子装置1同样的效果。进一步,由于热扩散层30构成为设置于上层12b的布线层13,因此能够使用布线形成工序形成热扩散层30。因此,热扩散层30的形成变得容易。另外,由于将热扩散层30设置为下芯片12a的正上方的上层12e中的最下层,因此能够使热扩散层30配置于下芯片12a附近。进一步,将热扩散层30的厚度构成为比布线层13厚。因此,从下芯片12a向热扩散层30的热传导效率提高,能够使下芯片12a产生的热量高效地传导到热扩散层30。
另外,在下芯片12a的横向的附近配置热扩散部32。在下芯片12a的横向传导的热量能够传导到热扩散部32,并从热扩散部32传递到与其连接的上层12e并传导到热扩散层30。因此,由于热扩散部32的存在,下芯片12a产生的热量进一步高效地传导到金属外壳14,因此能够进一步提高电子装置1整体的散热性。
本公开以实施例为基准进行了描述,但应理解为本公开并不限定于该实施例、构造。本公开也包含各种变形例、等同范围内的变形。其中,各种组合、方式,进一步仅包含它们中一个要素、一个以上、或一个以下的其它组合、方式也纳入到本公开的范畴、思想范围。
Claims (11)
1.一种电子装置,具备:
上封装件(10),具备上芯片(10a);
下封装件(12),具备下芯片(12a);
印刷基板(16),在上部层叠设置上述上封装件和上述下封装件;以及
热扩散层(26、30),在上述下封装件中,配置于上述下芯片附近。
2.根据权利要求1所述的电子装置,其中,
上述热扩散层(26)接触并覆盖上述下芯片的上表面。
3.根据权利要求1或2所述的电子装置,其中,
上述热扩散层(26、30)的上表面的面积大于上述下芯片的上表面的面积。
4.根据权利要求1~3中任一项所述的电子装置,其中,
上述热扩散层的热导率大于模制树脂的热导率。
5.根据权利要求1~4中任一项所述的电子装置,其中,
还具备金属外壳(14),上述金属外壳覆盖上述上封装件的上表面,
上述热扩散层配置于上述上封装件与上述金属外壳之间。
6.根据权利要求1~5中任一项所述的电子装置,其中,
上述热扩散层(26)与上述下芯片接触。
7.根据权利要求1~6中任一项所述的电子装置,其中,
还具备热扩散部(32),上述热扩散部是设置于上述下芯片附近的贯通电极。
8.根据权利要求1~7中任一项所述的电子装置,其中,
上述下封装件具备上层(12e)、中间层(12f)以及下层(12g),上述上层具备多个布线层(13),
上述热扩散层(30)是设置于上述上层的布线层。
9.根据权利要求8所述的电子装置,其中,
上述上层位于上述下芯片的正上方。
10.根据权利要求8或9所述的电子装置,其中,
上述热扩散层的厚度比上述布线层的厚度厚。
11.根据权利要求8~10中任一项所述的电子装置,其中,
上述热扩散层是多个上述布线层中的最下层。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019063313A JP2020167181A (ja) | 2019-03-28 | 2019-03-28 | 電子装置 |
JP2019-063313 | 2019-03-28 | ||
PCT/JP2020/010547 WO2020195834A1 (ja) | 2019-03-28 | 2020-03-11 | 電子装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113632218A true CN113632218A (zh) | 2021-11-09 |
Family
ID=72611428
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202080023587.1A Withdrawn CN113632218A (zh) | 2019-03-28 | 2020-03-11 | 电子装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20220013428A1 (zh) |
JP (1) | JP2020167181A (zh) |
CN (1) | CN113632218A (zh) |
WO (1) | WO2020195834A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113632227A (zh) * | 2019-03-28 | 2021-11-09 | 株式会社电装 | 电子装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103560090A (zh) * | 2013-10-31 | 2014-02-05 | 中国科学院微电子研究所 | 一种用于PoP封装的散热结构的制作方法 |
CN103715153A (zh) * | 2012-10-04 | 2014-04-09 | 台湾积体电路制造股份有限公司 | 热增强型堆叠封装(PoP) |
CN103811356A (zh) * | 2012-11-09 | 2014-05-21 | 辉达公司 | 将cpu/gpu/逻辑芯片嵌入堆叠式封装结构的衬底的方法 |
CN104064551A (zh) * | 2014-06-05 | 2014-09-24 | 华为技术有限公司 | 一种芯片堆叠封装结构和电子设备 |
US20150115467A1 (en) * | 2013-10-30 | 2015-04-30 | Kyol PARK | Package-on-package device |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102134133B1 (ko) * | 2013-09-23 | 2020-07-16 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
KR102327548B1 (ko) * | 2017-10-17 | 2021-11-16 | 삼성전자주식회사 | 반도체 패키지 |
-
2019
- 2019-03-28 JP JP2019063313A patent/JP2020167181A/ja active Pending
-
2020
- 2020-03-11 WO PCT/JP2020/010547 patent/WO2020195834A1/ja active Application Filing
- 2020-03-11 CN CN202080023587.1A patent/CN113632218A/zh not_active Withdrawn
-
2021
- 2021-09-24 US US17/484,337 patent/US20220013428A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103715153A (zh) * | 2012-10-04 | 2014-04-09 | 台湾积体电路制造股份有限公司 | 热增强型堆叠封装(PoP) |
CN103811356A (zh) * | 2012-11-09 | 2014-05-21 | 辉达公司 | 将cpu/gpu/逻辑芯片嵌入堆叠式封装结构的衬底的方法 |
US20150115467A1 (en) * | 2013-10-30 | 2015-04-30 | Kyol PARK | Package-on-package device |
CN103560090A (zh) * | 2013-10-31 | 2014-02-05 | 中国科学院微电子研究所 | 一种用于PoP封装的散热结构的制作方法 |
CN104064551A (zh) * | 2014-06-05 | 2014-09-24 | 华为技术有限公司 | 一种芯片堆叠封装结构和电子设备 |
US20150357307A1 (en) * | 2014-06-05 | 2015-12-10 | Huawei Technologies Co., Ltd. | Chip stacked package structure and electronic device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113632227A (zh) * | 2019-03-28 | 2021-11-09 | 株式会社电装 | 电子装置 |
Also Published As
Publication number | Publication date |
---|---|
JP2020167181A (ja) | 2020-10-08 |
US20220013428A1 (en) | 2022-01-13 |
WO2020195834A1 (ja) | 2020-10-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9107290B1 (en) | Package structure and stacked package module with the same | |
US9287231B2 (en) | Package structure with direct bond copper substrate | |
CN106057747B (zh) | 包括散热器的半导体封装件及其制造方法 | |
JP4086068B2 (ja) | 半導体装置 | |
TWI654734B (zh) | 堆疊型半導體封裝 | |
US20070045804A1 (en) | Printed circuit board for thermal dissipation and electronic device using the same | |
US7872869B2 (en) | Electronic chip module | |
US10181458B2 (en) | Electronic package and fabrication method thereof | |
US20080179737A1 (en) | Semiconductor device | |
EP1351301A3 (en) | Semiconductor built-in millimeter-wave band module | |
US8619428B2 (en) | Electronic package structure | |
US11004837B2 (en) | Semiconductor device with improved heat dissipation | |
JP2006073651A (ja) | 半導体装置 | |
KR20060051982A (ko) | 반도체 장치 및 전자기기 | |
US7298028B2 (en) | Printed circuit board for thermal dissipation and electronic device using the same | |
US7723843B2 (en) | Multi-package module and electronic device using the same | |
WO2018216627A1 (ja) | 電子機器 | |
CN107708286B (zh) | 印刷电路板组件 | |
TW201709461A (zh) | 封裝基板 | |
JP2007095860A (ja) | 半導体装置 | |
JP2006120996A (ja) | 回路モジュール | |
JP5115200B2 (ja) | 電子素子、それを有するパッケージ及び電子装置 | |
CN113632218A (zh) | 电子装置 | |
US20220130585A1 (en) | Stacked electronic module and method to make the same | |
TWI284403B (en) | Package structure and stiffener ring |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WW01 | Invention patent application withdrawn after publication |
Application publication date: 20211109 |
|
WW01 | Invention patent application withdrawn after publication |