CN103811356A - 将cpu/gpu/逻辑芯片嵌入堆叠式封装结构的衬底的方法 - Google Patents

将cpu/gpu/逻辑芯片嵌入堆叠式封装结构的衬底的方法 Download PDF

Info

Publication number
CN103811356A
CN103811356A CN201310556944.2A CN201310556944A CN103811356A CN 103811356 A CN103811356 A CN 103811356A CN 201310556944 A CN201310556944 A CN 201310556944A CN 103811356 A CN103811356 A CN 103811356A
Authority
CN
China
Prior art keywords
substrate
power
insulating barrier
power die
heat distribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310556944.2A
Other languages
English (en)
Inventor
翟军
亚伊普拉卡什·基帕尔卡蒂
尚塔努·卡尔丘里
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nvidia Corp
Original Assignee
Nvidia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nvidia Corp filed Critical Nvidia Corp
Publication of CN103811356A publication Critical patent/CN103811356A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H05K7/2039—Modifications to facilitate cooling, ventilating, or heating characterised by the heat transfer by conduction from the heat generating element to a dissipating body
    • H05K7/20509—Multiple-component heat spreaders; Multi-component heat-conducting support plates; Multi-component non-closed heat-conducting structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

本发明公开了将CPU/GPU逻辑芯片嵌入堆叠式封装结构的衬底的方法。本发明的实施例提供了其中低功率芯片可以邻近高功率芯片进行定位而不遭受过度加热的影响的IC系统。在一个实施例中，IC系统可以包括第一衬底、嵌入第一衬底内的高功率芯片、布置在第一衬底的第一侧面上的第二衬底，第一衬底和第二衬底彼此电通信，布置在第二衬底上的低功率芯片。在各实施例中，热分布层毗邻高功率芯片进行定位，使得由高功率芯片所生成的热量可以有效地耗散到附接到第一衬底的底层印刷电路板中，从而防止从高功率芯片到低功率芯片的传热。因此，延长了低功率芯片的寿命。

Description

将CPU/GPU/逻辑芯片嵌入堆叠式封装结构的衬底的方法
技术领域
本发明的实施例总地涉及集成电路芯片封装，并且更具体地，涉及具有高功率芯片和低功率芯片的堆叠式封装（POP）封装系统。
背景技术
随着电子工业的发展，存在对于具有经改进的性能的较小电子设备的渐增的需求。为了达到电子部件的较小占用面积（footprint）和较高集成密度，已经开发所谓的“堆叠式封装（POP）”技术。POP是用来利用在其之间路由信号的接口来将多个基于引线框的半导体封装垂直叠加在彼此上的三维封装技术。
最小化封装的厚度已是POP技术的成功实现方案的挑战，因为在包含在封装中的芯片和其他器件的热管理和器件的性能之间一般存在权衡。特别地，通过将IC封装的存储器芯片、无源器件和其他低功率部件尽可能地靠近IC封装中的中央处理单元（CPU）和其他高功率器件来放置，加速了在IC封装中的器件之间的通信并且降低了封装寄生。然而，已知由较高功率芯片所生成的热不利地影响定位在附近的存储器芯片和其它器件。因此，当并入单个IC封装时将存储器芯片和无源器件直接叠加在CPU或其它高功率芯片上或在CPU或其它高功率芯片下面不具有热可行性，因为这类配置必然限制高功率芯片的功率或者影响存储器芯片的性能。
如前述所示，本领域存在对于具有较大集成电路密度以及封装大小方面的相对应的降低的封装系统的需要。存在对于防止芯片之间的传热的垂直叠加中的高功率芯片和低功率芯片安排的进一步的需要。
发明内容
本发明的实施例阐述了其中一个或多个低功率芯片可以邻近高功率芯片进行定位而不遭受过度加热的影响的IC系统。在一个实施例中，IC系统包括嵌入第一封装衬底的高功率芯片，以及布置在定位在第一封装衬底上方的第二封装衬底上的低功率芯片以形成叠加。因为第一封装衬底的部分使所嵌入的高功率芯片与低功率芯片热绝缘，所以低功率芯片可以邻近高功率芯片进行定位而不被过度加热。在某些实施例中，毗邻高功率芯片的侧面定位薄的热分布层以将高功率芯片的热量散布到第一封装衬底中。在经模塑（molded）的POP封装系统中，第一封装衬底中的热量通过焊料球传送到用作IC系统的散热器的底层印刷电路板（PCB）。
本发明的一个优势在于，在同一IC系统中存储器芯片或其他低功率芯片可以紧密邻近嵌入封装衬底中的高功率芯片进行定位而不被高功率芯片过度加热。这类紧密邻近有利地降低了封装系统的总厚度，因此实现了较薄并且较轻电子设备。通过使热分布层毗邻高功率芯片布置，由高功率芯片所生成的热量可以有效地耗散到印刷电路板（PCB）中，这进一步防止从高功率芯片到低功率芯片的传热。因此，延长了低功率芯片的寿命。
附图说明
因此，可以详细地理解本发明的上述特征，并且可以参考实施例得到对如上面所简要概括的本发明更具体的描述，其中一些实施例在附图中示出。然而，应当注意的是，附图仅示出了本发明的典型实施例，因此不应被认为是对其范围的限制，本发明可以具有其他等效的实施例。
图1是根据本发明的一个实施例的、集成电路（IC）系统的示意性剖视图。
图2是根据本发明的另一个实施例的、具有毗邻高功率芯片布置以增加来自高功率芯片的热传递（thermal transmittance）的热分布机构的IC系统的示意性剖视图。
图3是根据本发明的又一个实施例的、具有毗邻高功率芯片布置以增加来自高功率芯片的热传递的热分布机构的IC系统的示意性剖视图。
为了清晰起见，同样的参考数字在适用的地方已经用来指明各图之间公共的同样的元件。应预期到的是，一个实施例的特征可以包含在其它实施例中而无需进一步陈述。
具体实施方式
图1是根据本发明的一个实施例的、集成电路（IC）系统100的示意性剖视图。IC系统100总地包括多个IC芯片和/或其它分立的微电子部件，并且配置为将所述芯片和部件电地和机械地连接到印刷电路板190。IC系统可以是垂直组合，即一个或多个高功率芯片101和一个或多个低功率芯片102、105的叠加配置，其中一个或多个低功率芯片102、105与一个或多个高功率芯片101热绝缘。因此，源自高功率芯片101的热量不显著影响低功率芯片102、105。
在本公开中，高功率芯片101是高功率处理器，诸如中央处理单元（CPU）、图形处理单元（GPU）、应用处理器或其它逻辑设备、或能够在操作期间生成足以不利地影响放置在IC系统100中的无源器件或低功率芯片101的性能的热量的任何IC芯片。例如，高功率芯片典型地是在正常操作期间生成至少10W热量或更多的一个芯片。相反，低功率芯片是在操作期间不生成足以不利地影响邻近IC芯片或器件的性能的热量的一个芯片。例如，低功率芯片是在正常操作期间生成近似大约1W热量即不多于大约5W热量的任何IC芯片。低功率芯片可以是放置在IC系统100中的无源器件，例如存储器器件，诸如RAM或闪存、I/O芯片、或在正常操作中不生成超过5W的任何其它芯片。
在图1示出的实施例中，IC系统100包括嵌入第一封装衬底110中的高功率芯片101，以及安装在第二封装衬底140上的低功率芯片102。低功率芯片102可以通过电传导焊盘165安装在第二封装衬底140上。如果使用一组低功率芯片，那么顶低功率芯片105可以通过电传导焊盘167安装到底低功率芯片102上。第一封装衬底110大致平行于第二封装衬底140并且与第二封装衬底140相对。第二封装衬底140布置在第一封装衬底110的顶面143之上并且通过电连接142电连接到第一封装衬底110。在第二封装衬底140和第一封装衬底110之间的电连接142可以使用本领域公知的任何技术上可行的方法制成，诸如焊料凸块或焊料球。电连接142可以与形成在第一封装衬底110的顶面143上的相对应的结合焊盘145物理接触。应预期到的是，在第二封装衬底140和第一封装衬底110之间的电通信还可以通过其它结合技术进行，诸如倒装式结合（flip-chip bonding）技术或引脚网格阵列（PGA）技术。
安装在第二封装衬底140上的低功率芯片102可以密封在模塑材料148中来保护低功率芯片102。如果期望的话，可以通过利用密封材料保护电连接142来改进电连接142的可靠性。模塑或密封材料可以是树脂，诸如环氧树脂、丙烯酸树脂、硅树脂、聚氨酯树脂、聚酰胺树脂、聚酰亚胺树脂等。任何其它技术上可行的封装技术可以用来保护低功率芯片102或低功率芯片102到第一封装衬底110的电连接142。尽管未示出，但是应预期到的是，模塑材料148的、背对第二封装衬底140的顶面150可以附接到散热器或其它冷却机构来增强IC系统100的热传递。
在叠加配置中，低功率芯片102安装在高功率芯片101对面，并且经由形成在第一封装衬底110中的导电过孔123和导电线路114电连接到高功率芯片101和PCB 190。在高功率芯片101和第一封装衬底110之间的电连接可以使用本领域公知的任何技术上可行的方法制成。应注意的是，导电线路114和导电过孔123以及其配置是可以用来将高功率芯片101电连接到外部部件的示例性方法。取代导电线路114和导电过孔123的使用或除了它之外，可以使用具有不同布线安排/配置的任何公知的电连接。
在图1示出的实施例中，高功率芯片101包括硅通孔（TSV）125，其穿过高功率芯片101并且用作贯穿高功率芯片101的电力、接地和信号互连。TSV125配置为促进在高功率芯片101和第一封装衬底110之间的快速电连接，这转而促进在高功率芯片101、低功率芯片102和PCB 190之间的电连接。与其中诸如结合焊盘等等的电连接制造在高功率芯片的单个侧面上并且厚的金属线用来将结合焊盘互连到外部电路的线结合（wire-bonding）技术相反，TSV 125可以为高功率芯片102的两侧的部件提供电连接。利用TSV 125，高功率芯片101可以嵌入如图1示出的IC系统100中并且使高功率芯片101既能电连接到低功率芯片102（通过导电线路114、导电过孔123以及电连接142）又能电连接到PCB 190（通过多个封装引线180）。因此，获得了在高功率芯片101和低功率芯片102之间的非常短的路径长度的互连。
电路之间的互连的较短的布线导致较快信号传播以及噪声、串扰和其它寄生方面的降低。在IC封装领域，寄生由芯片到外部部件的互连引起，所述外部部件例如IC结合焊盘、结合线、封装引线、导电线路等等。通过在如图1示出的重叠配置中叠加低功率芯片102和高功率芯片101，在低功率芯片和高功率芯片101之间的互连的长度被最小化，并且这类寄生被大大降低。而且，与其中高功率芯片101和低功率芯片102并排定位在封装衬底的同一侧的IC封装相比，IC系统100的总“占用面积”被最小化。此外，与高功率芯片安装在第一封装衬底110的顶面143上的现存的POP封装系统相比较，将高功率芯片101嵌入第一封装衬底110中降低IC系统100的厚度“H1”至少大约25μm或更多。最重要的是，因为高功率芯片101更靠近PCB 190（其用作IC系统100的散热器）并且第一封装衬底110的部分可以充当热绝缘层，所以低功率芯片102与所嵌入的高功率芯片101热绝缘而不受由高功率芯片101生成的热量的不利影响。
第一封装衬底110给IC系统100提供结构刚性和用于在高功率芯片101、低功率芯片102和PCB 190之间路由输入和输出信号以及电力的电接口。第一封装衬底110可以是包括累积在核心层119的顶面152和底面154上的层压板或绝缘层的叠加的层压衬底，高功率芯片101被嵌入所述核心层119中。导电线路114和导电过孔123形成在绝缘层117之间以在高功率芯片101、低功率芯片102和PCB 190之间提供电通信。通过使用湿法蚀刻工艺或干法蚀刻工艺在核心层119中形成腔或凹入的开口，高功率芯片101可以嵌入第一封装衬底110中。腔或凹入的开口经调整大小用于容纳高功率芯片101。在高功率芯片101形成在核心层119中之后，绝缘层117和诸如导电线路114和导电过孔123的电连接随后形成在高功率芯片101周围。尽管本文未讨论，但技术人员应该理解，导电线路114可以通过任何适合的工艺来形成，诸如蚀刻结合到第一封装衬底110的一个或多个层压板的铜箔。导电过孔123可以是通过电镀工艺或任何其它适合的技术所形成的填充铜的过孔。
高功率芯片101可以放置在第一封装衬底110中的预定深度处。在一些实施例中，将高功率芯片101置于更靠近PCB 190以提升到PCB 190中的热耗散的高度可能是有利的。还应预期到的是，高功率芯片101可以不必完全嵌入第一封装衬底110中。高功率芯片101的顶面152可以与第一封装衬底110的顶面143齐平、稍低于或稍高于第一封装衬底110的顶面143。高功率芯片101的高度可以取决于工艺方案或应用而变化。在一个实施例中，高功率芯片101可以具有大约100μm到大约200μm的厚度“T1”，例如大约150μm。第一封装衬底110可以具有大约300μm到大约500μm的厚度“T2”，诸如大约400μm。取决于应用来预期较厚或较薄外形。
图2是根据本发明的另一个实施例的、具有毗邻高功率芯片布置以增加来自高功率芯片的热传递的热分布机构的IC系统200的示意性剖视图。应注意的是，诸如图1示出的导电线路114和导电过孔123的电连接已被简化并标示为170，或仅为了便于理解而省略。除热分布层202嵌入第一封装衬底110中之外，IC系统200与IC系统100在配置和操作方面大致类似。在如示出的实施例中，热分布层202形成为在第一封装衬底110中的层209并且经定位与高功率芯片101的顶面156物理接触以提升从高功率芯片101到第一封装衬底110的快速热耗散。可替代地，热分布层202可以与高功率芯片101分开一段距离。热分布层202可以是具有比第一封装衬底110更高的导热性的金属片的形式。在一个实施例中，热分布层202包括铜或另一电传导材料，诸如铝、金、银或两个或更多个元素的合金。可以使用由导电树脂或导电膏制成的导电粘合层（未示出）来将热分布层202结合到高功率芯片101的顶面156以保证良好的导热和到高功率芯片101的牢固附接。
热分布层202配置为将由高功率芯片101所生成的热能传导远离低功率芯片102，从而降低在IC系统的操作期间过度加热低功率芯片102的风险。热分布层102沿第一封装衬底110的纵向将热分布到第一封装衬底202并且贯穿第一封装衬底202。热随后通过封装引线180耗散到PCB 190。由于用于热耗散的、第一封装衬底110内的热分布层202的经增加的表面积，所以由高功率芯片101所生成的热能可以更高效地耗散到PCB 190中。
热分布层202可以在平行于第一封装衬底110的顶面156的平面中横向延伸。热分布层202可以在第一封装衬底110的制作期间使用电镀工艺、物理气相沉积（PVD）或任何其它适合的沉积工艺来形成。热分布层202可以具有稍短于第一封装衬底110的长度、但长于高功率芯片101的长度的长度“L1”。在一个示例中，热分布层202的长度“L1”在大约20μm和大约150μm之间，例如大约80μm。尽管仅示出一个热分布层202，但是应预期到的是，两个或更多个热分布层可以以任何适合的安排使用在第一封装衬底110中来增强来自高功率芯片101的热排除。例如，两个或更多个热分布层（未示出）可以附接到高功率芯片101的底面158，热分布层202附接或不附接到高功率芯片101的顶面156。任何附加的热分布层（如果使用的话）可以沿第一封装衬底110的纵向穿过第一封装衬底110横向延伸或以取决于应用的任何其它安排延伸。在一些实施例中，热分布层202和/或任何附加的热分布层（如果使用的话）可以由两层或更多层金属箔形成，并且其厚度可以在给定IC系统200的占用面积和高功率芯片101和低功率芯片102的热生成的情况下由本领域技术人员容易地确定。尽管未示出，但是应预期到的是，热分布层202可以包括允许互连以在低功率芯片102和高功率芯片101之间运行而不接触热分布层202的通孔。
图3是根据本发明的又一个实施例的、具有毗邻高功率芯片布置以增加来自高功率芯片的热传递的热分布机构的IC系统300的示意性剖视图。除高功率芯片101密封在夹在顶绝缘层302和底绝缘层304之间的模塑材料305中之外，IC系统300与IC系统100在配置和操作方面类似。
高功率芯片101嵌入第一支持衬底310内。第一支持衬底310包括顶绝缘层302、底绝缘层304以及夹在顶绝缘层302和底绝缘层304之间的模塑材料305。模塑材料305密封高功率芯片101。特别地，模塑材料305大致填充由顶绝缘层302、底绝缘层304以及高功率芯片101的外围310所限定的空间306、308，导致高功率芯片101被模塑材料305围绕。尽管未示出，顶绝缘层和底绝缘层302、304可以是包括累积在模塑材料305的顶面352和底面354上的层压板或绝缘层（诸如图1示出的绝缘层117）的叠加的层压结构，高功率芯片101封装在所述模塑材料305中。顶绝缘层和底绝缘层302、304和（密封高功率芯片101的）模塑材料305因此形成具有类似于图1示出的第一封装衬底110的功能性的第一支持衬底310。
模塑材料305的底面354可以与底绝缘层304的顶面大致共面，而模塑材料305的顶面352可以与顶绝缘层302的底面大致共面。在这种情况下，高功率芯片101可以与顶绝缘层302和/或底绝缘层304分开期望的距离。可替代地，顶绝缘层302可以是覆盖模塑材料305的顶面352和嵌入模塑材料305内的高功率芯片101的顶面的连续层，而底绝缘层304可以是覆盖模塑材料305的底面354和嵌入模塑材料305内的高功率芯片101的底面的连续层。无论哪种情况，模塑材料305都可以包括流动良好的本领域公知的任何适合的模塑材料并且因此最小化任何间隙的形成。在一个示例中，模塑材料是模塑化合物，诸如环氧树脂、丙烯酸树脂、硅树脂、聚氨酯树脂、聚酰胺树脂、聚酰亚胺树脂等。
顶绝缘层302可以包括嵌入其中以促进在低功率芯片102、高功率芯片101和PCB 190之间的电信号的路由的顶重新分布特征。在一个实施例中，顶重新分布特征是在平行于模塑材料305的顶面352的平面中横向延伸期望的长度的电传导线312a。在另一个实施例中，顶重新分布特征可以包括安排在顶绝缘层302中并且通过导电过孔362彼此以平行关系电连接的两个或更多个电传导线（共面或非共面线）。重新分布特征的使用使用于封装系统300的第一支持衬底310中的布线层的数目能够降低。图3示出了其中共面的电传导线312a、312b分别电连接到底层的、共面的电传导线312d、312c的一个示例性安排。顶重新分布特征还可以对将由高功率芯片101所生成的热量散布到顶绝缘层302起作用。应预期到的是，第一重新分布特征的安排和数目可以取决于外部连接、顶绝缘层302的尺寸和应用而变化。在各实施例中，顶重新分布特征包括铜或另一导电材料，诸如铝、金、银或两个或更多个元素的合金。
在低功率芯片102、高功率芯片101和PCB 190之间的电连接可以通过本领域公知的任何技术上可行的芯片封装电连接进行。在一个实施例中，一个或多个顶重新分布特征312a可以分别通过导电过孔344和导电过孔346来分别连接到焊料凸块342和布置在高功率芯片101的一个侧面上的一个或多个结合焊盘330。一个或多个结合焊盘330凭借穿过高功率芯片101形成的硅通孔344与布置在高功率芯片101的另一个侧面上的一个或多个结合焊盘368电通信。类似地，一个或多个结合焊盘369通过导电线350和BGA 358与PCB 190电通信。尽管本文未讨论，但是应预期到的是，同样的电连接可以用来在低功率芯片102、高功率芯片101和PCB 190之间传送电力、接地和/或I/O信号。
类似地，底绝缘层304可以包括嵌入其中以促进在低功率芯片102、高功率芯片101和PCB 190之间的电信号的路由的底重新分布特征，从而使用于封装系统300的第一支持衬底310中的布线层的数目能够降低。底重新分布特征可以是在平行于模塑材料305的底面354的平面中横向延伸期望的长度的电传导线314a。可替代地，底重新分布特征可以包括安排在底绝缘层304中并且通过导电过孔364彼此以平行关系电连接的两个或更多个电传导线（共面或非共面线），从而使用于封装系统300的第一支持衬底310中的布线层的数目能够降低。底重新分布特征还可以对将由高功率芯片101所生成的热量散布到底绝缘层304起作用。尽管未示出，但是应预期到的是，顶绝缘层和底绝缘层302、304可以包括一个或多个电线路、结合焊盘连接器、过孔、线或将信号或电力从电路中的一个点物理转移到另一个点的本领域中的任何公知结构、构造、安排。顶重新分布特征和底重新分布特征还可以是将增加从高功率芯片101到第一支持衬底310中的热传递的任何其它安排/配置的方式。
利用顶绝缘层和底绝缘层302、304和嵌入其中的相关联的重新分布特征，高功率芯片101可以与安装在第二支持衬底340（与图1的第二封装衬底140在结构和操作方面相同）上的低功率芯片102和PCB 190电通信。为了促进从高功率芯片101到第一支持衬底310并且因此到PCB 190的热耗散，一系列热分布特征可以形成在高功率芯片101的两侧的模塑材料305中。在图3示出的实施例中，示出了两个热分布特征316a、316b。然而，预期更少或更多热分布特征。热分布特征316a、316b可以垂直穿过模塑材料305以电地并热地连接顶绝缘层302和底绝缘层304。特别地，热分布特征316a、316b分别与顶重新分布特征例如电传导线312d、312c和底重新分布特征例如电传导线314a、314b物理接触。因此，由顶绝缘层302所吸收的热量可以通过该系列热分布特征316传送到底绝缘层304，并且随后通过封装引线或诸如C4凸块366的电传导机构来传送到PCB 190。如上文所讨论的，PCB 190用作IC系统300的散热器。由于用于热耗散的、第一支持衬底310中的该系列热分布特征316a、316b的经增加的表面积，所以由高功率芯片101所生成的热能可以更高效地耗散到PCB 190中。
该系列热分布特征可以是通过激光打孔或任何其它适合的技术所形成的导热过孔。导热过孔使用诸如电镀工艺的任何适合的技术填充传热介质。在一个示例中，导热过孔填充诸如铜的金属填充物。然而，可以使用具有比第一支持衬底310更高的导热性的任何材料。
利用热分布特征的发明配置，低功率芯片102不遭受过度加热的影响，因为高功率芯片101嵌入封装衬底中并且由高功率芯片101所生成的热量可以通过如图2示出的热分布层202或如图3示出的该系列热分布特征316、318有效地耗散到PCB 190中。
总而言之，本发明的实施例阐述了其中一个或多个低功率芯片可以邻近高功率芯片进行定位而不遭受过度加热的影响的IC系统。通过使热分布特征毗邻嵌入封装衬底中的一个或多个高功率芯片进行布置，由高功率芯片所生成的热量可以有效地耗散到封装衬底中并且随后到用作IC系统的散热器的PCB，从而防止从高功率芯片到低功率芯片的传热。因此，延长了存储器芯片的寿命。
尽管前述针对本发明的实施例，但是可以设计本发明的其它和进一步的实施例而不脱离本发明的基本范围，并且本发明的范围由下面的权利要求来确定。

Claims (10)

1.一种集成电路系统，包括：
第一衬底；
嵌入所述第一衬底内的高功率芯片；
毗邻所述第一衬底的第一侧面布置的第二衬底，其中所述第一衬底和所述第二衬底彼此电通信；以及
布置在所述第二衬底上的低功率芯片。
2.根据权利要求1所述的系统，进一步包括：
嵌入所述第一衬底内的热分布层，其中所述热分布层沿所述高功率芯片的纵向横向地延伸。
3.根据权利要求2所述的系统，其中所述热分布层具有比所述高功率芯片的长度更长的长度。
4.根据权利要求2所述的系统，其中所述热分布层毗邻所述高功率芯片进行定位。
5.根据权利要求2所述的系统，其中所述热分布层附接到所述高功率芯片的至少第一侧面。
6.根据权利要求2所述的系统，其中所述热分布层由包括铜、铝、金、银或两个或更多个电传导元素的合金的电传导材料制成。
7.一种集成电路系统，包括：
第一衬底，包括：
顶绝缘层，其布置在所述第一衬底的顶面上；
底绝缘层，其布置在所述第一衬底的底面上，所述顶绝缘层与所述底绝缘层平行；
高功率芯片，其布置在所述顶绝缘层和所述底绝缘层之间并且与所述顶绝缘层和所述底绝缘层电通信；
模塑材料，其大致填充围绕所述高功率芯片的空间，所述模塑材料布置在所述顶绝缘层和所述底绝缘层之间；
第二衬底，其毗邻所述第一衬底的第一侧面布置，所述第一衬底和所述第二衬底彼此电通信；以及
低功率芯片，其布置在所述第二衬底上。
8.根据权利要求7所述的系统，进一步包括：
顶重新分布特征，其嵌入所述顶绝缘层中；以及
底重新分布特征，其嵌入所述底绝缘层中，
其中所述顶重新分布特征和所述底重新分布特征配置为促进在所述低功率芯片和所述高功率芯片之间的电信号的路由。
9.根据权利要求7所述的系统，其中所述模塑材料进一步包括：
通过所述模塑材料形成的一个或多个热分布特征，其中所述热分布特征分别与所述顶重新分布特征和所述底重新分布特征物理并热接触。
10.根据权利要求9所述的系统，其中所述一个或多个热分布特征由包括铜、铝、金、银或两个或更多个电传导元素的合金的电传导材料制成。
CN201310556944.2A 2012-11-09 2013-11-11 将cpu/gpu/逻辑芯片嵌入堆叠式封装结构的衬底的方法 Pending CN103811356A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/673,280 US20140133105A1 (en) 2012-11-09 2012-11-09 Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structure
US13/673,280 2012-11-09

Publications (1)

Publication Number Publication Date
CN103811356A true CN103811356A (zh) 2014-05-21

Family

ID=50555915

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310556944.2A Pending CN103811356A (zh) 2012-11-09 2013-11-11 将cpu/gpu/逻辑芯片嵌入堆叠式封装结构的衬底的方法

Country Status (4)

Country Link
US (1) US20140133105A1 (zh)
CN (1) CN103811356A (zh)
DE (1) DE102013018599B4 (zh)
TW (1) TW201428936A (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104409437A (zh) * 2014-12-04 2015-03-11 江苏长电科技股份有限公司 双面bump芯片包封后重布线的封装结构及其制作方法
CN106663680A (zh) * 2014-06-30 2017-05-10 艾利迪公司 包括发光二极管和控制电路的光电子装置
CN112040753A (zh) * 2020-10-13 2020-12-04 中国石油大学(华东) 一种5g通讯设备散热装置
CN112185911A (zh) * 2019-07-03 2021-01-05 美光科技公司 包含垂直集成电路的半导体组合件及其制造方法
CN113632218A (zh) * 2019-03-28 2021-11-09 株式会社电装 电子装置

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101419601B1 (ko) * 2012-11-20 2014-07-16 앰코 테크놀로지 코리아 주식회사 Emc 웨이퍼 서포트 시스템을 이용한 반도체 디바이스 및 이의 제조방법
KR102107038B1 (ko) * 2012-12-11 2020-05-07 삼성전기주식회사 칩 내장형 인쇄회로기판과 그를 이용한 반도체 패키지 및 칩 내장형 인쇄회로기판의 제조방법
US20150206855A1 (en) * 2014-01-22 2015-07-23 Mediatek Inc. Semiconductor package
US10056352B2 (en) 2014-07-11 2018-08-21 Intel IP Corporation High density chip-to-chip connection
KR102186149B1 (ko) * 2015-03-11 2020-12-03 삼성전기주식회사 인쇄회로기판 및 그의 제조 방법
KR102253472B1 (ko) * 2015-03-13 2021-05-18 삼성전기주식회사 인쇄회로기판 및 그 제조방법
JP6501638B2 (ja) * 2015-06-11 2019-04-17 オムロンオートモーティブエレクトロニクス株式会社 電子装置
JP2017038017A (ja) * 2015-08-13 2017-02-16 富士通株式会社 ノイズ低減基板及び電子機器
US9781863B1 (en) 2015-09-04 2017-10-03 Microsemi Solutions (U.S.), Inc. Electronic module with cooling system for package-on-package devices
US20170092594A1 (en) * 2015-09-25 2017-03-30 Qualcomm Incorporated Low profile package with passive device
KR102556052B1 (ko) 2015-12-23 2023-07-14 삼성전자주식회사 시스템 모듈과 이를 포함하는 모바일 컴퓨팅 장치
US9991219B2 (en) * 2016-06-23 2018-06-05 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package module
TWI620356B (zh) * 2016-10-07 2018-04-01 欣興電子股份有限公司 封裝結構及其製作方法
US10163799B2 (en) * 2016-11-07 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of manufacturing the same
KR20190047444A (ko) * 2017-10-27 2019-05-08 에스케이하이닉스 주식회사 단열벽을 포함하는 반도체 패키지
KR20240005974A (ko) 2017-12-29 2024-01-12 인텔 코포레이션 마이크로전자 어셈블리
FR3082354B1 (fr) 2018-06-08 2020-07-17 Commissariat A L'energie Atomique Et Aux Energies Alternatives Puce photonique traversee par un via
KR102582422B1 (ko) * 2018-06-29 2023-09-25 삼성전자주식회사 재배선층을 갖는 반도체 패키지
CN109300882A (zh) * 2018-09-20 2019-02-01 蔡亲佳 堆叠嵌入式封装结构及其制作方法
EP3637461A1 (en) 2018-10-11 2020-04-15 ABB Schweiz AG Power electronic module
CN113567929A (zh) * 2021-07-12 2021-10-29 南京国博电子股份有限公司 一种3d异构集成多功能收发芯片

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6159767A (en) * 1996-05-20 2000-12-12 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
WO2008067258A2 (en) * 2006-11-29 2008-06-05 Texas Instruments Incorporated Semiconductor chip embedded in an insulator and having two-way heat extraction
CN102403286A (zh) * 2010-09-13 2012-04-04 意法半导体(格勒诺布尔2)公司 配备有热耗散装置的半导体部件和器件

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3147087B2 (ja) * 1998-06-17 2001-03-19 日本電気株式会社 積層型半導体装置放熱構造
US6208512B1 (en) * 1999-05-14 2001-03-27 International Business Machines Corporation Contactless hermetic pump
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US7619901B2 (en) * 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
US7803714B2 (en) * 2008-03-31 2010-09-28 Freescale Semiconductor, Inc. Semiconductor through silicon vias of variable size and method of formation
JP2010114434A (ja) * 2008-10-08 2010-05-20 Ngk Spark Plug Co Ltd 部品内蔵配線基板及びその製造方法
US7928534B2 (en) * 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US8276268B2 (en) * 2008-11-03 2012-10-02 General Electric Company System and method of forming a patterned conformal structure
US20100133682A1 (en) * 2008-12-02 2010-06-03 Infineon Technologies Ag Semiconductor device
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
US8314483B2 (en) * 2009-01-26 2012-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. On-chip heat spreader
US8093711B2 (en) * 2009-02-02 2012-01-10 Infineon Technologies Ag Semiconductor device
WO2010114687A1 (en) * 2009-03-30 2010-10-07 Megica Corporation Integrated circuit chip using top post-passivation technology and bottom structure technology
US9230898B2 (en) * 2009-08-17 2016-01-05 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
JP5425584B2 (ja) * 2009-10-15 2014-02-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8508954B2 (en) * 2009-12-17 2013-08-13 Samsung Electronics Co., Ltd. Systems employing a stacked semiconductor package
US8996836B2 (en) * 2009-12-18 2015-03-31 Micron Technology, Inc. Stacked device detection and identification
US8492911B2 (en) * 2010-07-20 2013-07-23 Lsi Corporation Stacked interconnect heat sink
TWI419270B (zh) * 2011-03-24 2013-12-11 Chipmos Technologies Inc 封裝堆疊結構
US20120267782A1 (en) * 2011-04-25 2012-10-25 Yung-Hsiang Chen Package-on-package semiconductor device
KR20130007124A (ko) * 2011-06-29 2013-01-18 삼성전자주식회사 유기 보호막을 갖는 조인트 구조
US9728481B2 (en) * 2011-09-07 2017-08-08 Nvidia Corporation System with a high power chip and a low power chip having low interconnect parasitics
CN103814627A (zh) * 2011-09-21 2014-05-21 莫塞德技术公司 用于将嵌入的芯片连接到印刷电路板中的方法和设备
US9087830B2 (en) * 2012-03-22 2015-07-21 Nvidia Corporation System, method, and computer program product for affixing a post to a substrate pad
US20130256873A1 (en) * 2012-04-03 2013-10-03 Nvidia Corporation System, method, and computer program product for preparing a substrate post
US8618651B1 (en) * 2012-11-01 2013-12-31 Nvidia Corporation Buried TSVs used for decaps
US10096534B2 (en) * 2012-11-09 2018-10-09 Nvidia Corporation Thermal performance of logic chip in a package-on-package structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6159767A (en) * 1996-05-20 2000-12-12 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
WO2008067258A2 (en) * 2006-11-29 2008-06-05 Texas Instruments Incorporated Semiconductor chip embedded in an insulator and having two-way heat extraction
CN102403286A (zh) * 2010-09-13 2012-04-04 意法半导体(格勒诺布尔2)公司 配备有热耗散装置的半导体部件和器件

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106663680A (zh) * 2014-06-30 2017-05-10 艾利迪公司 包括发光二极管和控制电路的光电子装置
US10304812B2 (en) 2014-06-30 2019-05-28 Aledia Optoelectronic device including light-emitting diodes and a control circuit
CN106663680B (zh) * 2014-06-30 2019-05-31 艾利迪公司 包括发光二极管和控制电路的光电子装置
CN110265389A (zh) * 2014-06-30 2019-09-20 艾利迪公司 包括发光二极管和控制电路的光电子装置
CN110265389B (zh) * 2014-06-30 2023-06-06 艾利迪公司 包括发光二极管和控制电路的光电子装置
CN104409437A (zh) * 2014-12-04 2015-03-11 江苏长电科技股份有限公司 双面bump芯片包封后重布线的封装结构及其制作方法
CN104409437B (zh) * 2014-12-04 2017-09-22 江苏长电科技股份有限公司 双面bump芯片包封后重布线的封装结构及其制作方法
CN113632218A (zh) * 2019-03-28 2021-11-09 株式会社电装 电子装置
CN112185911A (zh) * 2019-07-03 2021-01-05 美光科技公司 包含垂直集成电路的半导体组合件及其制造方法
US11664291B2 (en) 2019-07-03 2023-05-30 Micron Technology, Inc. Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same
CN112040753A (zh) * 2020-10-13 2020-12-04 中国石油大学(华东) 一种5g通讯设备散热装置

Also Published As

Publication number Publication date
DE102013018599B4 (de) 2017-12-14
TW201428936A (zh) 2014-07-16
DE102013018599A1 (de) 2014-05-15
US20140133105A1 (en) 2014-05-15

Similar Documents

Publication Publication Date Title
CN103811356A (zh) 将cpu/gpu/逻辑芯片嵌入堆叠式封装结构的衬底的方法
KR100885924B1 (ko) 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법
CN103378017B (zh) 高密度3d封装
US7656015B2 (en) Packaging substrate having heat-dissipating structure
TWI467726B (zh) 堆疊封裝結構
JP3854054B2 (ja) 半導体装置
TWI515844B (zh) 具一高功率晶片和一低功率晶片的低互連寄生現象的系統
KR100586698B1 (ko) 수직 실장된 반도체 칩 패키지를 갖는 반도체 모듈
JP4742079B2 (ja) ウェハレベルのシステムインパッケージ及びその製造方法
CN107452707A (zh) 含热、电性能改善的再分布结构的芯片载体及半导体器件
JP7028553B2 (ja) 半導体装置及びその製造方法
US20090184412A1 (en) Resin-seal type semiconductor device
CN104051395A (zh) 芯片堆叠封装及其方法
US10096534B2 (en) Thermal performance of logic chip in a package-on-package structure
JP2007535156A (ja) 埋込み構成要素からの熱伝導
KR101046252B1 (ko) Ｔｓｖ를 이용한 적층 칩 패키지
KR101056750B1 (ko) Ｔｓｖ를 이용한 적층 칩 패키지
WO2012116157A2 (en) Chip module embedded in pcb substrate
US8031484B2 (en) IC packages with internal heat dissipation structures
US9006904B2 (en) Dual side package on package
KR102041635B1 (ko) 반도체 패키지
KR20220001679A (ko) 상하 전도층을 갖는 구리 비아 스페이서를 구비한 양면냉각 전력 패키지
KR20080104748A (ko) 반도체 패키지 및 그 제조방법
KR20210024362A (ko) 반도체 패키지
US11749583B2 (en) Electronic package and method for manufacturing the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20140521