TWI419270B - 封裝堆疊結構 - Google Patents

封裝堆疊結構 Download PDF

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TWI419270B
TWI419270B TW100110160A TW100110160A TWI419270B TW I419270 B TWI419270 B TW I419270B TW 100110160 A TW100110160 A TW 100110160A TW 100110160 A TW100110160 A TW 100110160A TW I419270 B TWI419270 B TW I419270B
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Taiwan
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carrier
package
disposed
electrically connected
heat dissipation
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TW100110160A
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English (en)
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TW201240028A (en
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Shih Wen Chou
Yu Tang Pan
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Chipmos Technologies Inc
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Priority to TW100110160A priority Critical patent/TWI419270B/zh
Priority to CN201110172866.7A priority patent/CN102693965B/zh
Priority to US13/205,649 priority patent/US20120241935A1/en
Publication of TW201240028A publication Critical patent/TW201240028A/zh
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Publication of TWI419270B publication Critical patent/TWI419270B/zh

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Description

封裝堆疊結構
本發明是有關於一種封裝堆疊結構,且特別是有關於一種具有較佳散熱及重配置線路的封裝堆疊結構(Package On Package structure)。
隨著科技日新月異,積體電路(integrated circuits,IC)元件已廣泛地應用於我們日常生活當中。一般而言,積體電路的生產主要分為三個階段:矽晶圓的製造、積體電路的製作及積體電路的封裝。在目前的封裝結構中,堆疊式封裝(package on package,POP)為一種常見的封裝型態。
如圖4所示,習知的堆疊式封裝通常是由堆疊的晶片封裝結構40、42所構成。晶片封裝結構40包括載板400、晶片402、隔離層(spacer)404、重配置線路板(re-layout board)406與封裝膠體414。晶片402藉由黏著層408固定至載板400上。隔離層404與重配置線路板406依序配置於晶片402上。晶片402藉由導線410與載板400電性連接。重配置線路板406藉由導線412與載板400電性連接。封裝膠體414包覆部分載板400、晶片402、隔離層404、導線410與412以及部分重配置線路板406。晶片封裝結構42包括載板416、晶片418與封裝膠體420。晶片418藉由黏著層422固定至載板416上,且藉由導線424與載板416電性連接。封裝膠體420包覆部分載板416、晶片418與導線424。此外,晶片封裝結構42堆疊於晶片封裝結構40上,且藉由凸塊426與晶片封裝結構40的重配置線路板406電性連接。如此一來,晶片封裝結構42可經由凸塊426、重配置線路板406與導線412而電性連接至載板400。另外,晶片封裝結構40還包括凸塊428,使得封裝堆疊結構40可藉由凸塊428電性連接至其他外部元件。
然而,在上述的堆疊式封裝結構中,由於重配置線路板406配置於晶片402與隔離層404上方,使得導線412必須具有較長的長度,且因此容易造成導線412坍塌(collapse)。此外,上述的堆疊式封裝結構亦容易產生散熱不佳的問題。
此外,由於重配置線路板406是藉由隔離層404設置於晶片402上,以供水平承載重配置線路板406及晶片封裝結構42,整體之構件不僅較為繁多,且於充填封裝膠體420時,由於膠體流動而易使重配置線路板406傾斜不平,進而影響產品之可靠度。
有鑑於此,本發明的目的就是在提供一種封裝堆疊結構,其同時具有較佳的散熱及重配置缐路。
本發明提出一種封裝堆疊結構,其包括第一封裝結構、多個凸塊以及第二封裝結構。第一封裝結構包括第一載板、第一晶片、散熱板以及第一封裝膠體。第一晶片配置於第一載板上,且藉由多條第一導線與第一載板電性連接。散熱板包括支撐部分與連接部分。散熱板的表面上具有線路層。支撐部分位於第一晶片上方,而連接部分分別位於支撐部分的相對二側。散熱板覆蓋第一晶片與第一導線,且藉由連接部分上的線路層電性連接至第一載板。第一封裝膠體包覆第一晶片、第一導線、部分散熱板與部分第一載板。凸塊配置於支撐部分上。第二封裝結構配置於第一封裝結構上,並藉由凸塊與第一封裝結構電性連接。
依照本發明實施例所述之封裝堆疊結構,上述之散熱板例如具有上表面以及與上表面相對的下表面,其中上表面上具有線路層,而凸塊與線路層電性連接,且第一封裝結構還可以包括多條第二導線,而位於連接部分上的線路層藉由第二導線與第一載板電性連接。
依照本發明實施例所述之封裝堆疊結構,還可以包括黏著層,其配置於連接部分與第一載板之間。
依照本發明實施例所述之晶片封裝結構,上述之黏著層例如為導電材料,而此導電材料選自於銲鍚、銀膠與異方性導電膠之一。
依照本發明實施例所述之封裝堆疊結構,上述之黏著層例如為絕緣材料,而此絕緣材料選自於環氧樹脂、兩階段性膠材(B-Stage)、非導電膠(non-conductive paste,NCP)與非導電膜(non-conductive film,NCF)之一。
依照本發明實施例所述之封裝堆疊結構,上述之散熱板例如由金屬核心層與絕緣層構成。絕緣層配置於金屬核心層的表面上,且線路層配置於絕緣層上。
依照本發明實施例所述之封裝堆疊結構,上述之散熱板例如具有上表面以及與上表面相對的下表面,其中下表面上具有線路層,且散熱板中具有多個導通孔,而凸塊藉由導通孔與線路層電性連接,且散熱板藉由位於連接部分上的線路層與第一載板電性連接。
依照本發明實施例所述之封裝堆疊結構,上述之導通孔的外周緣與散熱板之間例如配置有絕緣層。
依照本發明實施例所述之封裝堆疊結構,上述之第二封裝結構包括第二載板、第二晶片以及第二封裝膠體。第二載板藉由凸塊與第一封裝結構電性連接。第二晶片配置於第二載板上,且藉由多條第二導線與第二載板電性連接。第二封裝膠體包覆第二晶片、第二導線與部分第二載板。
依照本發明實施例所述之封裝堆疊結構,上述之第一載板例如具有正面、背面以及穿孔。第一晶片配置於第一載板的正面,且第一導線藉由穿孔伸出並電性連接於第一載板的背面。
在本發明中,由於散熱板具有線路層並經由線路層與載板電性連接,且散熱板與晶片電性分離,因此散熱板可以取代先前技術中的隔離層與重配置線路板而同時具有穩固承載位於上方的封裝結構以及散熱的功效,使得本發明的封裝堆疊結構能夠具有較佳的散熱效果。
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式,作詳細說明如下。
圖1為依照本發明的第一實施例所繪示的封裝堆疊結構之剖面示意圖。請參照圖1,封裝堆疊結構10包括第一封裝結構100、第二封裝結構200以及凸塊300。第一封裝結構100包括載板102、晶片104、散熱板106以及封裝膠體108。第二封裝結構200包括載板202、晶片204以及封裝膠體206。
在第一封裝結構100中,晶片104配置於載板102的正面102a上。載板102例如為線路板。晶片104具有接墊104a,載板102具有接墊103a,且藉由導線110使晶片104的接墊104a與載板102的接墊103a電性連接。在本實施例中,晶片104與載板102之間配置有黏著層112,以將晶片104固定於載板102上。此外,載板102的背面102b具有接墊103b。多個凸塊114與接墊103b電性連接,使得封裝堆疊結構10可藉由凸塊114電性連接至其他外部元件。
散熱板106包括支撐部分107a與連接部分107b。支撐部分107a位於晶片104上方,而連接部分107b分別位於支撐部分107a的相對二側,且晶片104與導線110位於這些連接部分107b之間,使得散熱板106覆蓋晶片104與導線110,且與二者電性隔離。在本實施例中,散熱板106具有上表面106a以及與上表面106a相對的下表面106b。此外,散熱板106具有位於上表面106a上的線路層116,且位於連接部分107b上的線路層116藉由導線118與載板102的接墊103a電性連接。在一實施例中,散熱板106例如由金屬核心層與配置於金屬核心層的表面上的絕緣層構成,而線路層116配置於絕緣層上。
此外,黏著層120配置於連接部分107b與載板102之間。在一實施例中,黏著層120為絕緣材料,其可選自於環氧樹脂、兩階段性膠材、非導電膠與非導電膜之一。在另一實施例中,黏著層120也可以是導電材料,其可選自於銲鍚、銀膠與異方性導電膠之一。
封裝膠體108包覆晶片104、導線110、部分載板102與部分散熱板106,且封裝膠體108暴露出散熱板106的支撐部分107a頂面。
與第一封裝結構100類似,在第二封裝結構200中,晶片204配置於載板202的正面202a上。載板202例如為線路板。晶片204具有接墊204a,載板202具有接墊203a,且藉由導線208使晶片204的接墊204a與載板202的接墊203a電性連接。在本實施例中,晶片204與載板202之間配置有黏著層210,以將晶片204固定於載板202上。此外,載板202的背面202b具有接墊203b。封裝膠體206包覆晶片204、導線208與部分載板202。
凸塊300配置於第一封裝結構100中的散熱板106的支撐部分107a上。第二封裝結構200配置於第一封裝結構200上方,並藉由凸塊300使接墊203b與支撐部分107a上的線路層116電性連接。
在本實施例中,由於散熱板106上具有線路層116並藉由線路層116使第二封裝結構200與載板102電性連接,因此散熱板106可以取代先前技術中的隔離層與重配置線路板而同時具有承載第二封裝結構200以及散熱的功效。此外,由於重配置線路(線路層116)可由散熱板106之連接部份107b延伸,明顯減少了打線長度,以及避免過長之打線於封裝時塌陷、偏移等,使得封裝堆疊結構10能夠不僅具有較佳的散熱功效,同時也具有重配置缐路、以及穩固支撐第二封裝結構200與減少打線長度之效果。
圖2為依照本發明的第二實施例所繪示的封裝堆疊結構之剖面示意圖。在圖1與圖2中,相似的元件將以相似的標號表示。請參照圖2,封裝堆疊結構20與封裝堆疊結構10的差異在於散熱板的結構。進一步說,在第一封裝結構100’中,散熱板106’具有位於下表面106b上的線路層116’,且散熱板106’中具有多個導通孔122。導通孔122的材料例如為金、銀、銅、鋁等導電金屬材料,且導通孔122與線路層116’電性連接。導通孔122的外周緣與散熱板106’之間配置有絕緣層124。凸塊300藉由導通孔122與線路層116’電性連接,並藉由位於連接部分107b上的線路層116’電性連接至載板102。較佳地,連接部分107b與載板102之間可配置有黏著層120。黏著層120可為導電材料,其可選自於銲鍚、銀膠與異方性導電膠之一,因此不需要再利用導線118電性連接至載板102。
圖3為依照本發明的第三實施例所繪示的封裝堆疊結構之剖面示意圖。在圖1與圖3中,相似的元件將以相似的標號表示。請參照圖3,封裝堆疊結構30與封裝堆疊結構10的差異在於載板的結構與晶片的配置方式。進一步說,在第一封裝結構100”中,載板102’具有穿孔126。晶片104配置於載板102’的正面102a上。穿孔126暴露出接墊104a,導線110藉由穿孔126伸出並電性連接於載板102’的接墊103b。
同樣地,圖2中所揭示的散熱板106’以及散熱板106’與第二封裝結構200及載板102之接合方式亦可適用於如圖3所示之載板102’與晶片104的配置型態,於此不另行說明。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10、20、30...封裝堆疊結構
40、42...晶片封裝結構
100、100’、100”...第一封裝結構
102、102’、202、400、416...載板
102a、202a...正面
102b、202b...背面
103a、103b、104a、203a、203b、204a...接墊
104、204、402、418...晶片
106、106’...散熱板
106a...上表面
106b...下表面
107a...支撐部分
107b...連接部分
108、206、414、420...封裝膠體
110、118、208、410、412、424...導線
112、120、210、408、422...黏著層
114、300、426、428...凸塊
116、116’...線路層
122...導通孔
124...絕緣層
126...穿孔
200...第二封裝結構
404...隔離層
406...重配置線路板
圖1為依照本發明的第一實施例所繪示的封裝堆疊結構之剖面示意圖。
圖2為依照本發明的第二實施例所繪示的封裝堆疊結構之剖面示意圖。
圖3為依照本發明的第三實施例所繪示的封裝堆疊結構之剖面示意圖。
圖4為習知一種堆疊式封裝的剖面示意圖。
10...封裝堆疊結構
100...第一封裝結構
102、202...載板
102a、202a...正面
102b、202b...背面
103a、103b、104a、203a、203b、204a...接墊
104、204...晶片
106...散熱板
106a...上表面
106b...下表面
107a...支撐部分
107b...連接部分
108、206...封裝膠體
110、118、208...導線
112、120、210...黏著層
114、300...凸塊
116...線路層
200...第二封裝結構

Claims (9)

  1. 一種封裝堆疊結構,包括:一第一封裝結構,包括:一第一載板;一第一晶片,配置於該第一載板上,且藉由多條第一導線與該第一載板電性連接;一散熱板,包括支撐部分與連接部分,且該散熱板的表面上具有一線路層,其中該支撐部分位於該第一晶片上方,而該些連接部分分別位於該支撐部分的相對二側,該散熱板覆蓋該第一晶片與該些第一導線,且藉由該些連接部分上的該線路層電性連接至該第一載板,其中該散熱板由一金屬核心層與一絕緣層構成,該絕緣層配置於該金屬核心層的表面上,且該線路層配置於該絕緣層上;以及一第一封裝膠體,包覆該第一晶片、該些第一導線、部分該散熱板與部分該第一載板;多個凸塊,配置於該支撐部分上;以及一第二封裝結構,配置於該第一封裝結構上,並藉由該些凸塊與該第一封裝結構電性連接。
  2. 如申請專利範圍第1項所述之封裝堆疊結構,其中該散熱板具有一上表面以及與該上表面相對的一下表面,其中該上表面上具有該線路層,而該些凸塊與該線路層電性連接,且該第一封裝結構更包括多條第二導線,而位於該些連接部分上的該線路層藉由該些第二導線與該第一載 板電性連接。
  3. 如申請專利範圍第2項所述之封裝堆疊結構,更包括一黏著層,配置於該些連接部分與該第一載板之間。
  4. 如申請專利範圍第3項所述之封裝堆疊結構,其中該黏著層為一導電材料,該導電材料選自於銲鍚、銀膠與異方性導電膠之一。
  5. 如申請專利範圍第3項所述之封裝堆疊結構,其中該黏著層為一絕緣材料,該絕緣材料選自於環氧樹脂、兩階段性膠材、非導電膠與非導電膜之一。
  6. 如申請專利範圍第1項所述之封裝堆疊結構,其中該散熱板具有一上表面以及與該上表面相對的一下表面,其中該下表面上具有該線路層,且該散熱板中具有多個導通孔,而該些凸塊藉由該些導通孔與該線路層電性連接,且該散熱板藉由位於該些連接部分上的該線路層與該第一載板電性連接。
  7. 如申請專利範圍第6項所述之封裝堆疊結構,其中該些導通孔的外周緣與散熱板之間配置有一絕緣層。
  8. 如申請專利範圍第1項所述之封裝堆疊結構,其中該第二封裝結構,包括:一第二載板,藉由該些凸塊與該第一封裝結構電性連接;一第二晶片,配置於該第二載板上,且藉由多條第二導線與該第二載板電性連接;以及一第二封裝膠體,包覆該第二晶片、該些第二導線與 部分該第二載板。
  9. 如申請專利範圍第1項所述之封裝堆疊結構,其中該第一載板具有一正面、一背面以及一穿孔,該第一晶片配置於該第一載板的該正面,且該些第一導線藉由該穿孔伸出並電性連接於該第一載板的該背面。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140133105A1 (en) * 2012-11-09 2014-05-15 Nvidia Corporation Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structure
KR102265243B1 (ko) 2015-01-08 2021-06-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US20170127567A1 (en) * 2015-10-28 2017-05-04 Stmicroelectronics (Grenoble 2) Sas Electronic device equipped with a heat sink
CN106328620B (zh) * 2016-08-26 2021-03-09 苏州日月新半导体有限公司 集成电路封装体及其制造方法
CN106328611B (zh) * 2016-10-21 2019-03-12 苏州日月新半导体有限公司 半导体封装构造及其制造方法
US9953933B1 (en) * 2017-03-30 2018-04-24 Stmicroelectronics, Inc. Flow over wire die attach film and conductive molding compound to provide an electromagnetic interference shield for a semiconductor die
US11222877B2 (en) * 2017-09-29 2022-01-11 Intel Corporation Thermally coupled package-on-package semiconductor packages

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW479337B (en) * 2001-06-04 2002-03-11 Siliconware Precision Industries Co Ltd High heat dissipation efficiency stacked-die BGA chip package structure and manufacturing process
TWI227552B (en) * 2003-06-17 2005-02-01 Advanced Semiconductor Eng Stacked chip package structure
TW200935585A (en) * 2008-02-13 2009-08-16 Walton Advanced Eng Inc Stackable window BGA semiconductor package and stacked assembly utilized the same

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739581A (en) * 1995-11-17 1998-04-14 National Semiconductor Corporation High density integrated circuit package assembly with a heatsink between stacked dies
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
CN100336221C (zh) * 2002-11-04 2007-09-05 矽品精密工业股份有限公司 可堆栈半导体封装件的模块化装置及其制法
TWI317549B (en) * 2003-03-21 2009-11-21 Advanced Semiconductor Eng Multi-chips stacked package
TWI227553B (en) * 2003-06-30 2005-02-01 Advanced Semiconductor Eng Stacked chip package structure
CN100386876C (zh) * 2004-03-26 2008-05-07 乾坤科技股份有限公司 多层基板堆叠封装结构
TWI423401B (zh) * 2005-03-31 2014-01-11 Stats Chippac Ltd 在上側及下側具有暴露基底表面之半導體推疊封裝組件
CN100481420C (zh) * 2005-09-08 2009-04-22 南茂科技股份有限公司 堆叠型芯片封装结构、芯片封装体及其制造方法
US7435619B2 (en) * 2006-02-14 2008-10-14 Stats Chippac Ltd. Method of fabricating a 3-D package stacking system
KR101210090B1 (ko) * 2006-03-03 2012-12-07 엘지이노텍 주식회사 금속 코어 인쇄회로기판 및 이를 이용한 발광 다이오드패키징 방법
TWI409924B (zh) * 2007-09-12 2013-09-21 Advanced Semiconductor Eng 半導體封裝體及其製造方法
TWI356482B (en) * 2007-09-20 2012-01-11 Advanced Semiconductor Eng Semiconductor package and manufacturing method the
TW200917431A (en) * 2007-10-05 2009-04-16 Advanced Semiconductor Eng Stacked-type chip package structure and method of fabricating the same
US9022632B2 (en) * 2008-07-03 2015-05-05 Samsung Electronics Co., Ltd. LED package and a backlight unit unit comprising said LED package
CN101882606B (zh) * 2009-05-08 2012-09-19 日月光封装测试(上海)有限公司 散热型半导体封装构造及其制造方法
TWI389296B (zh) * 2009-06-25 2013-03-11 Advanced Semiconductor Eng 可堆疊式封裝結構及其製造方法及半導體封裝結構
KR101125296B1 (ko) * 2009-10-21 2012-03-27 엘지이노텍 주식회사 라이트 유닛

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW479337B (en) * 2001-06-04 2002-03-11 Siliconware Precision Industries Co Ltd High heat dissipation efficiency stacked-die BGA chip package structure and manufacturing process
TWI227552B (en) * 2003-06-17 2005-02-01 Advanced Semiconductor Eng Stacked chip package structure
TW200935585A (en) * 2008-02-13 2009-08-16 Walton Advanced Eng Inc Stackable window BGA semiconductor package and stacked assembly utilized the same

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