TWI651828B - 晶片封裝結構及其製造方法 - Google Patents

晶片封裝結構及其製造方法 Download PDF

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TWI651828B
TWI651828B TW106135586A TW106135586A TWI651828B TW I651828 B TWI651828 B TW I651828B TW 106135586 A TW106135586 A TW 106135586A TW 106135586 A TW106135586 A TW 106135586A TW I651828 B TWI651828 B TW I651828B
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Taiwan
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chip
conductive
carrier board
branch frame
circuit carrier
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TW106135586A
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TW201824500A (zh
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王啓安
徐宏欣
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力成科技股份有限公司
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Priority to CN201710982289.5A priority Critical patent/CN107978584B/zh
Publication of TW201824500A publication Critical patent/TW201824500A/zh
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Abstract

一種晶片封裝結構，其包括線路載板、第一晶片、支線架、多個第一導電連接件、第一密封體以及封裝件。第一晶片配置於線路載板上。第一晶片具有主動面以及相對於主動面的晶背，且主動面面向線路載板。支線架位於第一晶片的晶背上，且支線架具有多個開口。第一導電連接件位於線路載板上，且第一導電連接件對應於開口配置。第一密封體位於線路載板與支線架之間且包封第一晶片。封裝件配置於支線架上且藉由第一導電連接件電性連接至線路載板。

Description

晶片封裝結構及其製造方法
本發明是有關於一種晶片封裝結構及其製造方法，且特別是有關於一種具有支線架的晶片封裝結構及其製造方法。
近年來，符合市場需求的電子設備以及製造技術的提升正在蓬勃地發展。考量到電腦（computer），通信（communication）以及消費（consumer）等3C電子產品的便攜性以及其不斷成長的需求，傳統的單晶片封裝結構已逐漸不符合市場的需求。也就是說，於產品設計之時，必須考慮到輕、薄、短、小、緊密度、高密度以及低成本的趨勢。因此，有鑑於對輕、薄、短、小以及緊密度的需求，以不同的方式堆疊具有各種功能的積體電路（integrated circuits；IC），以減少封裝產品的尺寸以及厚度，已成為封裝市場的主流策略。目前，具有封裝層疊（package on package；POP）結構的封裝產品乃是為了此趨勢而研究開發。
然而，在一般封裝層疊結構的封裝產品的製造過程中，常需要藉由不同的機台設備或製程以將不同的電子元件彼此電性連接。如此一來，常會造成良率（yield）或可靠性（reliability）的降低，也會降低生產率（throughput）且增加生產成本。因此，如何進一步提升封裝結構的良率及產品的可靠度，且可以提升生產率且降低生產成本，實已成目前亟欲解決的課題。
本發明提供一種晶片封裝結構，其具有較佳的良率或可靠性以及較低的生產成本。
本發明更提供一種晶片封裝結構的製造方法，其可以提升生產率且在製程上具有較大的製程裕度（process window），而可以提升晶片封裝結構的生產率及/或良率，並且降低了晶片封裝結構的生產成本。
本發明提供一種封裝結構，其包括線路載板、第一晶片、支線架、多個第一導電連接件、第一密封體以及封裝件。第一晶片配置於線路載板上。第一晶片具有主動面以及相對於主動面的晶背，且主動面面向線路載板。支線架位於第一晶片的晶背上，且支線架具有多個開口。第一導電連接件位於線路載板上，且第一導電連接件對應於開口配置。第一密封體位於線路載板與支線架之間且包封第一晶片。封裝件配置於支線架上且藉由第一導電連接件電性連接至線路載板。
在本發明的一實施例中，支線架的支線架表面、各個第一導電連接件的頂面與第一密封體的密封體表面齊平。
在本發明的一實施例中，支線架的開口與第一晶片不重疊。
本發明提供一種封裝結構的製造方法。本方法包括至少以下步驟。配置第一晶片於線路載板上，其中所述第一晶片具有主動面以及相對於所述主動面的晶背，且所述主動面面向所述線路載板。配置支線架於第一晶片的晶背上，且支線架具有多個開口。於線路載板上形成多個接線，且多個接線穿過對應的多個開口。在形成多個接線之後，於線路載板與支線架之間形成第一密封體，以包封第一晶片。移除部分的多個接線，以形成多個第一導電連接件。於支線架上配置封裝件，且封裝件藉由多個第一導電連接件電性連接至線路載板。
在本發明的一實施例中，形成第一密封體的步驟包括：於線路載板上形成第一密封材料，其中第一密封材料位於線路載板與支線架之間且包封第一晶片、支線架以及接線。移除部分的第一密封材料，以暴露出支線架以及接線，而形成第一密封體。
在本發明的一實施例中，接線藉由打線接合方式形成。
在本發明的一實施例中，形成多個接線的步驟包括：將瓷嘴伸入對應的開口。藉由瓷嘴以使導電材料與線路載板接觸。將供應導電材料的瓷嘴伸出對應的開口，以形成對應的接線。
在本發明的一實施例中，封裝結構的製造方法更包括以下步驟。於第一晶片的晶背上形成黏著層，且支線架藉由黏著層貼附於第一晶片。
在本發明的一實施例中，封裝結構的製造方法更包括以下步驟。於線路載板上形成多個導電端子，導電端子電性連接至線路載板，且線路載板位於第一晶片與導電端子之間。
在本發明的一實施例中，封裝件包括線路層、第二晶片以及第二密封體。第二晶片配置於線路層上且電性連接至線路層。第二密封體位於線路層上且包封第二晶片。
在本發明的一實施例中，封裝件更包括多個第二導電連接件。其中線路層位於第二導電連接件與第二晶片之間，且將封裝件配置於支線架上之後，各個第二導電連接件完全覆蓋對應的開口。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1G是依據本發明一實施例的晶片封裝結構的製造方法的剖面示意圖。請參照圖1A，提供線路載板110。線路載板110可以具有第一表面110a以及相對於第一表面110a的第二表面110b。舉例而言，線路載板110可以包括第一線路層111、核心層112、第二線路層113以及多個導通孔114。第一線路層111位於第一表面110a，且第二線路層113位於第二表面110b，且第一線路層111與第二線路層113可以藉由貫穿核心層112的導通孔114而彼此電性連接。在一些實施例中，第一線路層111可以包括多個第一接墊111a，且第二線路層113可以包括多個第二接墊113a。第一線路層111可以藉由第一接墊111a以與其他電子元件電性連接，第二線路層113可以藉由第二接墊113a以與其他電子元件電性連接。在本實施例中，線路載板110為雙面線路板（double sided wiring board），但本發明不限於此。在其他實施例中，線路載板110也可以是多層線路板（multi-layered wiring board）。當線路載板110為多層線路板時，線路載板110中的至少兩層線路層171之間可用通孔（through hole）或者是盲孔（blind hole）來電性連接。
請繼續參照圖1A，將第一晶片120於配置線路載板110上，並電性連接線路載板110。第一晶片120可以是晶粒（die）、封裝後晶片（packaged chip）、堆疊式的晶片封裝件170（stacked chip package）或是特殊應用積體電路（Application-Specific Integrated Circuit；ASIC），但本發明不限於此。第一晶片120具有主動面120a以及相對於主動面120a的晶背120b，且主動面120a面向所述線路載板110。在本實施例中，第一晶片120可用覆晶（flip chip）的方式藉由連接端子121與線路載板110上的部分第一接墊111a電性連接，但本發明不限於此。在相關封裝實施方式中，第一晶片120也可經由線路載板110的增層或減層技術以將第一晶片120置於線路載板110內部，其未顯示於本發明說明書之相關圖示。
在一些實施例中，可以線路載板110可以包括位於第二接墊113a上的多個導電端子115。導電端子115例如為陣列排列的焊球（solder balls）、凸塊（bumps）、導電柱（conductive pillars）或上述的組合等，以使第一晶片120藉由線路載板110以及對應的導電端子115與其他外部元件電性連接。然而，本實施例中對於導電端子115的材質、型態、形成方式或形成順序並不加以限制。
請同時參照圖1B與圖2，其中圖2是依據本發明一實施例的支線架140的上視示意圖。在將第一晶片120配置於線路載板110上之後，將支線架140配置於第一晶片120的晶背120b上。支線架140具有多個開口141，且開口141與第一晶片120不重疊。在本實施例中，支線架140的各個開口141可以具有對應的第一接墊111a。在本實施例中，支線架140可以為絕緣體。如此一來，縱使位於開口141內的導電元件（如：後續所形成的第一導電連接件150）與支線架140接觸也可以避免支線架140與其他元件的電性連接。在其他實施例中，支線架140暴露在外的表面可以為絕緣材料，以使支線架140可以不與任何的導電元件因接觸而電性連接。
在本實施例中，支線架140可以藉由黏著層130貼附於第一晶片120的晶背120b上，且黏著層130例如為例如是晶片貼合膜（die attached film；DAF），但本發明不限於此。
請同時參照圖1C與圖3，其中圖3是圖1C中的區域R的放大圖。在將支線架140配置於第一晶片120的晶背120b上之後，於線路載板110上形成多個接線152。各個接線152的徑寬150a小於開口141的口徑141a，以使各個接線152可以穿過支線架140上對應的開口141。在本實施例中，接線152可以藉由打線接合（wire bonding）方式與部分的第一接墊111a連接，但本發明不限於此。
以一般的打線接合方式為例，可以先將打線機（未完全繪示）的瓷嘴（capillary）10伸入對應的開口141內。瓷嘴10可以讓導電材料151導電材料151，且伸入開口141內的瓷嘴10的瓷嘴寬度10a小於開口141的口徑141a。在瓷嘴10伸入對應的開口141內之後，使導電材料151穿過瓷嘴10，穿出瓷嘴10的導電材料151在對應的第一接墊111a上經過下壓且連接後，導電材料151的連接端點151a可與線路載板110上的第一接墊111a連接。前述的連接方式可以為熱壓接合（thermocompression bonding）、超音波接合（ultrasonic bonding）或熱音波接合（thermosonic bonding），於本發明並不加以限制。在導電材料151與第一接墊111a連結之後，可以使瓷嘴10朝向遠離於線路載板110的方向伸出開口141，以使瓷嘴10內的導電材料151引出瓷嘴10。在瓷嘴10伸出開口141之後，可以截斷穿出瓷嘴10的導電材料151，以形成接線152。藉由上述的步驟的循環，可以形成多個接線152。各個接線152貫穿支線架140上對應的開口141，且與對應的第一接墊111a電性連接。
一般而言，在上述的打線接合方式中，瓷嘴10的瓷嘴寬度10a大約是60微米（micrometer；μm），而支線架140上對應的開口141的口徑141a大約是75微米，且所形成的接線152的徑寬150a約為20微米。然而，上述瓷嘴寬度10a、口徑141a以及徑寬150a的數值僅為示例性的舉例。於本實施例中，僅需使開口141的口徑141a大於瓷嘴10的瓷嘴寬度10a，以及使開口141的口徑141a大於接線152的徑寬150a即可。
參照圖1D，在形成多個接線152之後，於線路載板110上形成第一密封材料161。在一些實施例中，第一密封材料161例如是藉由模塑製程（molding process）或其他合適的方法將熔融的模塑化合物（molding compound）形成於線路載板110上。然後，使熔融的模塑化合物冷卻並且固化。在本實施例中，第一密封材料161位於線路載板110與支線架140之間且包封所述第一晶片120、支線架140以及多個接線152。換言之，第一晶片120並不會露出來，且貫穿開口141的接線152可以藉由填充於開口141內的第一密封材料161而固定。
參照圖1E，在形成第一密封材料161（繪示於圖1D）之後，可以藉由裁切、研磨、蝕刻或其他適宜的方式，以將接線152（繪示於圖1D）凸出於支線架140的支線架表面140a的部分移除，而形成第一導電連接件150。如此一來，可以使第一導電連接件150的頂面150b大致上與支線架140的支線架表面140a表面齊平。藉由前述的示例性實施方式，本實施例中的第一導電連接件150可以為藉由打線機所形成的柱形凸塊（stud bump）。換言之，相較於第一導電連接件150遠離於線路載板110部分的徑寬150a，第一導電連接件150與線路載板110連接的連接端點151a的具有較大的寬度。
在本實施例中，若第一密封材料161進一步覆蓋至支線架140的支線架表面140a上（如：圖1D所繪示），也可以進一步將第一密封材料161覆蓋於支線架140的支線架表面140a的部分移除，以暴露出支線架140以及多個接線152，而形成第一密封體160。在本實施例中，第一密封材料161可以藉由研磨製程、蝕刻製程或其他適宜的製程移除，但本發明不限於此。
在其他實施例中，若第一密封材料161已填充於開口141內且沒有覆蓋在支線架140的支線架表面140a上，也可以省略前述移除部分第一密封材料161的步驟，而所形成的第一密封材料161即為第一密封體160。
在一些實施例中，可以對第一密封體160、支線架140及/或第一導電連接件150實施平坦化製程（planarization process），以使支線架140的支線架表面140a、第一密封體160的密封體表面160a以及各個第一導電連接件150的頂面150b齊平。
參照圖1F，提供封裝件170。封裝件170可以包括線路層171、第二晶片172以及第二密封體173。第二晶片172配置於線路層171上且電性連接至線路層171。第二密封體173位於線路層171上且包封第二晶片172。
在本實施例中，第二晶片172是藉由覆晶的方式與線路層171電性連接，但本發明不限於此。在其他實施例中，第二晶片172可以藉由打線接合的方式與線路層171電性連接。
在本實施例中，線路層171可以為雙面線路板，但本發明不限於此。在其他實施例中，線路層171也可以是多層線路板或具有重佈線路層（redistribution layer；RDL）。
在本實施例中，第二晶片172可以是晶粒、封裝後晶片、堆疊式的晶片封裝件或是特殊應用積體電路，但本發明不限於此。
在本實施例中，封裝件170可以更包括多個第二導電連接件174，多個第二導電連接件174位於線路層171上且相對於第二晶片172。換言之，線路層171位於所述多個第二導電連接件174與所述第二晶片172之間。第二導電連接件174可以於後續的製程中，使封裝件170藉由第二導電連接件174與其他的元件電性連接。第二導電連接件174例如為焊球，但本發明不限於此。
參照圖1G，封裝件170配置在支線架140上，且封裝件170藉由多個第一導電連接件150電性連接至線路載板110，以構成封裝層疊（Package on Package；POP）的晶片封裝結構100。舉例而言，可以使封裝件170上的各個第二導電連接件174與對應的第一導電連接件150接觸，以使封裝件170內的第二晶片172藉由線路層171、第二導電連接件174、第一導電連接件150電性連接至線路載板110。
經過上述製程後即可大致上完成本實施例的晶片封裝結構100的製作。上述的晶片封裝結構100包括線路載板110、第一晶片120、支線架140、多個第一導電連接件150、第一密封體160以及封裝件170。第一晶片120配置於線路載板110上。第一晶片120具有主動面120a以及相對於主動面120a的晶背120b，且主動面120a面向線路載板110。支線架140位於第一晶片120的晶背120b上，且支線架140具有多個開口141。第一導電連接件150位於線路載板110上，且各個第一導電連接件150與對應的一個開口141配置。第一密封體160位於線路載板110與支線架140之間。第一密封體160包封第一晶片120且與第一導電連接件150的側壁150c直接接觸。封裝件170配置於支線架140上且藉由第一導電連接件150電性連接至線路載板110。
在本實施例中，第一導電連接件150可以為藉由打線機所形成的柱形凸塊，且構成第一導電連接件150的導電材料151（繪示於圖1C）可以是在形成第一密封體160之前已與線路載板110電性連接。在一般的穿塑孔技術（through mold via；TMV）中，通常是先行成模塑化合物，接著再以雷射裝置以雷射鑽孔（laser drilling）的方式形成通孔（through via），而後再以電鍍、沉積或其他將導電物質填充的類似方式形成導電通孔（conductive via）。相較於上述的穿塑孔技術，本實施例可以省略使用雷射裝置以形成的雷射鑽孔，因此可以降低生產成本。或是，以蝕刻、機械鑽孔（mechanical drill）、雷射鑽孔（laser drill）或其他似的移除方式常會因通孔內所留下的膠渣（smear），而使導電通孔的導電性降低。因此，在一般的穿塑孔技術中常需要使用額外的去膠渣製程（desmear process）。由於本實施例構成第一導電連接件150的導電材料151可以是在形成第一密封體160之前已與線路載板110電性連接，因此可以具有較佳的導電性，且可以省略模塑化合物的移除製程以及後續的導電物質填充製程，而可以提升生產率。除此之外，相較於預先成型（preformed）的導電柱，藉由打線機所形成的柱形凸塊可以具有較低的生產成本，且可以具有較佳的細間距（fine pitch），因此在配置上可以具有較大的彈性。
在本實施例中，由於在晶片封裝結構100的製程中，各個第一導電連接件150是藉由打線機將接線152（繪示於圖1C、1D）穿過支線架140的對應開口141之後，再將接線152凸出於支線架140的支線架表面140a的部分移除所形成。如此一來，具有多個開口141的支線架140可以具有類似於整線（wire trimming）的功能，而可以降低相鄰的接線152及/或第一導電連接件150之間不必要的觸碰，以提升晶片封裝結構100的良率或可靠性。
在本實施例中，由於支線架140可以藉由黏著層130貼附於第一晶片120的晶背120b。如此一來，可以藉由具有較佳導熱性的材質來構成支線架140，及/或藉由具有較佳導熱性的黏著層130，以提升晶片封裝結構100的散熱性。
在本實施例中，由於各個第一導電連接件150遠離於線路載板110的一端位於支線架140的對應開口141內，且遠離於線路載板110的一端的頂面150b暴露於第一密封體160。因此，封裝件170上的第二導電連接件174可以僅需要對準且完全覆蓋對應的開口141即可以與第一導電連接件150接觸而電性連接。如此一來，在第二導電連接件174及/或第一導電連接件150的配置上可以具有較大的製程裕度，而可以提升晶片封裝結構100的生產率及/或良率。
綜上所述，在本發明的晶片封裝結構中，第一導電連接件可以為藉由打線機所形成，且構成第一導電連接件的導電材料可以是在形成第一密封體之前已與線路載板電性連接，因此可以具有較佳的導電性且可以提升生產率。並且，藉由打線機所形成的第一導電連接件可以具有較低的生產成本，且可以具有較佳的細間距，因此在配置上可以具有較大的彈性。除此之外，在本發明的晶片封裝結構中，由於支線架上具有多個開口，因此可以提升晶片封裝結構的製造過程的良率或可靠性，也可以具有較大的製程裕度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧瓷嘴
10a‧‧‧瓷嘴寬度
100‧‧‧晶片封裝結構
110‧‧‧線路載板
110a‧‧‧第一表面
110b‧‧‧第二表面
111‧‧‧第一線路層
111a‧‧‧第一接墊
112‧‧‧核心層
113‧‧‧第二線路層
113a‧‧‧第二接墊
114‧‧‧導通孔
115‧‧‧導電端子
120‧‧‧第一晶片
120a‧‧‧主動面
120b‧‧‧晶背
121‧‧‧連接端子
130‧‧‧黏著層
140‧‧‧支線架
140a‧‧‧支線架表面
141‧‧‧開口
141a‧‧‧口徑
150‧‧‧第一導電連接件
150a‧‧‧徑寬
150b‧‧‧頂面
150c‧‧‧側壁
151‧‧‧導電材料
151a‧‧‧連接端點
152‧‧‧接線
160‧‧‧第一密封體
160a‧‧‧密封體表面
161‧‧‧第一密封材料
170‧‧‧封裝件
171‧‧‧線路層
172‧‧‧第二晶片
173‧‧‧第二密封體
174‧‧‧第二導電連接件
R‧‧‧區域
圖1A至圖1G是依據本發明一實施例的晶片封裝結構的製造方法的剖面示意圖。 圖2是依據本發明一實施例的支線架的上視示意圖。 圖3是圖1C中的區域R的放大圖。

Claims (10)

  1. 一種晶片封裝結構，包括：線路載板；第一晶片，配置於所述線路載板上，所述第一晶片具有主動面以及相對於所述主動面的晶背，且所述主動面面向所述線路載板；支線架，位於所述第一晶片的所述晶背上，且所述支線架具有多個開口；多個第一導電連接件，位於所述線路載板上，各個所述多個第一導電連接件為一體的導電元件，且所述多個第一導電連接件對應於所述多個開口配置；第一密封體，位於所述線路載板與所述支線架之間且包封所述第一晶片；以及封裝件，配置於所述支線架上且藉由所述多個第一導電連接件電性連接至所述線路載板，其中所述支線架的支線架表面、所述第一密封體的密封體表面以及各個所述多個第一導電連接件的頂面齊平。
  2. 如申請專利範圍第1項所述的晶片封裝結構，其中第一密封體填充於所述多個開口內且暴露出各個所述多個第一導電連接件。
  3. 如申請專利範圍第1項所述的晶片封裝結構，其中第一密封體直接覆蓋各個所述多個第一導電連接件的側壁。
  4. 如申請專利範圍第1項所述的晶片封裝結構，其中各個所述多個第一導電連接件為柱形凸塊(stud bump)。
  5. 如申請專利範圍第1項所述的晶片封裝結構，其中各個所述多個第一導電連接件的徑寬小於各個所述多個開口的口徑。
  6. 如申請專利範圍第1項所述的晶片封裝結構，其中所述支線架與所述線路載板、所述第一晶片、所述多個第一導電連接件以及所述封裝件電性絕緣。
  7. 如申請專利範圍第1項所述的晶片封裝結構，更包括：黏著層，位於所述第一晶片與所述支線架之間。
  8. 如申請專利範圍第1項所述的晶片封裝結構，更包括：多個導電端子，電性連接至所述線路載板，且所述線路載板位於所述第一晶片與所述多個導電端子之間。
  9. 如申請專利範圍第1項所述的晶片封裝結構，其中所述封裝件包括：線路層；第二晶片，配置於所述線路層上且電性連接至所述線路層；第二密封體，位於所述線路層上且包封所述第二晶片；以及多個第二導電連接件，其中所述線路層位於所述多個第二導電連接件與所述第二晶片之間，且各個所述多個第二導電連接件完全覆蓋對應的所述多個開口。
  10. 一種晶片封裝結構的製造方法，包括：配置第一晶片於線路載板上，其中所述第一晶片具有主動面以及相對於所述主動面的晶背，且所述主動面面向所述線路載板；配置支線架於所述第一晶片的所述晶背上，且所述支線架具有多個開口；於所述線路載板上形成多個接線，且所述多個接線穿過對應的所述多個開口；在形成所述多個接線之後，於所述所述線路載板與所述支線架之間形成第一密封體，以包封所述第一晶片；移除部分的所述多個接線，以形成多個第一導電連接件，其中各個所述多個第一導電連接件為一體的導電元件，且所述支線架的支線架表面、所述第一密封體的密封體表面以及各個所述多個第一導電連接件的頂面齊平；以及於所述支線架上配置封裝件，且所述封裝件藉由所述多個第一導電連接件電性連接至所述線路載板。
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