TWI644369B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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Publication number
TWI644369B
TWI644369B TW106135873A TW106135873A TWI644369B TW I644369 B TWI644369 B TW I644369B TW 106135873 A TW106135873 A TW 106135873A TW 106135873 A TW106135873 A TW 106135873A TW I644369 B TWI644369 B TW I644369B
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Taiwan
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substrate
conductive
circuit carrier
section
sealing body
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TW106135873A
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TW201830527A (zh
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王啓安
徐宏欣
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力成科技股份有限公司
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Abstract

本發明提供一種封裝結構及其製造方法。封裝結構包含電路載體、基板、晶粒、多根導電線以及密封體。基板設置於電路載體上且包含多個開口。晶粒設置於電路載體與基板之間。導電線穿過基板的開口以電性連接在基板與電路載體之間。密封體設置於電路載體上且密封晶粒、基板以及導電線。

Description

封裝結構及其製造方法
本發明是有關於一種封裝結構(package structure)及其製造方法，且特別是有關於一種半導體封裝結構(semiconductor package structure)。
為了使電子產品設計實現輕、薄、短且小，半導體封裝技術正持續進步，以嘗試開發出體積較小、重量較輕、整合度較高且更具市場競爭力的產品。舉例來說，已開發例如封裝等3D堆疊技術以滿足較高封裝密度的要求。因此，對於本領域研究人員來說，如何以較低製造成本增加輸入/輸出(Input/output，I/O)連接的數目已成為挑戰。
本發明提供一種封裝結構及其製造方法，其降低製造成本且增加I/O連接的數目。
本發明的提供一種封裝結構製造方法。所述方法至少包 含以下步驟。設置晶粒於電路載體上。設置基板於晶粒上。基板包含多個開口。形成穿過基板的開口的多根導電線，以在基板與電路載體之間形成電性連接。形成密封體在電路載體上，以密封晶粒、基板以及導電線。
在本發明的一實施例中，晶粒是經由覆晶接合而設置於電路載體上。
在本發明的一實施例中，設置基板於晶粒上是使用黏著層將基板與晶粒彼此黏附。
在本發明的一實施例中，導電線是經由打線機形成。
在本發明的一實施例中，在基板上形成開口，其中開口環繞晶粒的外圍。
本發明提供一種封裝結構，包含電路載體、基板、晶粒、多根導電線以及密封體。基板設置於電路載體上且包含多個開口。晶粒設置於電路載體與基板之間。導電線穿過基板的開口，以在基板與電路載體之間電性連接。密封體設置於電路載體上且密封晶粒、基板以及導電線。
在本發明的一實施例中，封裝結構還包括設置於電路載體與基板之間的黏著層。
在本發明的一實施例中，晶粒包括面向電路載體的多個導電凸塊，且晶粒經由導電凸塊電性連接到電路載體。
在本發明的一實施例中，導電線中的每一者的線弧高度大於基板的與電路載體相對的表面及電路載體的面向基板的表面 之間的距離。
在本發明的一實施例中，開口環繞晶粒的外圍而佈置於基板上。
基於上述，設置於晶粒上的基板有利於形成導電線。此外，基板可以作為用於進一步電性連接的導電介面。此外，因為通孔形成於密封體上以暴露出基板的至少一部分，因此使得封裝結構更靈活以與不同裝置應用相容。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
10、20、30‧‧‧封裝結構
110‧‧‧電路載體
112‧‧‧核心層
114‧‧‧頂部電路層
114a、116a‧‧‧導電接墊
116‧‧‧底部電路層
118‧‧‧導電結構
120‧‧‧晶粒
122‧‧‧導電凸塊
130‧‧‧基板
130a‧‧‧開口
130b‧‧‧導電層
130c‧‧‧表面
140‧‧‧黏著層
150‧‧‧導電線
150a‧‧‧第一區段
150b‧‧‧中心區段
150c‧‧‧第二區段
160‧‧‧密封體
160a‧‧‧通孔
160b‧‧‧表面
170‧‧‧導電元件
200‧‧‧半導體元件
202‧‧‧導電結構
D1、D3‧‧‧距離
D2‧‧‧深度
H‧‧‧高度
S1‧‧‧頂表面
S2‧‧‧底表面
圖1A至圖1D為說明根據本發明的實施例的封裝結構製造方法的剖面示意圖。
圖2為說明根據本發明的實施例的封裝結構的基板的俯視示意圖。
圖3為說明根據本發明的實施例的封裝結構的剖面示意圖。
圖4為說明根據本發明的實施例的封裝結構的剖面示意圖。
圖1A到圖1D為說明根據本發明的實施例的封裝結構製造方法的剖面示意圖。圖2為說明根據本發明的實施例的封裝結 構的基板的俯視示意圖。參考圖1A，提供電路載體110(circuit carrier)。電路載體110可以具有頂表面S1以及與頂表面S1相對的底表面S2。舉例來說，電路載體110可以包含核心層(core layer)112、設置於頂表面S1上的頂部電路層114以及設置於電路載體110的底表面S2上的底部電路層116。換句話說，核心層112設置於頂部電路層114與底部電路層116之間，且電性連接頂部電路層114與底部電路層116。在一些實施例中，頂部電路層114可以包含多個導電接墊(conductive pad)114a，且底部電路層116可以包含用於電性連接的多個導電接墊116a。此外，頂部電路層114的導電接墊114a與底部電路層116的導電接墊116a可以是由相同材料如銅、焊料、金、鎳等等，以及例如微影(photolithography)和蝕刻(etching)製程等相同製程形成。在其它實施例中，頂部電路層114的導電接墊114a與底部電路層116的導電接墊116a可以根據設計要求而由不同材料和/或不同製程形成。
核心層112可以包含作為中間電路層以電性連接頂部電路層114與底部電路層116的多個嵌入電路層。舉例來說，核心層112可以包含基底層以及穿透所述基底層的多個導電通孔(conductive vias)。此外，核心層112的導電通孔的兩個相對末端可以電性連接到頂部電路層114的導電接墊114a以及底部電路層116的導電接墊116a。在一些實施例中，電路載體110可以包含形成於底表面S2上的多個導電結構118。舉例來說，導電結構118的材料可以包含銅、錫、金、鎳或其它合適導電材料，並不限 於此。此外，導電結構118可以例如為導電凸塊(conductive bump)、導電柱(conductive pillar)或透過植球製程(ball placement process)以及回焊製程(reflow process)形成的焊球(solder ball)。可以利用其它可能的形式和形狀的導電結構118，以進行進一步的電性連接。在一些實施例中，導電結構118可以根據後續製程的需求，而形成佈置於電路載體110的底表面S2上的帶微間距的陣列(fine pitched array)。
此外，晶粒(die)120接合於電路載體110的頂表面S1上。晶粒120可以經由覆晶接合(flip-chip bonding)而電性連接到電路載體110。在一些實施例中，晶粒120的主動面(active surface)(未繪示)可以經由面向電路載體110的多個導電凸塊122而連接到電路載體110的頂部電路層114的導電接墊114a。導電凸塊122可以是銅凸塊(copper bumps)。在一些實施例中，焊料(solders)(未繪示)可以塗覆到導電凸塊122的表面上，以與電路載體110的頂部電路層114的導電接墊114a耦合。此外，晶粒120可以是例如特殊應用積體電路(Application-Specific Integrated Circuit，ASIC)。在一些實施例中，晶粒120可以用來執行邏輯應用(logic applications)，但本發明並不以此為限。其它合適主動裝置也可以作為晶粒120。此外，底膠(underfill)(未繪示)可以形成於電路載體110的頂表面S1上，並且形成於晶粒120的主動面與電路載體110的頂表面S1之間的間隙中，以增強晶粒接合製程的可靠性(reliability)。
參考圖1B以及圖2，基板130設置於晶粒120上。基板130可以包含多個開口130a。基板130的材料可以包含導電材料(例如鋁、銅、鎳、金或其合金等)、非導電材料(例如玻璃、剛性塑膠(rigid plastic)等)或其組合。其它合適的材料可以適用為基板130，只要材料能夠耐受在其上執行的處理製程即可。此外，本發明並不限制基板130的大小、形狀以及厚度。此外，基板130的開口130a可以經由機械鑽孔、微影以及蝕刻或其它合適的方法形成，並不限於此。此外，參考圖2，基板130的開口130a可以形成於基板130上，環繞晶粒120的外圍。此外，開口130a可以與晶粒120錯開(staggered)。本發明並不限制開口130a的數目。
在一些實施例中，導電層130b可以利用物理氣相沉積(physical vapor deposition，PVD)、化學氣相沉積(chemical vapor deposition，CVD)、電鍍或其它合適的金屬沉積製程而形成於與基板130的晶粒120相對的表面130c上，但不限於此。導電層130b的材料可以包含鋁、銅、金、銀或其它合適的導電材料，但本發明並不以此為限。在其它實施例中，導電層130b可以經圖案化以形成為多個導電連接器(conductive connectors)，例如接觸接墊(如鋁接墊、銅接墊等)。換句話說，基板130不僅作為用於執行後續電接合處理的導電連接器，而且提供隔板(spacer)功能，以防止損壞晶粒120。
基板130可以是經由黏著層(adhesive layer)140接合到 晶粒120。在一些實施例中，黏著層140可以是晶粒附著膜(die attach film)或由包含環氧樹脂(epoxy resin)的黏著材料形成。黏著層140可以透過例如旋塗(spin coating)、噴墨印刷(inject printing)或其它合適的方法或用於提供結構支撐的其它合適方法而形成，而不需要晶粒120與基板130之間的機械夾持。
參考圖1C，基板130與電路載體110透過穿過基板130的開口130a的多根導電線150而電性連接。舉例來說，導電線150可以經由打線機(wire bonder)(未繪示)形成。打線機的類型可以根據設計要求而包含楔型接合(wedge bond)、球型接合(ball bond)或其它合適的打線機。此外，導電線150連接於基板130的導電層130b與電路載體110之間。導電線150的材料可以是金、銅或其它合適材料，並不限於此。在一些實施例中，導電線150可以從基板130形成到電路載體110。在其它實施例中，導電線150可以從電路載體110形成到基板130。導電線150的形成順序可以取決於設計要求。在一些實施例中，因為導電線150形成於基板130的導電層130b與電路載體110之間且穿過基板130的開口130a，因此基板130的開口130a的大小可以是足夠大的尺寸，以使打線機通過。
此外，導電線150中的每一者的頂端(peak)(未繪示)定義為在連接基板130與電路載體110之後，相對於導電線150中的每一者的兩個末端之間的最高點。此外，導電線150中的每一者的線弧(loop)高度H定義為導電線150中的每一者的頂端 與電路載體110之間的距離。導電線150中的每一者的線弧高度H的數值取決於打線機的類型和/或設計要求。
此外，導電線150中的每一者可以包含第一區段150a、中心區段150b以及第二區段150c。第一區段150a可以連接到電路載體110，第二區段150c可以連接到基板130，且中心區段150b可以是第一區段150a與第二區段150c之間的區段。在一些實施例中，第一區段150a可以形成於基板130下方，且第二區段150c可以形成於基板130上方。導電線150中的每一者的第二區段150c可以形成為弧形(arc shape)。此外，導電線150中的每一者的頂端可以是第二區段150c的最高點。此外，中心區段150b可以穿過對應的基板130的開口130a。在一些實施例中，導電線150中的每一者的線弧高度H可以大於基板130的表面130c與電路載體110的頂表面S1之間的距離D1。
參考圖1D，密封體(encapsulant)160形成於電路載體110上，以密封晶粒120、基板130、黏著層140以及導電線150。在一些實施例中，密封體160的厚度大於導電線150的線弧高度H。此外，密封體160可以包含透過模製製程(molding process)形成的模製化合物(molding compound)。在一些實施例中，密封體160可以透過例如環氧樹脂、樹脂、可模製聚合物(moldable polymer)或其它合適的樹脂等絕緣材料形成，但本發明不限於此。
因此，封裝結構10具有堆疊於晶粒120上的基板130，基板130作為用於執行打線製程的導電介面，且不必在封裝結構 10內形成額外中介層(interposer)來進一步的電性連接。以此方式，可以實現製造成本較低的簡化的製造方法。
圖3為說明根據本發明的實施例的封裝結構的剖面示意圖。參考圖3，封裝結構20的製造方法類似於圖1A到圖1D中所說明的實施例的製造方法。本文中省略詳細描述。本實施例與圖1A到圖1D中所說明的實施例之間的差異在於，多個通孔160a可以形成於密封體160上，通孔160a從密封體160的表面160b延伸到基板130的表面130c，以暴露出基板130的至少一部分，以便在電路載體110上形成密封體160之後形成封裝結構20，如圖1D中所示。
舉例來說，可以透過雷射剝離(laser ablation)、雷射鑽孔、機械鑽孔或其它合適的方法移除密封體160以形成通孔160a。本發明並不限制通孔160a的數目。此外，舉例來說，可以透過雷射的功率(power)、雷射的移動速度和/或其它製程參數(processing factors)來控制通孔160a中的每一個的深度D2。在一些實施例中，通孔160a中的每一個的深度D2可以等於基板130的表面130c與密封體160的最遠離電路載體110的表面160b之間的距離D3。在一些實施例中，通孔160a的一部分可以形成在對應於晶粒120的區域內。因為基板130提供隔板功能，因此在形成對應於晶粒120的區域內的通孔160a的部分時，晶粒120的可靠性可不受影響。
在一些實施例中，通孔160a可以與基板130的開口130a 錯開。因此，在密封體160上形成通孔160a時，導電線150可不受影響，藉此來確保基板130與電路載體110之間的電性連接。在一些實施例中，通孔160a可以對應於導電層130b而形成，藉以形成導電通孔。因此，通孔160a可以作為封裝結構20與外部連接器之間的導電路徑。此外，封裝結構20可以實現微間距(fine pitch)要求，且增加I/O連接的數目。因此，封裝結構20可以與高端裝置應用以及I/O連接的數目較多且每個晶粒的接墊間距較窄的高級前端技術節點(advanced front-end technology node)相容。
圖4為說明根據本發明的實施例的封裝結構的剖面示意圖。參考圖4，封裝結構30的製造方法類似於圖3中所說明的實施例的製造方法。本文中省略詳細描述。如圖4中所示，通孔160a可以用導電元件170填充，且半導體元件200可以堆疊於密封體160上，並且電性連接到基板130，以形成封裝結構30。
舉例來說，填充於通孔160a中的導電元件170可以形成為導電凸塊、導電柱、導電接墊或其它導電連接器。在一些實施例中，可以透過將導電材料(例如，鋁、銅、鎳、金、銀、焊料或合金等)沉積於密封體160的表面160b上且經由蒸鍍(evaporation)、電鍍(electro-plating)、植球(ball drop)、網版印刷(screen printing)或其它合適的方法填充通孔160a來形成導電元件170。此外，導電材料可以經由微影以及蝕刻製程加以圖案化，以形成導電元件170。然而，本發明中不限制導電元件170 的材料以及其形成製程。因此，在用導電元件170填充通孔160a之後，導電元件170與電路載體110的導電結構118位於半導體封裝結構30的兩個相對的側邊上，因此增加I/O連接的數目。
在一些實施例中，可以透過膏體印刷製程(paste print process)來用焊料填充通孔160a，以實現球柵陣列(ball grid array，BGA)互連。在其它實施例中，通孔160a可以用來作為增層(build up)互連結構(例如導電元件170)，以進一步電性連接到半導體元件200。在其它實施例中，半導體元件200可以包含動態隨機存取記憶體(DRAM)、NAND快閃記憶體或其它合適的主動裝置，其不限於此。此外，半導體元件200可以進一步包含對應地耦接到例如導電元件170的多個導電結構202。此外，導電結構202可以是導電凸塊、導電柱或透過植球製程以及回焊製程形成的焊球。換句話說，半導體元件200可以堆疊於密封體160上，且經由導電元件170、基板130以及導電線150電性連接到電路載體110，以形成封裝結構30。
在一些實施例中，封裝結構30可以稱為堆疊封裝(package-on-package，POP)結構。因為基板130可以作為導電介面且通孔160a形成於密封體160上以暴露出基板130的至少一部分，故封裝結構可利於進一步的電性連接。因此，使得封裝結構更靈活以與不同裝置應用相容。
綜上所述，設置於晶粒上的基板不僅利於形成導電線，而且提供隔板功能，以防止在後續製程中損壞晶粒。此外，當在 通孔形成於密封體上，以暴露出基板的至少一部分時，導電線可以作為用於進一步電性連接的導電介面。因此，封裝結構可以實現微間距要求，並且增加I/O連接的數目，故使得封裝結構更靈活以與不同裝置應用相容。據此，可以較低製造成本開啟各種封裝設計的可能性。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。

Claims (10)

  1. 一種封裝結構製造方法，包括：設置晶粒於電路載體上；設置基板於所述晶粒上，其中所述基板包括多個開口；形成穿過所述基板的所述開口的多根導電線，以在所述基板與所述電路載體之間形成電性連接；形成密封體在所述電路載體上，以密封所述晶粒、所述基板以及所述導電線；以及形成多個導電元件，埋設在所述密封體中並設置在所述基板上以電性連接所述基板，其中所述導電元件與所述基板的所述開口錯開，且部分的所述導電元件與所述晶粒錯開。
  2. 如申請專利範圍第1項所述的封裝結構製造方法，其中所述導電線中的每一者包括連接到所述電路載體的第一區段、連接到所述基板的第二區段以及連接於所述第一區段與所述第二區段之間的中心區段，所述第一區段形成於所述基板下方，所述第二區段形成於所述基板上方，且所述中心區段形成於對應的所述基板的所述開口中的任一者內。
  3. 如申請專利範圍第1項所述的封裝結構製造方法，還包括：形成多個通孔在所述密封體上，以暴露出所述基板的至少一部分。
  4. 如申請專利範圍第3項所述的封裝結構製造方法，其中所述通孔的深度為所述基板的最遠離所述電路載體的表面與所述密封體的最遠離所述電路載體的表面之間的距離。
  5. 如申請專利範圍第3項所述的封裝結構製造方法，還包括：用所述導電元件填充所述通孔；以及設置半導體元件於所述密封體上，且經由所述通孔將所述半導體元件電性連接到所述基板。
  6. 一種封裝結構，包括：電路載體；基板，設置於所述電路載體上，其中所述基板包括多個開口；晶粒，設置於所述電路載體與所述基板之間；多根導電線，穿過所述基板的所述開口，以電性連接在所述基板與所述電路載體之間；密封體，設置於所述電路載體上，其中所述密封體密封所述晶粒、所述基板以及所述導電線；以及多個導電元件，埋設在所述密封體中並設置在所述基板上以電性連接所述基板，其中所述導電元件與所述基板的所述開口錯開，且部分的所述導電元件所述晶粒錯開。
  7. 如申請專利範圍第6項所述的封裝結構，其中所述導電線中的每一者包括連接到所述電路載體的第一區段、連接到所述基板的第二區段以及連接於所述第一區段與所述第二區段之間的中心區段，所述第一區段設置於所述基板下方，所述第二區段設置於所述基板上方，且所述中心區段設置於對應的所述基板的所述開口中的任一者內。
  8. 如申請專利範圍第6項所述的封裝結構，其中所述密封體包括暴露出所述基板的至少一部分的多個通孔。
  9. 如申請專利範圍第8項所述的封裝結構，其中所述通孔的深度為所述基板的最遠離所述電路載體的表面與所述密封體的最遠離所述電路載體的表面之間的距離。
  10. 如申請專利範圍第8項所述的封裝結構，其中所述密封體包括設置於所述通孔中的所述導電元件，所述封裝結構還包括設置於所述密封體上的半導體元件，其中所述半導體元件經由所述通孔電性連接到所述基板。
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