TW201828370A - 形成堆疊式封裝結構的方法 - Google Patents

形成堆疊式封裝結構的方法 Download PDF

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Publication number
TW201828370A
TW201828370A TW106122989A TW106122989A TW201828370A TW 201828370 A TW201828370 A TW 201828370A TW 106122989 A TW106122989 A TW 106122989A TW 106122989 A TW106122989 A TW 106122989A TW 201828370 A TW201828370 A TW 201828370A
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semiconductor package
substrate
package
conductive
metal bumps
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TW106122989A
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English (en)
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徐宏欣
王啓安
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力成科技股份有限公司
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Publication of TW201828370A publication Critical patent/TW201828370A/zh

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Abstract

本發明揭露一種形成堆疊式封裝結構的方法。對第一半導體封裝體的模封複合物進行雷射鑽孔，以在模封複合物內形成多個貫穿孔。導電層形成於模封複合物上，以使模封複合物被導電物質所覆蓋，且使上述的多個貫穿孔被導電物質所填充。導電層被研磨後，會暴露出模封複合物。第二半導體封裝體堆疊在第一半導體封裝體上，以使第二半導體封裝體的多個金屬凸塊與填充於多個貫穿孔內的導電物質接觸。

Description

形成堆疊式封裝結構的方法
本發明係有關於一種封裝的方法，尤指一種形成堆疊式封裝（package-on-package；POP）結構的方法。
堆疊式封裝（POP）是目前成長最快速的半導體封裝技術，這是因為對於整合在單一封裝體中的高密度系統來說，堆疊式封裝是個具有高度成本效益的方案。在堆疊式封裝結構中，多種的封裝體被整合在單一封裝體中，以減少其尺寸。先前技術中的堆疊式封裝結構通常使用銲球、銲柱或銅柱，並藉由表面黏著技術（surface mount technology；SMT）或迴焊製程（reflow process），以連接第一封裝體與第二封裝體。多個封裝體可因此被整合成單一封裝體，以縮小這些封裝體的尺寸並降低其電路的複雜度。然而，減少封裝體的厚度仍舊是困難的。由於堆疊式封裝結構至少包含了兩個彼此堆疊的封裝體，故共通的問題是堆疊式封裝結構的厚度會因此而太厚而難以被薄化。對於諸如行動裝置的應用，尺寸太大的堆疊式封裝結構將會難以嵌入到一個小裝置內。因此，對本領域來說，亟需一種可減少封裝結構之厚度的方案。
本發明的一實施例提供一種形成一堆疊式封裝（package-on-package；POP）結構的方法。上述的方法包含對第一半導體封裝體的模封複合物（mold compound）進行雷射鑽孔，以在模封複合物內形成多個貫穿孔（through hole）；在模封複合物上形成導電層，以使模封複合物被導電物質所覆蓋，並使導電物質填充於上述多個貫穿孔內；研磨導電層，以暴露模封複合物；以及將一第二半導體封裝體堆疊在第一半導體封裝體，以使第二半導體封裝體的多個金屬凸塊與填充於上述多個貫穿孔內的導電物質接觸。
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。
依據本發明的第一實施例，一種形成堆疊式封裝結構的方法舉例說明於第1圖至第6圖之元件截面示意圖。
如第1圖所示，提供了第一半導體封裝體100。第一半導體封裝體100包含第一晶片（die）110、模封複合物（mold compound）120、多個導電墊（conductive pad）132、基板140以及多個金屬凸塊（metal bump）150。第一晶片110與導電墊132係設置於基板140上且被模封複合物120所包覆。金屬凸塊150形成於基板140之下。在此實施例中，第一半導體封裝體100是一個覆晶封裝體（flip-chip package），然而本發明並不以此為限。第一晶片110可具有多個柱狀凸塊（pillar bump）112，柱狀凸塊112係設置於基板140上並電性連接到部分的金屬凸塊150。柱狀凸塊112作為第一晶片110的輸入/輸出介面。基板140可包含墊遮罩層（pad mask layer）130以及多個導電柱142。導電柱142形成在基板140內並貫穿基板140。部分的金屬凸塊150藉由導電柱142電性連接到導電墊132。在此實施例中，第一半導體封裝體100也可以是一個扇出型封裝體（fan-out package）。
如第2圖所示，可對模封複合物120進行雷射鑽孔，以在模封複合物120內形成多個貫穿孔（through hole）122，進而使導電墊132暴露在貫穿孔122的底部。模封複合物120可以是環氧樹脂模製化合物（epoxy molding compound）。
如第3圖所示，導電層160可形成在模封複合物120上，以使模封複合物120被一導電物質所覆蓋，並使貫穿孔122被上述的導電物質所填充。上述的導電物質可以是銅、金或金銅合金。其中，可藉由將上述導電物質濺鍍或電鍍在模封複合物120上的方式，而在模封複合物120上形成導電層160。
如第4圖所示，可研磨導電層160，以暴露模封複合物120。藉此，填充於貫穿孔122內的導電物質形成了多個貫穿導孔（through hole via；THV）160A。貫穿導孔160A可與導電墊132接觸，而每一貫穿導孔160A的高度H可介於200微米至300微米之間，且兩相鄰貫穿導孔160A的底部之間的距離D可小於300微米。在本發明另一實施例中，當研磨導電層160時，可同時地研磨模封複合物120。由於導電層160與模封複合物120可被研磨，故可減少第一半導體封裝體100的厚度。在本發明另一實施例中，第一半導體封裝體100的基板140可在貫穿導孔160A形成後被移除，而如此一來，可進一步地減少第一半導體封裝體100的厚度。
如第5圖及第6圖所示，第二半導體封裝體200堆疊在第一半導體封裝體100上。當第二半導體封裝體200堆疊在第一半導體封裝體100上時，第二半導體封裝體200的多個金屬凸塊250可與貫穿導孔160A接觸。第二半導體封裝體200的金屬凸塊250可藉由執行一迴焊程序（reflow soldering process）而接合於貫穿導孔160A的暴露表面。其結果，第一半導體封裝體100與第二半導體封裝體200可整合成堆疊式封裝（POP）結構300。由於貫穿孔122可藉由執行雷射鑽孔而形成，故堆疊式封裝結構300可以是一個微間距的(fine pitch)封裝體。
在本實施例中，第二半導體封裝體200可以是一個扇出型封裝體及/或覆晶封裝體，然而本發明並不以此為限。第二半導體封裝體200包含第二晶片210、模封複合物220、基板240以及多個金屬凸塊250。第二晶片210設置於基板240上並被模封複合物220所包覆。多個金屬凸塊250形成於基板240之下。第二晶片210藉由第二半導體封裝體200的金屬凸塊250、貫穿導孔160A以及基板140的導電電路，而電性連接到第一半導體封裝體100部分的金屬凸塊150。第二晶片210包含多個柱狀凸塊212。導電柱242設置於基板240內並電性連接到金屬凸塊250。
依據本發明的第二實施例，另一種形成堆疊式封裝結構的方法舉例說明於第7圖至第12圖之元件截面示意圖。其中，第一實施例與第二實施例中所使用的相同元件符號係表示相同的元件。
如第7圖所示，依據本發明第二實施例，提供了第一半導體封裝體400。兩第一半導體封裝體100與400之間最大的不同點在於第7圖中的第一晶片110係藉由打線（wire bonding）的方式而耦接於基板140。其中，第一晶片110藉由多條接合接線（bonding wire）114而電性連接到形成在基板140中的電路。上述形成在基板140中的電路係電性連接到部分的金屬凸塊150。
如第8圖所示，可對模封複合物120進行雷射鑽孔，以在模封複合物120內形成多個貫穿孔122，進而使導電墊132暴露在貫穿孔122的底部。
如第9圖所示，導電層160可形成在模封複合物120上，以使模封複合物120被一導電物質所覆蓋，並使貫穿孔122被上述的導電物質所填充。
如第10圖所示，可研磨導電層160，以暴露模封複合物120。藉此，填充於貫穿孔122內的導電物質形成了多個貫穿導孔160A。貫穿導孔160A可與導電墊132接觸，而每一貫穿導孔160A的高度H可介於200微米至300微米之間，且兩相鄰貫穿導孔160A的底部之間的距離D可小於300微米。在本發明另一實施例中，當研磨導電層160時，可同時地研磨模封複合物120。由於導電層160與模封複合物120可被研磨，故可減少第一半導體封裝體400的厚度。
如第11圖及第12圖所示，第二半導體封裝體200堆疊在第一半導體封裝體400上。當第二半導體封裝體200堆疊在第一半導體封裝體400上時，第二半導體封裝體200的多個金屬凸塊250可與貫穿導孔160A接觸。第二半導體封裝體200的金屬凸塊250可藉由執行一迴焊程序而接合於第一半導體封裝體40的貫穿導孔160A。其結果，第一半導體封裝體400與第二半導體封裝體200可整合成堆疊式封裝結構500。
綜上所述，藉由進行雷射鑽孔，可以在模封複合物內形成多個貫穿孔，而貫穿孔可填充導電物質以形成多個貫穿導孔。兩相鄰貫穿導孔的底部之間的距離可小於300微米，而使所形成的堆疊式封裝結構可以是一個微間距的封裝體。此外，導電層與模封複合物可被研磨，且第一半導體封裝體的基板可在貫穿導孔形成後被移除。因此，可減少堆疊式封裝結構的厚度。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100、400‧‧‧第一半導體封裝體
110‧‧‧第一晶片
112、212‧‧‧柱狀凸塊
114‧‧‧接合接線
120、220‧‧‧模封複合物
122‧‧‧貫穿孔
130‧‧‧墊遮罩層
132‧‧‧導電墊
140、240‧‧‧基板
142、242‧‧‧導電柱
150、250‧‧‧金屬凸塊
160‧‧‧導電層
160A‧‧‧貫穿導孔
200‧‧‧第二半導體封裝體
210‧‧‧第二晶片
300、500‧‧‧堆疊式封裝結構
D‧‧‧距離
H‧‧‧高度
第1圖至第6圖是依據本發明的第一實施例而繪示的一種形成堆疊式封裝結構的方法之對應步驟的元件截面示意圖。 第7圖至第12圖是依據本發明的第二實施例而繪示的一種形成堆疊式封裝結構的方法之對應步驟的元件截面示意圖。

Claims (10)

  1. 一種形成一堆疊式封裝（package-on-package；POP）結構的方法，包含： 對一第一半導體封裝體的一模封複合物（mold compound）進行雷射鑽孔，以在該模封複合物內形成多個貫穿孔（through hole）； 在該模封複合物上形成一導電層，以使該模封複合物被一導電物質所覆蓋，並使該導電物質填充於該些貫穿孔內； 研磨該導電層，以暴露該模封複合物；以及 將一第二半導體封裝體堆疊在該第一半導體封裝體，以使該第二半導體封裝體的多個金屬凸塊與填充於該些貫穿孔內的該導電物質接觸。
  2. 如請求項第1項所述之方法，其中在該模封複合物上形成該導電層包括以濺鍍或電鍍的方式將該導電物質形成在該模封複合物上。
  3. 如請求項第1項所述之方法，其中該第一半導體封裝體包含一第一晶片以及一第一基板，一電路形成在該第一基板內，而該第一晶片藉由多條接合接線（bonding wire）電性連接到該電路。
  4. 如請求項第1項所述之方法，其中該第一半導體封裝體包含一第一晶片、一第一基板以及多個導電墊，該第一晶片設置於該第一基板上且被該模封複合物所包覆，而在對該模封複合物進行完雷射鑽孔後，該些導電墊暴露於該些貫穿孔的底部。
  5. 如請求項第4項所述之方法，其中該第一半導體封裝體另包含形成在該第一基板內的多個導電柱以及形成在該第一基板之下的多個金屬凸塊，而該些導電墊藉由該些導電柱電性連接到該第一半導體封裝體的該些金屬凸塊中的部分的金屬凸塊。
  6. 如請求項第1項所述之方法，其中該第二半導體封裝體包含一第二晶片，第一半導體封裝體包含一第一晶片、一第一基板、多個導電柱以及多個金屬凸塊，該第一晶片設置於該第一基板上且被該模封複合物所包覆，該些導電柱形成於該第一基板內，該第一半導體封裝體的該些金屬凸塊形成於該第一基板之下，填充於該些貫穿孔內的該導電物質形成多個貫穿導孔（through hole via；THV），而該第二晶片藉由該第二半導體封裝體的該些金屬凸塊、該些貫穿導孔以及該些導電柱電性連接到該第一半導體封裝體的該些金屬凸塊中的部分金屬凸塊。
  7. 如請求項第6項所述之方法，其中該第二半導體封裝體另包含多個柱狀凸塊，電性連接到該第二半導體封裝體的該些金屬凸塊。
  8. 如請求項第6項所述之方法，其中該第二半導體封裝體另包含一第二基板，該第二晶片設置於該第二基板上，而該第二半導體封裝體的該些金屬凸塊形成於該第二基板之下。
  9. 如請求項第1項所述之方法，其中該第一半導體封裝體及/或該第二半導體封裝體是覆晶封裝體（flip-chip package）。
  10. 如請求項第1項所述之方法，其中該第一半導體封裝體及/或該第二半導體封裝體是扇出型封裝體（fan-out package）。
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