TWI733056B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TWI733056B
TWI733056B TW107132963A TW107132963A TWI733056B TW I733056 B TWI733056 B TW I733056B TW 107132963 A TW107132963 A TW 107132963A TW 107132963 A TW107132963 A TW 107132963A TW I733056 B TWI733056 B TW I733056B
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Taiwan
Prior art keywords
layer
opening
protective layer
circuit
electronic package
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TW107132963A
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English (en)
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TW202013634A (zh
Inventor
葉育瑋
林彥宏
廖芷苡
邱志賢
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矽品精密工業股份有限公司
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Priority to TW107132963A priority Critical patent/TWI733056B/zh
Priority to CN201811136514.4A priority patent/CN110931450B/zh
Priority to US16/196,503 priority patent/US10818515B2/en
Publication of TW202013634A publication Critical patent/TW202013634A/zh
Application granted granted Critical
Publication of TWI733056B publication Critical patent/TWI733056B/zh

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

一種電子封裝件及其製法，係於配置有電子元件之承載結構上形成保護層，再以包覆層包覆該電子元件與該保護層，接著於該包覆層形成穿孔，並使該穿孔延伸貫穿該保護層，以令該承載結構之部分表面外露於該穿孔，之後將導電結構形成於該穿孔中以電性連接該承載結構，俾藉由該保護層之設計，以於形成該穿孔時，該保護層之緩衝效果可防止雷射直接連續燒穿該包覆層與該保護層，避免損壞該承載結構。

Description

電子封裝件及其製法
本發明係有關一種半導體封裝技術，尤指一種電子封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。
目前貫穿膠體(Through molding via，簡稱TMV)之技術已廣泛運用於半導體封裝製程領域，其主要技術係利用雷射燒灼方式於封裝膠體表面進行開孔製程，以顯露出位於封裝膠體下之電性接點(如線路或電性連接墊)。
如第1A圖所示，一具有複數線路層101之封裝基板10係設於一支撐件1上，且該封裝基板10上設有一晶片11與一封裝膠體12，並使該封裝膠體12包覆該晶片11。接著，利用雷射鑽孔方式貫穿該封裝膠體12，以形成複數穿孔120，令部分該線路層101(即電性連接墊)外露於該穿孔120。之後，形成如銅之導電材於該穿孔120中，以作為外接點，俾製成半導體封裝件。最後，移除該支撐件1，以於後續製程中，該半導體封裝件藉由該些外接點接置 一如電路板或另一封裝件之電子裝置。
惟，習知穿孔120之製作方式中，雷射鑽孔方式不易控制功率與時間(於靠近該線路層101時需降低功率或減緩速度)，致使該線路層101容易燒壞(如第1B圖所示之線路層101之凹狀表面)，甚至燒穿該線路層101，造成後續所形成之導電材與該線路層101之間的電性連接不良，導致短路或斷路的問題，甚而降低封裝產品的可靠度。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑒於上述習知技術之缺失，本發明提供一種電子封裝件，係包括：承載結構，係具有外露之線路層；電子元件，係設於該承載結構上；保護層，係形成於該承載結構上以覆蓋該線路層；包覆層，係形成於該承載結構上且包覆該電子元件與該保護層，其中，該包覆層形成有穿孔，並使該穿孔延伸貫穿該保護層，以令該承載結構之部分表面外露於該穿孔；以及導電結構，係形成於該穿孔中且電性連接該承載結構之線路層。
本發明又提供一種電子封裝件之製法，係包括：設置電子元件於一具有線路層之承載結構上，且形成保護層於該承載結構上，並使該保護層覆蓋該線路層；以包覆層包覆該電子元件與該保護層；形成穿孔於該包覆層上，並使該穿孔延伸貫穿該保護層，以令該承載結構之部分表面外露於該穿孔；以及形成導電結構於該穿孔中，使該導電結 構電性連接該承載結構之線路層。
前述之電子封裝件之製法中，該穿孔之製程係包括：以第一雷射形成第一開孔於該包覆層上，使該保護層外露於該第一開孔；以及以第二雷射形成第二開孔於該保護層上，使該承載結構之第二側之部分表面外露於該第二開孔，以令該第一開孔與該第二開孔作為該穿孔。例如，該第一雷射之光強度係大於該第二雷射之光強度。
前述之電子封裝件及其製法中，該承載結構係為線路重佈層結構。
前述之電子封裝件及其製法中，該保護層係覆蓋該線路層之上表面及側面。或者，該保護層係覆蓋該線路層之上表面。
前述之電子封裝件及其製法中，該承載結構係為封裝基板。
前述之電子封裝件及其製法中，該包覆層之材質不同於該保護層之材質。
前述之電子封裝件及其製法中，該導電結構係為銲錫材料或導電柱。
前述之電子封裝件及其製法中，形成該保護層之材質係為非金屬材。例如，該非金屬材係為防銲層、底膠或兩者組合。
前述之電子封裝件及其製法中，復包括形成於該包覆層上之線路結構，其電性連接該導電結構。進一步，又包括形成於該線路結構上之複數導電元件。
由上可知，本發明之電子封裝件及其製法，主要藉由該保護層之設計，以於形成該穿孔時，先使用第一雷射移除該包覆層，再使用第二雷射移除該保護層，故相較於習知技術，本發明之製法藉由該保護層之緩衝效果，可防止該第一雷射直接連續燒穿該包覆層與該保護層，以避免損壞該承載結構，進而提升該電子封裝件的可靠度。
1:支撐件
10:封裝基板
101:線路層
11:晶片
12:封裝膠體
120,250:穿孔
2,3,4:電子封裝件
2a:封裝組合
20:承載結構
20a:第一側
20b:第二側
200,200’:第一介電層
201,201’,201”:第一線路層
201a:上表面
201c:側面
21,21’:第一電子元件
21a,22a:作用面
21b,22b:非作用面
210,27:導電凸塊
22:第二電子元件
220:電極墊
23,33:導電結構
24,44:封裝層
25:包覆層
251:第一開孔
252:第二開孔
28:保護層
280:開口
36:線路結構
360:第二介電層
361:第二線路層
37:導電元件
F:第一雷射
L:第二雷射
第1A圖係為習知半導體封裝件於製程中之剖面示意圖。
第1B圖係為第1A圖之局部放大圖。
第2A至2F圖係為本發明之電子封裝件之製法的剖面示意圖。
第2B’及2B”圖係為第2B圖之不同實施例。
第3圖係為第2F圖之另一實施例的剖面示意圖。
第4圖係為第3圖之另一實施例的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功 效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示，提供一封裝組合2a，其包含一承載結構20、至少一第一電子元件21,21’及一封裝層24。
於本實施例中，該封裝組合2a之製作方式繁多，並無特別限制。
所述之承載結構20係具有相對之第一側20a與第二側20b，其包括至少一第一介電層200及結合該第一介電層200之第一線路層201,201’,201”。例如，以線路重佈層(redistribution layer，簡稱RDL)之製作方式形成無核心層(coreless)結構，其由該第一線路層201,201’,201”與該第一介電層200構成，其中，形成該第一線路層201,201’,201”之材質係為銅，且形成該第一介電層200之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。應可理解地，該承載結構20亦可為其它可供承載如晶片等電子元件之承載單元，並不限於上述。
所述之第一電子元件21,21’係結合於該承載結構20 之第一側20a上。於本實施例中，該第一電子元件21,21’係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，若該第一電子元件21係為半導體晶片，其具有相對之作用面21a與非作用面21b，該作用面21a係以覆晶方式(如圖所示之導電凸塊210)電性連接該第一線路層201’；或者，該第一電子元件21亦可藉由複數銲線(圖略)以打線方式電性連接該第一線路層201’；亦或，該第一電子元件21可直接接觸該第一線路層201’。若該第一電子元件21’係為被動元件，其可藉由導電凸塊210電性連接該第一線路層201’。然而，有關該第一電子元件21,21’電性連接線路層之方式不限於上述。
所述之封裝層24係形成於該承載結構20之第一側20a上，以包覆該些第一電子元件21,21’。具體地，該封裝層24係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)環氧樹脂之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該承載結構20之第一側20a上。
另外，該封裝層24係覆蓋該第一電子元件21之非作用面21b。應可理解地，亦可依需求，使該封裝層44之外表面齊平該第一電子元件21之非作用面21b，以令該第一電子元件21之非作用面21b外露出該封裝層44，如第4圖所示。
如第2B圖所示，設置至少一第二電子元件22於該承載結構20之第二側20b上，且形成一保護層28於該承載結構20之第二側20b上。
於本實施例中，該第二電子元件22係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該第二電子元件22係為半導體晶片，其具有相對之作用面22a與非作用面22b，且該作用面22a具有複數電極墊220，使該第二電子元件22以其電極墊220藉由覆晶方式(如圖所示之導電凸塊27)電性連接該第一線路層201”；或者，該第二電子元件22亦可藉由複數銲線(圖略)以打線方式電性連接該第一線路層201”；亦或，該第二電子元件22可直接接觸該第一線路層201”。然而，有關該第二電子元件22電性連接線路層之方式不限於上述。
再者，可先於該承載結構20之第二側20b上形成一如防銲層(如綠漆)、底膠或兩者組合之非金屬材，以作為保護層28，再移除部分保護層28以形成一開口280，使該開口280外露出部分該承載結構20之第二側20b，再設置該第二電子元件22於該開口280中，以令該第二電子元件22電性連接該第一線路層201”。或者，可直接以圖案化模壓方式形成保護層28於該承載結構20之第二側20b之部分第一線路層201上，而不需形成該開口280。
又，該保護層28係覆蓋該第一線路層201之上表面201a及側面201c。於另一實施例中，如第2B’圖所示， 該保護層28僅覆蓋該第一線路層201之上表面201a。於其它實施例中，如第2B”圖所示，該第一線路層201,201”,201’可嵌埋於該第一介電層200’中，且該保護層28形成於該第一介電層200’之部分表面上以覆蓋該第一線路層201之上表面201a。
另外，該第一電子元件21之作用面21a與該第二電子元件22之作用面22a係面對面配置。
如第2C圖所示，形成一包覆層25於該承載結構20之第二側20b上，以令該包覆層25包覆該第二電子元件22、該導電凸塊27與該保護層28。
於本實施例中，該包覆層25係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)環氧樹脂之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該承載結構20之第二側20b上，且該包覆層25之材質不同於該保護層28之材質。
再者，該包覆層25之材質與該封裝層24之材質可相同或不相同。
另外，可依需求藉由整平製程，如研磨方式，使該包覆層25之外表面齊平該第二電子元件22之非作用面22b，以令該第二電子元件22之非作用面22b外露出該包覆層25。
如第2D圖所示，以第一雷射F形成第一開孔251於該包覆層25上，使該保護層28外露於該第一開孔251。
於本實施例中，該第一雷射F可藉由時間控制，使其不會燒灼至該保護層28，或即使燒灼至該保護層28，亦不會貫穿該保護層28。
如第2E圖所示，以第二雷射L形成第二開孔252於該保護層28上，使該承載結構20之第二側20b之第一線路層201之部分表面外露於該第二開孔252，以令該第一開孔251與該第二開孔252作為穿孔250，而使該承載結構20之第二側20b之第一線路層201之部分表面外露於該穿孔250。
於本實施例中，該第一雷射F之光強度係大於該第二雷射L之光強度，因而易於控制該第二雷射L之燒灼程度，故可令該第二雷射L貫穿該保護層28而不會燒灼該第一線路層201。
再者，該第一開孔251之壁面與該第二開孔252之壁面係形成一連續面。
如第2F圖所示，例如以電鍍或沉積方式，形成導電結構23於該穿孔250中，且該導電結構23電性連接該第一線路層201，以製成電子封裝件2。
於本實施例中，該導電結構23係為銲錫材料，其作為外接點，以於後續製程中，該電子封裝件2藉由該些外接點接置至少一如電路板、封裝結構或其它結構(如另一封裝件或晶片)之電子裝置(圖略)。
於另一實施例中，該導電結構33係為如銅柱之金屬柱，如第3圖所示。例如，可將金屬材形成於該包覆層25上以作為第二線路層361，且一併將該金屬材形成於該穿孔250中以作為該導電結構33，使該第二線路層361電性連接該些導電結構33及接觸該第二電子元件22之非作用面22b。進一步，可依需求於該包覆層25與該第二線路層361上形成第二介電層360，且該第二介電層360外露出部分該第二線路層361，使該第二線路層361與該第二介電層360作為線路結構36，以於後續製程中，形成複數如銲球之導電元件37於該第二線路層361上，俾供後續接置至少一如電路板、封裝結構或其它結構(如另一封裝件或晶片)之電子裝置(圖略)。
因此，本發明之製法係藉由該保護層28覆蓋部分該第一線路層201之設計，以於形成該穿孔250時，先使用高強度第一雷射F移除該包覆層25，再使用低強度之第二雷射L移除該保護層28，故相較於習知技術，本發明之製法藉由該保護層28之緩衝效果，能防止該第一雷射F直接連續燒穿該包覆層25與該保護層28，以避免損壞該第一線路層201。
再者，由於該第一雷射F無需考量燒灼該第一線路層201之情事，因而無需於靠近該第一線路層201時減緩速度，故可輕易移除該包覆層25，以加快該第一雷射F之鑽孔作業。
又，由於該保護層28之材質選用(不同於該包覆層25)，使該第二雷射L能快速移除該保護層28，故能加快雷射鑽孔之速度。
另外，該承載結構20之第一側亦可省略封裝製程，如第3圖所示，即無需配置該第一電子元件21與封裝層24。
本發明係提供一種電子封裝件2,3,4，其包括：一承載結構20、一第二電子元件22、一保護層28、一包覆層25以及一導電結構23,33。進一步，該電子封裝件2,4可包括至少一第一電子元件21,21’及一封裝層24,44。
所述之承載結構20係具有相對之第一側20a與第二側20b。
所述之第二電子元件22係設於該承載結構20之第二側20b上。
所述之保護層28係形成於該承載結構20之第二側20b上。
所述之包覆層25係形成於該承載結構20之第二側20b上，以包覆該第二電子元件22與該保護層28，其中，該包覆層25上形成有至少一穿孔250，並使該穿孔250延伸貫穿該保護層28，以令該承載結構20之第二側20b之部分表面外露於該穿孔250。
所述之導電結構23,33係形成於該穿孔250中且電性連接該承載結構20。
所述之第一電子元件21,21’係結合於該承載結構20之第一側20a上。
所述之封裝層24,44係形成於該承載結構20之第一側20a上，以令該封裝層24,44包覆該第一電子元件21,21’。
於一實施例中，該承載結構20係具有第一線路層 201,201’,201”，以電性連接該第一電子元件21、第二電子元件22及導電結構23,33。例如，該保護層28係覆蓋該第一線路層201之上表面201a及側面201c。
於一實施例中，該承載結構20係為封裝基板。
於一實施例中，該第二電子元件22之非作用面22b外露於該包覆層25之表面。
於一實施例中，該包覆層25之材質不同於該保護層28之材質。
於一實施例中，形成該保護層28之材質係為非金屬材，例如為防銲層、底膠或兩者組合。
於一實施例中，該導電結構23,33係為銲錫材料或導電柱。
於一實施例中，所述之電子封裝件3復包括形成於該包覆層25上之線路結構36，其電性連接該導電結構33。例如，該第二電子元件22係接觸該線路結構36。進一步，該電子封裝件3又包括形成於該線路結構36上之複數導電元件37。
綜上所述，本發明之電子封裝件及其製法，係藉由該保護層之設計，以於形成該穿孔時，能防止該第一雷射直接連續燒穿該包覆層與該保護層，故能避免損壞該第一線路層之情況發生，因而能提升該電子封裝件的可靠度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20‧‧‧承載結構
20a‧‧‧第一側
20b‧‧‧第二側
201,201’,201”‧‧‧第一線路層
21,21’‧‧‧第一電子元件
22‧‧‧第二電子元件
23‧‧‧導電結構
24‧‧‧封裝層
25‧‧‧包覆層
250‧‧‧穿孔
251‧‧‧第一開孔
252‧‧‧第二開孔
27‧‧‧導電凸塊
28‧‧‧保護層

Claims (16)

  1. 一種電子封裝件，係包括：承載結構，係具有外露之線路層；電子元件，係設於該承載結構上；保護層，係接觸形成於該承載結構上以覆蓋該線路層，該保護層係覆蓋該線路層之上表面及側面，其中，形成該保護層之材質係為非金屬材，且該保護層上形成有第二開孔，以令該承載結構之部分表面外露於該第二開孔；包覆層，係形成於該承載結構上且包覆該電子元件與該保護層，其中，該包覆層之材質不同於該保護層之材質，且該包覆層形成有對應第二開孔之第一開孔，使該第一開孔與該第二開孔作為穿孔，以令該承載結構之部分表面外露於該穿孔，且該第二開孔不會大於第一開孔；以及導電結構，係形成於該穿孔中且電性連接該承載結構之線路層。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該承載結構係為線路重佈層結構。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該承載結構係為封裝基板。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該非金屬材係為防銲層、底膠或兩者組合。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該導 電結構係為銲錫材料或導電柱。
  6. 如申請專利範圍第1項所述之電子封裝件，復包括有形成於該包覆層上且電性連接該導電結構之線路結構。
  7. 如申請專利範圍第6項所述之電子封裝件，復包括有形成於該線路結構上之複數導電元件。
  8. 一種電子封裝件之製法，係包括：設置電子元件於一具有線路層之承載結構上，且形成保護層於該承載結構上，並使該保護層覆蓋該線路層，其中，該保護層係覆蓋該線路層之上表面及側面，且形成該保護層之材質係為非金屬材；以包覆層包覆該電子元件與該保護層，其中，該包覆層之材質不同於該保護層之材質；形成第一開孔於該包覆層上，使該保護層外露於該第一開孔；形成第二開孔於該保護層上，使該第一開孔與該第二開孔作為穿孔，以令該承載結構之部分表面外露於該穿孔；以及形成導電結構於該穿孔中，使該導電結構電性連接該承載結構之線路層。
  9. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該穿孔之製程係包括：以第一雷射形成該第一開孔於該包覆層上，使該保護層外露於該第一開孔；以及以第二雷射形成該第二開孔於該保護層上，使該 承載結構之部分表面外露於該第二開孔，以令該第一開孔與該第二開孔作為該穿孔。
  10. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該第一雷射之光強度係大於該第二雷射之光強度。
  11. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該承載結構係為線路重佈層結構。
  12. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該承載結構係為封裝基板。
  13. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該非金屬材係為防銲層、底膠或兩者組合。
  14. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該導電結構係為銲錫材料或導電柱。
  15. 如申請專利範圍第8項所述之電子封裝件之製法，復包括形成線路結構於該包覆層上，且該線路結構電性連接該導電結構。
  16. 如申請專利範圍第15項所述之電子封裝件之製法，復包括形成複數導電元件於該線路結構上。
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