TWI624020B - 電子封裝件及其製法 - Google Patents
電子封裝件及其製法 Download PDFInfo
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- H—ELECTRICITY
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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- H01L21/4814—Conductive parts
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Abstract
一種電子封裝件,係包括:絕緣層、嵌埋於該絕緣層中之電子元件、設於該絕緣層上之介電層、設於該介電層上並電性連接該電子元件之線路層、以及設於該介電層中並圍繞該線路層之止擋層,以令該止擋層作為切單過程中之對位標的,避免切割位置超出誤差範圍及產品損耗問題。本發明復提供該電子封裝件之製法。
Description
本發明係關於一種半導體封裝技術,特別是指一種晶圓級封裝技術。
隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求,係發展出晶圓級封裝(Wafer Level Packaging,簡稱WLP)的技術。
如第1A至1D圖,係為習知晶圓級半導體封裝件1之製法之剖面示意圖。
如第1A圖所示,形成一熱化離型膠層(thermal release tape)11於一承載件10上。
接著,置放複數半導體元件12於該熱化離型膠層11上,該些半導體元件12具有相對之作用面12a與非作用面12b,各該作用面12a上均具有複數電極墊120,且各該作用面12a黏著於該熱化離型膠層11上。
如第1B圖所示,形成一封裝膠體13於該熱化離型膠層11上,以包覆該半導體元件12。
如第1C圖所示,進行烘烤製程以硬化該封裝膠體13,而同時該熱化離型膠層11因受熱後會失去黏性,故可一併移除該熱化離型膠層11與該承載件10,以外露該半導體元件12之作用面12a。
如第1D圖所示,進行線路重佈層(Redistribution layer,簡稱RDL)製程,係形成一線路重佈結構14於該封裝膠體13與該半導體元件12之作用面12a上,令該線路重佈結構14電性連接該半導體元件12之電極墊120。
接著,形成一絕緣保護層15於該線路重佈結構14上,且該絕緣保護層15外露該線路重佈結構14之部分表面,以供結合如銲球之導電元件16。最後進行切單製程。
惟,習知半導體封裝件1之製法中,由於該線路重佈結構14上的絕緣保護層15會覆蓋於後續切單製程之切割道L上,故當進行切單製程時,需額外進行曝光、顯影及蝕刻等製程以移除該切割道L上的絕緣保護層15之材料,導致該半導體封裝件1之製作成本高,且該切割道L上易殘留該絕緣保護層15之材料,而影響切割品質。
再者,該絕緣保護層15的邊緣易造成切割時的誤認,因而造成良率上的損失及信賴性問題。
因此,如何克服上述習知技術的種種問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失,本發明係提供一種電子封裝件,係包括:絕緣層;電子元件,係嵌埋於該絕緣
層中;介電層,係形成於該絕緣層與該電子元件上,且該介電層具有相對之上、下表面與該上、下表面相鄰之側面;線路層,係形成於該介電層上並電性連接該電子元件;以及止擋層,係形成於該介電層中並圍繞該線路層,且該止擋層與該介電層之該側面之間並無線路層。
本發明亦提供一種電子封裝件之製法,係包括:提供一嵌埋有電子元件之絕緣層;形成介電層於該絕緣層上,且該介電層具有相對之上、下表面與該上、下表面相鄰之側面;以及形成電性連接該電子元件之線路層於該介電層上,且形成圍繞該線路層之止擋層於該介電層中,且該止擋層與該介電層之該側面之間並無線路層。
前述之電子封裝件及其製法中,該電子元件係外露於該絕緣層之第二側。
前述之電子封裝件及其製法中,該止擋層係為導體。
前述之電子封裝件及其製法中,該止擋層係為環形。
前述之電子封裝件及其製法中,該止擋層係電性連接該線路層之接地部。
前述之電子封裝件及其製法中,復包括形成增層結構於該介電層與該線路層上,且該止擋層復形成於該增層結構中。例如,該止擋層之縱剖面形狀係呈疊杯狀或柱狀。
由上可知,本發明之電子封裝件及其製法,係於該介電層中形成該止擋層,以令該止擋層作為切割路徑的對位標的,故相較於習知技術,本發明無需額外進行曝光、顯影及蝕刻等製程,因而能降低製作成本,且能避免切單製程之切割位置超出誤差範圍及良率不佳的問題。
再者,該止擋層亦可作為密封環結構,以阻擋水氣進入該介電層內部,而能避免該線路層氧化。
又,於該線路層的周圍形成該止擋層,以於切單過程
中或切單後受到外力碰撞時,該止擋層能阻擋外力向內延伸至該線路層,因而有效避免該線路層損毀,故能提升產品良率及產品之可靠度。
1‧‧‧半導體封裝件
11‧‧‧熱化離型膠層
12a,22a‧‧‧作用面
120,220‧‧‧電極墊
14‧‧‧線路重佈結構
16,26‧‧‧導電元件
200‧‧‧離形層
21,41‧‧‧止擋層
23‧‧‧絕緣層
23b‧‧‧第二側
240,250‧‧‧介電層
242,252‧‧‧導電盲孔
260‧‧‧凸塊底下金屬層
40‧‧‧穿孔
L‧‧‧切割道
10,20‧‧‧承載件
12‧‧‧半導體元件
12b,22b‧‧‧非作用面
13‧‧‧封裝膠體
15,253‧‧‧絕緣保護層
2,4‧‧‧電子封裝件
201‧‧‧結合層
22‧‧‧電子元件
23a‧‧‧第一側
24‧‧‧線路結構
241,251‧‧‧線路層
25‧‧‧增層結構
3‧‧‧電子裝置
S‧‧‧切割路徑
第1A至1D圖係為習知半導體封裝件之製法之剖面示意圖;以及第2A至2D圖係為本發明之電子封裝件之製法之剖面示意圖;第2E圖係為第2D圖之後續製程之剖面示意圖;第3A圖係為第2B圖之另一實施例之局部放大圖;第3B圖係為第2B圖之局部上視圖;以及第4A至4B圖係為本發明之電子封裝件之製法之另一實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如
“上”、“第一”、“第二”、及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
請參閱第2A至2D圖,係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示,提供一具有相對之第一側23a與第二側23b之絕緣層23,且該絕緣層23中嵌埋有至少一電子元件22。
於本實施例中,形成該絕緣層23之材質係為模封材(molding compound)、乾膜(dry film)、聚對二唑苯(Poly-p-Polybenzoxazole,簡稱PBO)、聚醯亞胺(polyimide,簡稱PI)Ajinomoto build-up film(ABF)、環氧樹脂(expoxy)或光阻材。
再者,該電子元件22係為主動元件、被動元件或其組合者,其中,該主動元件係為半導體晶片,而該被動元件係為電阻、電容及電感。例如,該電子元件22係為半導體晶片,其具有相對之作用面22a與非作用面22b,該作用面22a具有複數電極墊220,且該電子元件22之非作用面22b齊平該絕緣層23之第二側23b。應可理解地,於其它實施例中,該絕緣層23之第二側23b可覆蓋該電子元件22之非作用面22b;或者,該電子元件22倒置,即該電子元件22之非作用面22b外露該絕緣層23之第一側23a,且該絕緣層23之第二側23b齊平或覆蓋該作用面22a。
又,該絕緣層23與該電子元件22之製作方式繁多,例如,該絕緣層23係以鑄模成型(molding)或壓合(Laminate)方式形成者,但並不限於此方式。具體地,可先將複數電子元件22設於支撐件(圖略)上,再形成用以包覆該些電子元件22之絕緣層23,之後將該絕緣層23之第二側23b結合於一承載件20上,才移除該支撐件。或者,先將複數電子元件22以其非作用面22b設於該承載件20上,再形成用以包覆該些電子元件22之絕緣層23。
另外,該承載件20上可依序形成有一離形層200與一結合層201,使該絕緣層23之第二側23b與該電子元件22之非作用面22b結合於該結合層201上。具體地,該離形層200係例如熱化離型膠(thermal release tape)、光感離形膜或機械離形結構,且該結合層201係如黏著材。
如第2B圖所示,進行線路重佈層(Redistribution layer,簡稱RDL)製程,以形成一線路結構24於該絕緣層23之第一側23a與該電子元件22上,且該線路結構24係電性連接該電子元件22,並形成一止擋層21於該線路結構24上。
於本實施例中,該線路結構24係包含一介電層240及設於該介電層240上之一線路層241,且該線路層241藉由延伸於該介電層240中之導電盲孔242電性連接至該電子元件22之電極墊220。
再者,該止擋層21係設於該介電層240中且貫穿該介電層240以接觸該絕緣層23之第一側23a,或如第3A圖
所示之該止擋層21未貫穿該介電層240,且該止擋層21係為導體,使其可與該線路層241一同製作;或者,該止擋層21與該線路層241不同製程製作。因此,該止擋層21之材質與該線路層241之材質可相同(如銅)或不相同。
又,該止擋層21之縱剖面形狀係為上寬下窄的形狀,如杯狀,但不限於上述。
另外,該止擋層21之整體平面形狀係為環形,如第3B圖所示,以圍繞該線路層241之周圍,且第3B圖所示之虛線係用以表示該電子元件22之平面輪廓。應可理解地,該止擋層21之輪廓與數量不限於第3B圖中所示,亦可為其它數量或其它形狀之輪廓。
如第2C圖所示,持續進行線路重佈層(RDL)製程,以形成一增層結構25於該線路結構24上,且該止擋層21復形成於該增層結構25中,並形成複數導電元件26於該增層結構25上。
於本實施例中,該增層結構25具有一絕緣保護層253、複數介電層250、形成於該些介電層250上之線路層251、及設於該些介電層250中的複數導電盲孔252,且藉由該些導電盲孔252電性連接該些線路層241,251,而該絕緣保護層253係形成於最外側之介電層250與線路層251上,以令該最外側之線路層251部分表面外露於該絕緣保護層253,俾供結合該些導電元件26於該線路層251外露之部分表面上。
再者,該止擋層21係設於該介電層250中,其可與該
線路層251一同製作,使該止擋層21之材質與該線路層251之材質可相同或不相同,且該些止擋層21所組成之縱剖面形狀係呈疊杯狀(即以窄端堆疊於寬端上)。
又,於製作該些線路層251及其同層之止擋層21時,下層的止擋層21可作為上層的線路層251與止擋層21之對位,以利於黃光製程(例如,圖案化該線路層251與導電盲孔252之製程)的進行。
另外,該導電元件26係為銲球、金屬凸塊或金屬柱等,且於形成該導電元件26前,可先於該線路層251外露之部分表面上形成凸塊底下金屬層(Under Bump Metallurgy,簡稱UBM)260,以利於結合該導電元件26。
如第2D圖所示,移除該承載件20、離形層200及該結合層201,使該電子元件22之非作用面22b係外露於該絕緣層23之第二側23b。之後,沿如第2C圖所示之切割路徑S進行切單製程,以完成該電子封裝件2之製作,故於後續製程中,如第2E圖所示,可將該電子封裝件2藉由該些導電元件26結合至一如電路板之電子裝置3上。
於本實施例中,該止擋層21可選擇性地電性連接該線路層241,251之接地部,以令該止擋層21作為電磁干擾(Electromagnetic Interference,簡稱EMI)之屏蔽(shielding)結構的接地使用。
於另一實施例中,如第4A至4B圖所示之電子封裝件4,其係先製作該線路結構24與該增層結構25(未形成該
絕緣保護層253),再貫穿各該介電層240,250以形成至少一穿孔40,之後形成填充材(如金屬材)於該穿孔40中以作為止擋層41,使該止擋層41貫穿該線路結構24與該增層結構25,或不貫穿線路結構24且其縱剖面形狀係呈柱狀。最後,形成該絕緣保護層253與導電元件26,並進行切單製程。
本發明之製法係於該介電層240,250中形成該止擋層21,41,以令該止擋層21,41作為切割路徑S的對位標的,故相較於習知技術,本發明之製法無需額外進行曝光、顯影及蝕刻等製程,因而能降低製作成本,且能避免切單製程之切割位置超出誤差範圍及良率損失的問題。
再者,該止擋層21,41亦可作為密封環結構,以阻擋水氣進入該介電層240,250內部,因而能避免該線路層241,251氧化。
又,於該線路層241,251的周圍形成該止擋層21,41,以於切單過程中或切單後受到外力碰撞時,藉由該止擋層21,41阻擋外力向內延伸至該線路層241,251,因而能避免該線路層241,251損毀,故能提升產品良率及產品之可靠度。
本發明提供一種電子封裝件2,4,係包括:一絕緣層23、一電子元件22、一介電層240、一線路層241以及一止擋層21,41。
所述之電子元件22係嵌埋於該絕緣層23中。
所述之介電層240係形成於該絕緣層23及該電子元件22上,且該介電層240具有相對之上、下表面與該上、下表面相鄰之側面。
所述之線路層241係形成於該介電層240上並電性連接該電子元件22。
所述之止擋層21,41係位於該介電層240中並圍繞該線路層241而為環形,且該止擋層21,41與該介電層240之該側面之間並無線路層241。
於一實施例中,該止擋層21,41係為導體。
於一實施例中,該止擋層21,41係電性連接該線路層241之接地部。
於一實施例中,所述之電子封裝件2,4復包括一增層結構25,其形成於該介電層240與該線路層241上,且該止擋層21,41復形成於該增層結構25之介電層250中。例如,該止擋層21之縱剖面形狀係呈疊杯狀、或該止擋層41之縱剖面形狀係呈柱狀。
綜上所述,本發明之電子封裝件及其製法,係藉由該止擋層之設計,以作為切割路徑的對位標的而能避免切單製程之切割位置超出誤差範圍及良率損失的問題,且能作為密封環結構,以阻擋水氣進入該介電層內部而避免該線路層氧化,並阻擋外力向內延伸至該線路層而避免損毀該線路層,故能提升產品良率及產品之可靠度。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
Claims (14)
- 一種電子封裝件,係包括:絕緣層;電子元件,係嵌埋於該絕緣層中;介電層,係形成於該絕緣層與該電子元件上,且該介電層具有相對之上、下表面與該上、下表面相鄰之側面;線路層,係形成於該介電層上並電性連接該電子元件;以及止擋層,係形成於該介電層中並圍繞該線路層,且該止擋層與該介電層之該側面之間並無線路層。
- 如申請專利範圍第1項所述之電子封裝件,其中,該止擋層係為導體。
- 如申請專利範圍第1項所述之電子封裝件,其中,該止擋層係為環形。
- 如申請專利範圍第1項所述之電子封裝件,其中,該止擋層係電性連接該線路層之接地部。
- 如申請專利範圍第1項所述之電子封裝件,復包括形成於該介電層與該線路層上之增層結構,且該止擋層復形成於該增層結構中。
- 如申請專利範圍第5項所述之電子封裝件,其中,該止擋層之縱剖面形狀係呈疊杯狀。
- 如申請專利範圍第5項所述之電子封裝件,其中,該止擋層之縱剖面形狀係呈柱狀。
- 一種電子封裝件之製法,係包括:提供一嵌埋有電子元件之絕緣層;形成介電層於該絕緣層上,且該介電層具有相對之上、下表面與該上、下表面相鄰之側面;以及形成電性連接該電子元件之線路層於該介電層上,且形成圍繞該線路層之止擋層於該介電層中,且該止擋層與該介電層之該側面之間並無線路層。
- 如申請專利範圍第8項所述之電子封裝件之製法,其中,該止擋層係為導體。
- 如申請專利範圍第8項所述之電子封裝件之製法,其中,該止擋層係為環形。
- 如申請專利範圍第8項所述之電子封裝件之製法,其中,該止擋層係電性連接該線路層之接地部。
- 如申請專利範圍第8項所述之電子封裝件之製法,復包括形成增層結構於該介電層與該線路層上,且該止擋層復形成於該增層結構中。
- 如申請專利範圍第12項所述之電子封裝件之製法,其中,該止擋層之縱剖面形狀係呈疊杯狀。
- 如申請專利範圍第12項所述之電子封裝件之製法,其中,該止擋層之縱剖面形狀係呈柱狀。
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