TWI736859B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TWI736859B
TWI736859B TW108109120A TW108109120A TWI736859B TW I736859 B TWI736859 B TW I736859B TW 108109120 A TW108109120 A TW 108109120A TW 108109120 A TW108109120 A TW 108109120A TW I736859 B TWI736859 B TW I736859B
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conductive
electronic component
item
patent application
electronic package
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TW108109120A
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TW202036808A (zh
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邱志賢
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矽品精密工業股份有限公司
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Priority to TW108109120A priority Critical patent/TWI736859B/zh
Priority to CN201910249759.6A priority patent/CN111725146A/zh
Priority to US16/533,751 priority patent/US10811378B2/en
Publication of TW202036808A publication Critical patent/TW202036808A/zh
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Publication of TWI736859B publication Critical patent/TWI736859B/zh

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    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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Abstract

一種電子封裝件，係將電子元件與複數電性連接該電子元件之導電柱嵌埋於封裝層中，其中，該導電柱之周面之寬度係小於該導電柱之兩端面之寬度，俾藉由該封裝層包覆該電子元件，以有效保護該電子元件，且提升產品之可靠度。本發明復提供該電子封裝件之製法。

Description

電子封裝件及其製法
本發明係有關一種半導體封裝製程，尤指一種電子封裝件及其製法。
隨著電子產業的發達，現今的電子產品已趨向輕薄短小與功能多樣化的方向設計，半導體封裝技術亦隨之開發出不同的封裝型態。為滿足半導體封裝結構之高積集度(Integration)以及微型化(Miniaturization)需求，除傳統打線式(Wire bonding)之半導體封裝技術外，亦可藉由覆晶(Flip chip)方式，以提升佈線密度。
第1圖係為習知覆晶式封裝結構1之剖視示意圖。如第1圖所示，主要將一半導體晶片13藉由複數銲錫凸塊130結合至一封裝基板10之線路層11之電性接觸墊110上並電性連接該線路層11之導電跡線111，再形成如封裝膠體或底膠之絕緣材14於該半導體晶片13與該封裝基板10之間，以包覆該些銲錫凸塊130。
惟，於封裝製程中，由於該半導體晶片13係以裸晶狀態(如晶背13b外露)於製程機台間進行運送，因而該半導體晶片13無任何保護， 容易造成該半導體晶片13發生缺角(chipping)與損毀問題，嚴重導致產品發生可靠度問題與龐大的財務損失。
再者，該封裝基板10之絕緣保護層12係形成有複數對應外露各該電性接觸墊110之開孔，故於該絕緣材14流入該半導體晶片13與該封裝基板10間時，容易導致該絕緣材14中具較大尺寸的填充料(filler)無法通過而產生氣室(void)，以致於後續製程中容易發生爆米花現象(Popcorn)，造成產品良率下降問題。
因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之缺失，本發明提供一種電子封裝件，係包括：至少一電子元件；複數導電結構，係設於該電子元件上且包含有導電柱，其中，該導電柱係具有相對之兩端面及鄰接該兩端面之周面，且該周面之寬度係小於該兩端面之寬度；以及一封裝層，係包覆該電子元件與該複數導電結構，且令該導電柱之一端面外露出該封裝層之外表面。
本發明復提供一種電子封裝件之製法，係包括：提供一導電架，其中，該導電架包含有一板體與複數連接該板體之導電柱，且該導電柱具有相對之兩端面及鄰接該兩端面之周面，且該周面之寬度係小於該兩端面之寬度；設置至少一電子元件於該導電架上，且令該複數導電柱之至少一部分與該電子元件結合；形成封裝層於該板體上，以令該封裝層包覆該電子元件與該複數導電柱；以及移除該板體，以令該導電柱之一端面外露出該封裝層之外表面。
前述之電子封裝件及其製法中，該導電柱係藉由導電體結合該電子元件，例如，該導電體係包含銲錫材料。進一步，該電子元件係藉由金屬部結合該導電體，例如，該金屬部係為銅柱。
前述之電子封裝件及其製法中，該導電柱之外露端面係低於或齊平該封裝層之外表面。
前述之電子封裝件及其製法中，該電子元件之部分表面係外露於該封裝層之外表面。
前述之電子封裝件及其製法中，復包括於移除該板體後，形成導電元件於該導電柱上，且該導電元件位於該封裝層之外表面上。
前述之電子封裝件及其製法中，該複數導電柱之其中一部分係未與該電子元件結合，以作為虛柱結構。例如，該虛柱結構係外露出該封裝層之外表面。
由上可知，本發明之電子封裝件及其製法，主要藉由該導電柱與該封裝層之設計，以令該封裝層包覆該電子元件之表面，使該電子元件能有效受到保護，故相較於習知技術，本發明之電子封裝件能提升產品之可靠度。
再者，本發明係以導電架取代習知封裝基板，因而無需形成絕緣保護層及用以對應外露各該電性接觸墊之開孔，故相較於習知技術，該封裝層能順利佈設而不會產生氣室，因而能避免於後續製程中發生爆米花現象。
1‧‧‧覆晶式封裝結構
10‧‧‧封裝基板
11‧‧‧線路層
110‧‧‧電性接觸墊
111‧‧‧導電跡線
13‧‧‧半導體晶片
13b‧‧‧晶背
130‧‧‧銲錫凸塊
14‧‧‧絕緣材
2,2’,3a,3b,3c,4a,4b‧‧‧電子封裝件
2a‧‧‧導電架
20‧‧‧金屬板
21‧‧‧電子元件
21a‧‧‧作用面
21b‧‧‧非作用面
21c‧‧‧側面
210‧‧‧電極墊
22‧‧‧導電體
22a,22a’‧‧‧導電凸塊
220‧‧‧金屬部
221‧‧‧銲錫部
23,33‧‧‧導電柱
23a,23b,33a‧‧‧端面
23c‧‧‧周面
24‧‧‧板體
240‧‧‧凹部
25,35‧‧‧封裝層
25a‧‧‧第一表面
25b,35b‧‧‧第二表面
25c‧‧‧側面
26,26’,36‧‧‧導電結構
27‧‧‧導電元件
28‧‧‧導電材料
3‧‧‧電路板
43‧‧‧虛柱結構
A‧‧‧垂直投影區域
d‧‧‧寬度
S‧‧‧切割路徑
第1圖係為習知覆晶式封裝結構之剖視示意圖。
第2A至2G圖係為本發明之電子封裝件之製法之剖視示意圖。
第2A’圖係為第2A圖之局部上視圖。
第2B’圖係為第2B圖之另一實施態樣之剖視示意圖。
第2C’及2C”圖係為第2C圖之其它不同實施態樣之局部剖視示意圖。
第2G’圖係為第2G圖之另一實施態樣之剖視示意圖。
第2H圖係為第2G圖之後續應用之剖視示意圖。
第3A至3C圖係為第2G圖之其它不同實施態樣之剖視示意圖。
第4A及4B圖係為第2G圖之其它不同實施態樣之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及 「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當視為本發明可實施之範疇。
第2A至2G圖係為本發明之電子封裝件2之製法之剖視示意圖。
如第2A圖所示，提供一導電架2a，其包含一板體24及複數形成於該板體24上之導電柱23，其中，該導電柱23具有相對之兩端面23a,23b及鄰接該兩端面23a,23b之周面23c，且該周面23c之寬度小於該兩端面23a,23b之寬度d。
於本實施例中，該導電柱23之周面23c係相對兩端面23a,23b呈凹狀，使該導電柱23呈蘋果核狀，且該板體24與導電柱23係一體成形。例如，利用蝕刻、雷射或其它適當方式移除一金屬板之部分材質，以形成該導電架2a。具體地，可經由蝕刻方式於該金屬板上形成底切型凹部240，藉以形成複數間隔相鄰的導電柱23，且令該導電柱23之周面23c呈內凹弧形。
再者，該導電柱23並未延伸有導電跡線，如第2A’圖所示，即沒有走線(routing)設計。
如第2B圖所示，形成導電材料28於該導電架2a之導電柱23之端面23b上。
於本實施例中，該導電材料28係如銲錫材料、錫膏、銅膏、銀膠或其它適當材料。
再者，該導電架2a與該導電材料28之製程順序可依需求調整。如第2B’圖所示，若該導電材料28不同於該導電架2a之材質，則可利用該導電材料28作為阻層，而形成於一金屬板20上，再利用蝕刻、雷射或 其它適當方式移除該金屬板20之部分材質，以令該金屬板20成為該導電架2a。
如第2C圖所示，設置至少一電子元件21於該導電柱23上之導電材料28上。
於本實施例中，該電子元件21係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該電子元件21係具有相對之作用面21a與非作用面21b，該作用面21a具有複數電極墊210，並以覆晶方式將其作用面21a結合於該導電材料28上以電性連接該導電柱23。
再者，該電子元件21之作用面21a之電極墊210上可先形成複數導電凸塊22a，如第2C’圖所示，且該導電凸塊22a包含一結合該電極墊210之金屬部220與一結合該金屬部220之銲錫部221(如錫膏)；或者，如第2C”圖所示，該導電凸塊22a’亦可為銲錫凸塊(如錫膏)，而未具有如銅塊之金屬部。具體地，該電子元件21可於晶圓狀態時佈設該些導電凸塊22a,22a’，再依規格需求切單成所需尺寸之電子元件21。
又，該電子元件21與該導電柱23相結合後，將回銲所用之銲錫材料(如錫膏)，以令所用之銲錫材料融合成導電體22。例如，該導電材料28與第2C’圖之銲錫部221形成該導電體22；或者，該導電材料28與第2C”圖之導電凸塊22a’形成該導電體22。亦或，該電子元件21僅設有該金屬部220，以令該導電材料28作為該導電體22。
因此，於設置該電子元件21於該導電柱23上之前，所用之銲錫材料(或該導電體22於回銲前之狀態)可依需求形成於該電子元件21之電極墊210(或該金屬部220)上及/或該導電架2a之導電柱23上。
如第2D圖所示，接續第2C圖所示之製程，形成一封裝層25於該導電架2a之板體24上，以包覆該電子元件21、導電體22、導電柱23及金屬部220，使該封裝層25覆蓋該電子元件21之作用面21a、非作用面21b及側面21c，且令該導電架2a之板體24外露出該封裝層25。
於本實施例中，該封裝層25具有相對之第一表面25a與第二表面25b，且其以第一表面25a結合於該板體24上，並使該板體24外露出該封裝層25之第一表面25a。
再者，形成該封裝層25之材質係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)環氧樹脂之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該板體24上，但不限於上述。
如第2E圖所示，移除該導電架2a之板體24，以令該導電柱23之端面23a外露出該封裝層25之第一表面25a。又，由於該封裝層25包覆該導電柱23，故該導電柱23可視為封裝穿孔(Through Mold Via，簡稱TMV)結構。
於本實施例中，係採用研磨、蝕刻、燒灼、切除或其它適合方式移除該板體24(依需求可一併移除該封裝層25之部分材質)，使該導電柱23之端面23a與該封裝層25之第一表面25a共平面(即該導電柱23之端面23a齊平該封裝層25之第一表面25a)，以令該導電柱23之端面23a外露出該封裝層25之第一表面25a。因此，藉由移除該板體24以分開該些導電柱23，可使該些導電柱23的高度一致，故該些導電柱23所排列成之柵狀陣列之共面性良好，因而能避免於後續製程中產生接點偏移之問題。
再者，該導電體22、導電柱23及金屬部220係作為導電結構26，以作為接點。
如第2F圖所示，結合複數如銲球之導電元件27於該導電結構26之導電柱23之外露端面23a上。
如第2G圖所示，沿如第2F圖所示之切割路徑S進行切單製程，以獲取複數電子封裝件2，且該電子封裝件2可於後續應用中藉由該些導電元件27接置如電路板3之電子裝置，如第2H圖所示。
於本實施例中，若接續第2C”圖所示之製程，可獲取如第2G’圖所示之電子封裝件2’，其導電結構26’未包含有金屬部。
再者，於其它實施例中，如第3A圖所示，於切單製程時，可依需求令該電子封裝件3a包括複數個電子元件21；或者，如第3B圖所示之電子封裝件3b，可進行整平製程，如採用研磨、蝕刻、燒灼、切除或其它適合方式移除該封裝層25之部分材質(依需求可一併移除該電子元件21之部分材質)，使該電子元件21之非作用面21b齊平該封裝層35之第二表面35b，以令該電子元件21之非作用面21b外露出該封裝層35；亦或，如第3C圖所示之電子封裝件3c，於移除該板體24時，可一併移除該導電柱23之部分材質，使該導電結構36(或該導電柱33之端面33a)低於該封裝層25之第一表面25a。
又，部分該導電柱23亦可未連結該電子元件21，如第4A或4B圖所示，以作為虛柱結構43(其未電性連接該電子元件21)，供該電子封裝件4a,4b分散應力之用。具體地，該虛柱結構43可對應位於該電子元件21之垂直投影區域A之內(如第4A圖所示)或之外(如第4B圖所示)，且該虛柱結構43更可外露於該封裝層25之側面25c(如第4B圖所示)。
因此，本發明之製法主要藉由該導電柱23,33與該封裝層25,35之設計，以包覆該電子元件21之表面，使該電子元件21於製程機台間進行運送時(如於後續應用中接合該電路板3)能有效受到保護，以避免該 電子元件21之缺角問題，因而能避免整個電子元件21損毀，故相較於習知技術，本發明之電子封裝件2,2’,3a,3b,3c,4a,4b能提升產品之可靠度。
再者，本發明之製法係以導電架2a取代習知封裝基板，因而無需形成絕緣保護層及用以對應外露各該電性接觸墊之開孔，故於該封裝層25,35流入該電子元件21與該板體24間時，該封裝層25,35能順利通過而不會產生氣室(void)，因而能避免於後續製程中發生爆米花現象。
又，該導電柱23,33之周面23c之寬度係小於該兩端面23a,23b之寬度d，使該導電柱23,33之周面23c內凹，故於回銲該些導電元件27而使該導電體22變成流體(處於回銲溫度之條件狀態)時，能避免該導電體22沿該周面23c溢流至該封裝層25,35之第一表面25a而橋接相鄰兩導電元件27之問題。換言之，若該導電柱23,33之周面呈平面狀，於回銲該些導電元件27而使該導電體22變成流體時，該導電體22容易沿平面狀周面溢流至該封裝層25,35之第一表面25a而橋接相鄰兩導電元件27，進而發生短路問題。
另外，該導電柱23,33之內凹周面23c亦能容納該封裝層25,35，以提供該封裝層25,35與該導電柱23,33之間較佳的固定效果，故本發明之製法能避免因該封裝層25,35與該導電柱23,33的結合性不佳而於後續製程發生脫層之問題。
本發明復提供一種電子封裝件2,2’,3a,3b,3c,4a,4b，係包括：至少一電子元件21、複數導電結構26,26’,36以及一封裝層25,35。
所述之電子元件21係具有相對之作用面21a與非作用面21b，該作用面21a具有複數電極墊210。
所述之導電結構26,26’,36係設於該電子元件21之作用面21a上且包含有導電柱23,33，其中，各該導電柱23具有相對之兩端面 23a,23b及鄰接該兩端面23a,23b之周面23c，且該周面23c之寬度係小於該兩端面23a,23b之寬度d。
所述之封裝層25,35係包覆該電子元件21與該複數導電結構26,26’,36，且該封裝層25,35具有相對之第一表面25a與第二表面25b,35b，以令該導電柱23,33之一端面外露出該封裝層25,35之第一表面25a。
於一實施例中，該導電結構26,26’,36復具有導電體22，如包含銲錫材料，其設於該導電柱23,33與該電子元件21之間。進一步，該導電結構26復具有金屬部220，如銅柱，其設於該導電體22與該電子元件21之間。
於一實施例中，該導電柱23之外露端面23a係齊平該封裝層25之第一表面25a。
於一實施例中，該導電柱33之外露端面33a係低於該封裝層25之第一表面25a。
於一實施例中，該電子元件21之非作用面21b係外露於該封裝層35之第二表面35b。
於一實施例中，所述之電子封裝件2,2’,3a,3b,4a,4b復包括複數結合該些導電柱23,33之導電元件27，其位於該封裝層25,35之第一表面25a外。
於一實施例中，所述之電子封裝件4a,4b復包括至少一嵌埋於該封裝層25中之虛柱結構43，其未連結該電子元件21。例如，該虛柱結構43係外露於該封裝層25之第一表面25a及/或側面25c。
綜上所述，本發明之電子封裝件及其製法，係藉由該導電柱與該封裝層之設計，以令該封裝層包覆該電子元件之表面，使該電子元件能有效受到保護，故本發明之電子封裝件能提升產品之可靠度。
再者，本發明係以導電架取代習知封裝基板，因而無需形成絕緣保護層及用以對應外露各該電性接觸墊之開孔，故該封裝層能順利佈設而不會產生氣室，因而能避免於後續製程中發生爆米花現象。
又，藉由該導電柱之內凹周面之設計，故於回銲該些導電元件而使該導電體變成流體時，能避免該導電體沿該周面溢流至該封裝層之第一表面而橋接相鄰兩導電元件之問題。
另外，該導電柱之內凹周面亦能容納該封裝層，以提供該封裝層與該導電柱之間較佳的固定效果，故能避免該封裝層與該導電柱發生脫層之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
21‧‧‧電子元件
22‧‧‧導電體
220‧‧‧金屬部
23‧‧‧導電柱
25‧‧‧封裝層
25a‧‧‧第一表面
25b‧‧‧第二表面
26‧‧‧導電結構
27‧‧‧導電元件

Claims (16)

  1. 一種電子封裝件，係包括：至少一電子元件，係具有相對之作用面與非作用面，該作用面具有複數電極墊；複數導電結構，係設於該電子元件之電極墊上，且包含有導電柱、設於該導電柱與該電極墊之間的導電體、及設於該導電體與該電極墊之間的金屬部，其中，該導電柱係具有相對之兩端面及鄰接該兩端面之周面，且該周面之寬度係小於各該端面之寬度；以及一封裝層，係包覆該電子元件與該複數導電結構，且令該導電柱之一端面外露出該封裝層之外表面。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該導電體係包含銲錫材料。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該金屬部係為銅柱。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該導電柱之外露端面係低於或齊平該封裝層之外表面。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該電子元件之部分表面係外露於該封裝層之外表面。
  6. 如申請專利範圍第1項所述之電子封裝件，復包括複數位於該封裝層之外表面上且結合至該導電柱之導電元件。
  7. 如申請專利範圍第1項所述之電子封裝件，復包括至少一嵌埋於該封裝層中且未連結該電子元件之虛柱結構。
  8. 如申請專利範圍第7項所述之電子封裝件，其中，該虛柱結構係外露出該封裝層之外表面。
  9. 一種電子封裝件之製法，係包括：提供一導電架，其中，該導電架包含有一板體與複數連接該板體之導電柱，該導電柱具有相對之兩端面及鄰接該兩端面之周面，且該周面之寬度係小於各該端面之寬度；設置至少一電子元件於該導電架上，且該電子元件係具有相對之作用面與非作用面，該作用面具有複數電極墊，以令該複數導電柱之至少一部分與該複數電極墊結合，其中，該導電柱係藉由導電體結合該電極墊，且該電極墊係藉由金屬部結合該導電體；形成封裝層於該板體上，以令該封裝層包覆該電子元件與該複數導電柱；以及移除該板體，以令該導電柱之一端面外露出該封裝層之外表面。
  10. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該導電體係包含銲錫材料。
  11. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該金屬部係為銅柱。
  12. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該導電柱之外露端面係低於或齊平該封裝層之外表面。
  13. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該電子元件之部分表面係外露於該封裝層之外表面。
  14. 如申請專利範圍第9項所述之電子封裝件之製法，復包括於移除該板體後，形成導電元件於該導電柱上，且該導電元件位於該封裝層之外表面上。
  15. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該複數導電柱之其中一部分係未與該電子元件結合，以作為虛柱結構。
  16. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該虛柱結構係外露出該封裝層之外表面。
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