TWI807827B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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TWI807827B
TWI807827B TW111118103A TW111118103A TWI807827B TW I807827 B TWI807827 B TW I807827B TW 111118103 A TW111118103 A TW 111118103A TW 111118103 A TW111118103 A TW 111118103A TW I807827 B TWI807827 B TW I807827B
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Taiwan
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layer
electronic
conductive
wiring structure
electrically connected
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TW111118103A
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TW202345322A (zh
Inventor
林欣柔
王隆源
林志男
高灃
陳秋鈴
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矽品精密工業股份有限公司
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Priority to TW111118103A priority Critical patent/TWI807827B/zh
Priority to CN202210554028.4A priority patent/CN117116895A/zh
Priority to US17/858,358 priority patent/US20230369229A1/en
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Publication of TWI807827B publication Critical patent/TWI807827B/zh
Publication of TW202345322A publication Critical patent/TW202345322A/zh

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Abstract

一種電子封裝件及其製法，係將一作為橋接元件之電子模組及複數導電柱嵌埋於封裝層中，並於該封裝層上形成佈線結構，以供設置複數電子元件於該佈線結構上，使該些電子元件藉由該佈線結構電性橋接該電子模組。

Description

電子封裝件及其製法
本發明係有關一種電子封裝件及其製法，尤指一種具有橋接元件之電子封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。同時，目前應用於晶片封裝領域之技術，包含有例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組等。
圖1A係為習知半導體封裝件1之剖面示意圖，該半導體封裝件1包括：第一封裝層15、一嵌埋於該第一封裝層15中之橋接晶片10與複數導電柱13、一設於該第一封裝層15上側15a並電性連接該橋接晶片10與複數導電柱13之第一佈線結構11、複數設於該第一佈線結構11上之電子元件19、用以包覆複數該電子元件19之第二封裝層18、一設於該第一封裝層15下側15b並電性連接該複數導電柱13之第二佈線結構12、以及複數設於該第二佈線結構12上且電性連接該第二佈線結構12之導電元件17。
如圖1B所示，所述之橋接晶片10係具有複數外露於鈍化層10a之電極墊100，並結合有複數銅凸塊101。
所述之第一佈線結構11係包括複數絕緣層110、設於該複數絕緣層110上之複數佈線層111及電性連接各該佈線層111之複數導電盲孔112，以令該複數導電盲孔112電性連接該複數銅凸塊101與該複數佈線層111，且最外層之佈線層111具有複數微墊(u-pad)規格之電性接觸墊113，如圖1A及圖1B所示。
所述之電子元件19係為功能晶片，其具有複數複數外露於鈍化層19a之電極墊190，如圖1B所示，以結合如微凸塊(u-bump)規格之導電凸塊193，使該電子元件19藉由覆晶方式將導電凸塊193與銲錫材料191銲接於該電性接觸墊113上，再以底膠192包覆該些導電凸塊193與銲錫材料191。
習知半導體封裝件1係藉由配置該橋接晶片10，以作為兩個電子元件19之間的訊號水平方向之電性連接路徑，且藉由該複數導電柱13作為垂直電性連接之路徑。
惟，習知半導體封裝件1中，該橋接晶片10需藉由第一佈線結構11與該複數導電柱13，才能將訊號傳遞至該第二佈線結構12，致使該橋接晶片10對外之電性訊號傳輸路徑過長，且訊號傳遞速度過慢。
再者，該橋接晶片10無法採用大尺寸規格，因而其僅能以小尺寸規格進行設計，導致該第一佈線結構11受限於該橋接晶片10之尺寸而使其配線設計不易，因而容易產生各層導電盲孔112相互疊合(如圖1R所示之垂直投影重疊區域P)而形成疊孔結構，造成應力集中之現象，導致該第一佈線結構11容易因應力分佈不均而發生碎裂之問題。
因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：第一封裝層，係具有相對之第一側與第二側；複數導電柱，係嵌埋於該第一封裝層中並連通該第一封裝層之第一側與第二側；電子模組，係嵌埋於該第一封裝層中且包含：包覆層，係具有相對之第一表面與第二表面；第一電子元件，係嵌埋於該包覆層中；複數導電通孔，係嵌埋於該包覆層中並連通該第一表面與第二表面；及第一線路結構，係形成於該包覆層之第一表面上以電性連接該第一電子元件與該複數導電通孔；第一佈線結構，係設於該第一封裝層之第一側上並電性連接該複數導電柱與該電子模組之第一線路結構；以及複數第二電子元件，係設於該第一佈線結構上並電性連接該第一佈線結構，其中，該複數第二電子元件之至少兩者係藉由該第一佈線結構電性導通至該電子模組，使該電子模組電性橋接該複數第二電子元件之至少兩者。
本發明復提供一種電子封裝件之製法，係包括：提供一電子模組，其包含有一包覆層、嵌埋於該包覆層中之第一電子元件與複數導電通孔、及形成於該包覆層上之第一線路結構，且該第一線路結構係電性連接該第一電子元件與該複數導電通孔；將該電子模組設於一承載板上，且於該承載板上形成有複數導電柱；形成第一封裝層於該承載板上，以包覆該電子模組與複數導電柱，其中，該第一封裝層係具有相對之第一側與第二側，且該第一封裝層以其第二側結合該承載板；移除該承載板；形成第一佈線結構於該第一封裝層之第一側上，以令該第一佈線結構電性連接該複數導電柱與該電子模組之第一線路結構；以及將 複數第二電子元件設於該第一佈線結構上並電性連接該第一佈線結構，其中，該複數第二電子元件之至少兩者係藉由該第一佈線結構電性導通至該電子模組，使該電子模組電性橋接該複數第二電子元件之至少兩者。
前述之電子封裝件及其製法中，該電子模組之包覆層係具有相對之第一表面與第二表面，以於該第一表面上形成該第一線路結構，且於該第二表面上形成第二線路結構，以令該複數導電通孔電性連接該第二線路結構。
前述之電子封裝件及其製法中，該電子模組之第一電子元件係具有相對之作用面與非作用面，且其作用面具有複數電性連接該第一線路結構之電極墊。
前述之電子封裝件及其製法中，該第二電子元件係藉由複數導電凸塊電性連接該第一佈線結構。
前述之電子封裝件及其製法中，復包括以第二封裝層包覆該複數第二電子元件。
前述之電子封裝件及其製法中，復包括於移除該承載板後，於該第一封裝層之第二側上形成第二佈線結構，以令該複數導電柱電性連接該第二佈線結構。例如，該第二佈線結構係包含至少一絕緣層及至少一結合該絕緣層之佈線層，且最外層之佈線層係具有電性接觸墊或凸塊底下金屬層。
前述之電子封裝件及其製法中，復包括形成複數導電元件於該第一封裝層之第二側上，以令該複數導電元件電性連接該複數導電柱及/或該電子模組。
前述之電子封裝件及其製法中，該電子模組之第一線路結構係包含複數錯位之導電盲孔。
由上可知，本發明之電子封裝件及其製法中，主要藉由該電子模組具有導電通孔之設計，以作為該電子模組對外之電性傳輸路徑，故相較於習知 技術，該電子模組對外之電性訊號傳輸路徑將大幅縮短，且訊號傳遞速度將大幅增快。
再者，該電子模組藉由配置該導電通孔，使該包覆層可採用大尺寸規格進行封裝，以於該包覆層上進行RDL製程，且第一線路結構之配線設計不會受限於該第一電子元件之尺寸，因而可將各層之第一導電盲孔採用錯位設計，以避免應力集中之現象，故相較於習知技術，該第一線路結構可有效避免因應力分佈不均而發生碎裂之問題。
1:半導體封裝件
10:橋接晶片
10a,19a:鈍化層
100,190,200,290:電極墊
101:銅凸塊
11,31:第一佈線結構
110,30:絕緣層
111:佈線層
112:導電盲孔
113,213,323:電性接觸墊
12,32:第二佈線結構
13,33:導電柱
15,25:第一封裝層
15a:上側
15b:下側
17,27:導電元件
18,28:第二封裝層
19:電子元件
191:銲錫材料
192,292:底膠
193,223,291:導電凸塊
2:電子封裝件
2a:電子模組
20:第一電子元件
20a,29a:作用面
20b,29b:非作用面
201:絕緣膜
202:導電體
21:第一線路結構
210:第一介電層
211:第一線路層
212:第一導電盲孔
22:第二線路結構
220:第二介電層
221:第二線路層
222:第二導電盲孔
23:導電通孔
24:包覆層
24a:第一表面
24b:第二表面
25a:第一側
25b:第二側
270:凸塊底下金屬層
29:第二電子元件
300,340:開孔
310:第一絕緣層
311:第一佈線層
320:第二絕緣層
321:第二佈線層
33a:端面
34:絕緣保護層
8:佈線板件
9:承載板
90:離形層
91:黏著層
A:配線區域
P:垂直投影重疊區域
P1,P2:位置
S:切割路徑
圖1A係為習知半導體封裝件之剖視示意圖。
圖1B係為圖1A之局部放大剖視示意圖。
圖2A至圖2G係為本發明之電子封裝件之製法之剖視示意圖。
圖2H係為圖2G之後續製程之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、及「一」等之用語，亦僅為便於敘述 之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2G係為本發明之電子封裝件2之製法之剖面示意圖。
如圖2A所示，提供一作為橋接元件之電子模組2a，其包括：一包覆層24、至少一嵌埋於該包覆層24中之第一電子元件20、複數嵌埋於該包覆層24中之導電通孔23、分別設於該包覆層24相對兩側之第一線路結構21及第二線路結構22。
所述之包覆層24係為絕緣材，如環氧樹脂之封裝膠體，其具有相對之第一表面24a及第二表面24b，以令該第一線路結構21設於該包覆層24之第一表面24a上並電性連接該複數導電通孔23，且該第二線路結構22設於該包覆層24之第二表面24b上並電性連接該複數導電通孔23。
所述之第一電子元件20係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。於本實施例中，該第一電子元件20係為半導體晶片，如橋接晶片，其具有相對之作用面20a與非作用面20b，且其作用面20a具有複數電極墊200，其中，該複數電極墊200上形成有如銅凸塊之複數導電體202，並於該作用面20a上形成一絕緣膜201，且令該導電體202外露於該絕緣膜201。
所述之導電通孔23係連通該包覆層24之第一表面24a與第二表面24b，且可為如銅柱體之金屬柱、銲錫凸塊或其它可垂直電性導通訊號之適當結構，並無特別限制。
所述之第一線路結構21係電性連接該複數導電通孔23與該複數電極墊200，且該第一線路結構21係包含至少一第一介電層210、結合該第一介電層210之第一線路層211及複數電性連接該第一線路層211之第一導電盲孔212， 並可使最外層之第一線路層211外露出該第一介電層210，供作為電性接觸墊213，如微墊(u-pad)規格。
於本實施例中，以線路重佈層(redistribution layer，簡稱RDL)之製作方式形成該第一線路層211與該第一導電盲孔212，其材質係為銅，且形成該第一介電層210之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。應可理解地，該第一線路結構21亦可僅包括單一介電層及單一線路層。
再者，若具有至少兩層盲孔配置，則上下兩層之第一導電盲孔212之位置P1,P2係相互錯開，如圖2A所示之左右兩側之電性接觸墊213所電性連接之配線區域A。
所述之第二線路結構22係電性連接該些導電通孔23，且該第二線路結構22係包含至少一第二介電層220、結合該第二介電層220之第二線路層221及複數電性連接該第二線路層221之第二導電盲孔222，並可使最外層之第二介電層220作為防銲層，以令最外層之第二線路層221部分外露出該防銲層，供結合複數如銲錫凸塊之導電凸塊223。
於本實施例中，以線路重佈層(RDL)之製作方式形成該第二線路層221與該第二導電盲孔222，其材質係為銅，且形成該第二介電層220之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)等之介電材，而該導電凸塊223係為如銅柱、銲錫球等金屬凸塊。應可理解地，該第二線路結構22亦可僅包括單一介電層及單一線路層，且若具有至少兩層盲孔配置，則上下兩層之第二導電盲孔222可相互錯位。
如圖2B所示，提供一設有絕緣層30之承載板9，其中，該絕緣層30上形成複數開孔300，並於該絕緣層30之部分開孔300上形成導電柱33，且將該電子模組2a藉由該些導電凸塊223嵌入部分該開孔300中而設於該絕緣層30上。
於本實施例中，該絕緣層30之材質係如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材。
再者，該承載板9係例如為半導體材質(如矽或玻璃)之板體，其上可依需求依序形成有一離形層90與一黏著層91，以供該絕緣層30設於該黏著層91上。
又，該導電柱33係以電鍍方式形成於該絕緣層30上，且形成該導電柱33之材質係為如銅之金屬材或銲錫材。
如圖2C所示，形成一第一封裝層25於該絕緣層30上，以令該第一封裝層25包覆該電子模組2a與該些導電柱33，其中，該第一封裝層25係具有相對之第一側25a與第二側25b，且其以第二側25b結合該絕緣層30。接著，藉由整平製程，使該第一封裝層25之第一側25a之表面齊平該導電柱33之端面33a，令該導電柱33之端面33a與該電子模組2a之第一線路層211之電性接觸墊213外露出該第一封裝層25之第一側25a。
於本實施例中，該第一封裝層25係為絕緣材，如聚醯亞胺(PI)、乾膜(dry film)、環氧樹脂(epoxy)等之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該絕緣層30上。
再者，該整平製程係藉由研磨方式，移除該導電柱33之部分材質與該第一封裝層25之部分材質。
又，該第一封裝層25係接觸該電子模組2a之包覆層24。
如圖2D所示，形成一第一佈線結構31於該第一封裝層25之第一側25a上，且令該第一佈線結構31電性連接該複數導電柱33與該電子模組2a之第一線路層211之複數電性接觸墊213。
於本實施例中，該第一佈線結構31係以線路重佈層(redistribution layer，簡稱RDL)之製作方式，其包括複數第一絕緣層310、及設於該第一絕緣層310上之複數第一佈線層311，且最外層之第一絕緣層310可作為防銲層，以令最外層之第一佈線層311部分外露出該防銲層。或者，該第一佈線結構31亦可僅包括單一絕緣層及單一佈線層。
再者，形成該第一佈線層311之材質係為銅，且形成該第一絕緣層310之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)或其它等之介電材。
如圖2E所示，移除該承載板9及其上之離形層90與黏著層91，以外露該絕緣層30，且使該複數導電柱33與該複數導電凸塊223外露於該絕緣層30。
如圖2F所示，於最外層之第一佈線層311上接置複數第二電子元件29，並以一第二封裝層28包覆該複數第二電子元件29，且可形成複數如銲球之導電元件27於該第一封裝層25之第二側25b上，以令該複數導電元件27電性連接該複數導電柱33及/或該電子模組2a之複數導電凸塊223。
於本實施例中，可於該絕緣層30上以線路重佈層(redistribution layer，簡稱RDL)之製作方式形成第二佈線結構32，其包含第二絕緣層320及結合該第二絕緣層320與絕緣層30之第二佈線層321。例如，形成該第二佈線層321之材質係為銅，且形成該第二絕緣層320之材質係如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材，並可形成一如防銲層之絕緣保護層34於該第二絕緣層320上，且於該絕緣保護層34上形成複數開孔340，以令該第二佈線層321外露出該些開孔，俾供結合該複數導電元件27，使該複數導電元件27藉由該第二佈線結構32電性連接該複數導電柱33及/或該電子模組2a之第二線路層221之複數導電凸塊223。
進一步，最外層之第二佈線層321可具有複數電性接觸墊323及/或最外層之第二佈線層321上可形成有凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)270，以利於結合該導電元件27。
再者，該第二電子元件29係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該第二電子元件29係為半導體晶片，如系統單晶片(System-On-Chip，簡稱SOC)型之功能晶片，其具有相對之作用面29a與非作用面29b，且以其作用面29a之電極墊290藉由複數如銲錫材料之導電凸塊291採用覆晶方式設於該第一佈線層311上並電性連接該第一佈線層311，並以底膠292包覆該些導電凸塊291；或者，該第二電子元件29以其非作用面29b設於該第一佈線結構31上，並可藉由複數銲線(圖略)以打線方式電性連接該第一佈線層311；亦或透過如導電膠或銲錫等導電材料(圖略)電性連接該第一佈線層311。然而，有關該第二電子元件29電性連接該第一佈線層311之方式不限於上述。
又，該複數第二電子元件29之至少兩者係藉由該第一佈線結構31電性導通至該電子模組2a之第一線路層211之複數電性接觸墊213，使該電子模組2a係作為兩第二電子元件29之電性接橋元件，以增加該些第二電子元件29之接點數量(即增加該電子封裝件2之功能)。
另外，該第二封裝層28係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該第一佈線結構31上。因此，該第二封裝層28、第一封裝層25與包覆層24之至少二者之材質可相同或相異。
進一步，可藉由整平製程，如研磨方式，使該第二封裝層28齊平該第二電子元件29之非作用面29b，以令該第二電子元件29之非作用面29b外露於該第二封裝層28之上表面(未圖示)。
應可理解地，於其它實施例中，亦可省略製作該底膠292，而依需求以該第二封裝層28包覆該導電凸塊291與該第二電子元件29。
如圖2G所示，沿圖2F中所示之切割路徑S進行切單製程，以獲取該電子封裝件2，且於後續製程中，如圖2H所示，該電子封裝件2可藉由該些導電元件27接置於一佈線板件8之上側，其中，該佈線板件8例如有機材板體(如具有核心層與線路之封裝基板(substrate)或具有線路之無核心層式(coreless)封裝基板)或無機材板體(如矽板材)，且該佈線板件8之下側可接置於一如電路板之電子裝置(圖未示)上。
因此，本發明之製法主要藉由該電子模組2a具有導電通孔23之設計，以作為該電子模組2a對外之電性傳輸路徑，使該電子模組2a藉由該導電通孔23，即可將訊號傳遞至該第二佈線結構32，故相較於習知技術，該電子模組2a對外之電性訊號傳輸路徑大幅縮短，且訊號傳遞速度大幅增快。
再者，該電子模組2a藉由配置該導電通孔23，使該包覆層24可採用大尺寸規格進行封裝，因而該電子模組2a能以大尺寸規格進行設計，以於該包覆層24上進行RDL製程，且第一線路結構21之配線設計不會受限於該第一電子元件20之尺寸，因而能將各層之第一導電盲孔212採用錯位設計，以避免應力集中之現象，故相較於習知技術，該第一線路結構21能有效避免因應力分佈不均而發生碎裂之問題。
應可理解地，由於該電子模組2a之第一線路結構21可依需求進行配線設計，故該第一佈線結構31更能於該第一封裝層25上依需求進行配線設計， 完全不受限於該電子模組2a之尺寸，因而該第一佈線結構31不會發生如習知因應力分佈不均而發生碎裂之問題。
又，將作為輔助功能之電子模組2a嵌埋於該第一封裝層25中以對接該第二電子元件29，以利於配合不同功能之第二電子元件29。
另外，本發明之第二電子元件29之部分電性功能(如電源或接地)可藉由電子模組2a之導電通孔23作為電性傳輸路徑。
本發明亦提供一種電子封裝件2，係包括：一第一封裝層25、複數導電柱33、至少一電子模組2a、第一佈線結構31以及複數第二電子元件29，且該電子模組2a係包含有一包覆層24、第一電子元件20、複數導電通孔23及一第一線路結構21。
所述之第一封裝層25係具有相對之第一側25a與第二側25b。
所述之導電柱33係嵌埋於該第一封裝層25中並連通該第一封裝層25之第一側25a與第二側25b。
所述之電子模組2a係嵌埋於該第一封裝層25中。
所述之包覆層24係具有相對之第一表面24a與第二表面24b。
所述之第一電子元件20係嵌埋於該包覆層24中。
所述之導電通孔23係嵌埋於該包覆層24中並連通該第一表面24a與第二表面24b。
所述之第一線路結構21係形成於該包覆層24之第一表面24a上以電性連接該第一電子元件20與該複數導電通孔23。
所述之第一佈線結構31係設於該第一封裝層25之第一側25a上並電性連接該複數導電柱33與該電子模組2a之第一線路結構21。
所述之第二電子元件29係設於該第一佈線結構31上並電性連接該第一佈線結構31，其中，該複數第二電子元件29之至少兩者係藉由該第一佈線 結構31電性導通至該電子模組2a，使該電子模組2a電性橋接該複數第二電子元件29之至少兩者。
於一實施例中，該電子模組2a之包覆層24之第二表面24b上係形成有第二線路結構22，以令該複數導電通孔23電性連接該第二線路結構22。
於一實施例中，該電子模組2a之第一電子元件20係具有相對之作用面20a與非作用面20b，且其作用面20a具有複數電性連接該第一線路結構21之電極墊200。
於一實施例中，該第二電子元件29係藉由複數導電凸塊291電性連接該第一佈線結構31。
於一實施例中，所述之電子封裝件2復包括包覆該複數第二電子元件29之第二封裝層28。
於一實施例中，所述之電子封裝件2復包括形成於該第一封裝層25之第二側25b上之第二佈線結構32，以令該複數導電柱33電性連接該第二佈線結構32。例如，該第二佈線結構32係包含至少一第二絕緣層320及至少一結合該第二絕緣層320之第二佈線層321，且最外層之第二佈線層321係具有電性接觸墊322或凸塊底下金屬層270。
於一實施例中，所述之電子封裝件2復包括形成於該第一封裝層25之第二側25b上之複數導電元件27，其電性連接該複數導電柱33及/或該電子模組2a。例如，該電子封裝件2係透過該複數導電元件27係接置於一佈線板件8上。
於一實施例中，該電子模組2a之第一線路結構21係包含複數錯位之導電盲孔212。
綜上所述，本發明之電子封裝件及其製法，係藉由該電子模組具有導電通孔之設計，以作為該電子模組對外之電性傳輸路徑，故該電子模組對外之電性訊號傳輸路徑能大幅縮短，且訊號傳遞速度能大幅增快。
再者，該電子模組藉由配置該導電通孔，使該電子模組能以大尺寸規格進行封裝設計，以於該包覆層上進行RDL製程，且第一線路結構之配線設計不會受限於該第一電子元件之尺寸，故能將各層之第一導電盲孔採用錯位設計，以避免應力集中之現象，使該第一線路結構能有效避免因應力分佈不均而發生碎裂之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2a:電子模組
20:第一電子元件
21:第一線路結構
22:第二線路結構
23:導電通孔
24:包覆層
25:第一封裝層
25a:第一側
25b:第二側
27:導電元件
28:第二封裝層
29:第二電子元件
30:絕緣層
31:第一佈線結構
32:第二佈線結構
33:導電柱

Claims (17)

  1. 一種電子封裝件，係包括：第一封裝層，係具有相對之第一側與第二側；複數導電柱，係嵌埋於該第一封裝層中並連通該第一封裝層之第一側與第二側；電子模組，係嵌埋於該第一封裝層中且包含：包覆層，係具有相對之第一表面與第二表面；第一電子元件，係嵌埋於該包覆層中；複數導電通孔，係嵌埋於該包覆層中並連通該第一表面與第二表面；第一線路結構，係形成於該包覆層之第一表面上並嵌埋於該第一封裝層中以電性連接該第一電子元件與該複數導電通孔；及第二線路結構，係形成於該包覆層之第二表面上並嵌埋於該第一封裝層中以電性連接該複數導電通孔；第一佈線結構，係設於該第一封裝層之第一側上並電性連接該複數導電柱與該電子模組之第一線路結構；以及複數第二電子元件，係設於該第一佈線結構上並電性連接該第一佈線結構，其中，該複數第二電子元件之至少兩者係藉由該第一佈線結構電性導通至該電子模組，使該電子模組電性橋接該複數第二電子元件之至少兩者。
  2. 如請求項1所述之電子封裝件，其中，該電子模組之第一電子元件係具有相對之作用面與非作用面，且其作用面具有複數電性連接該第一線路結構之電極墊。
  3. 如請求項1所述之電子封裝件，其中，該第二電子元件係藉由複數導電凸塊電性連接該第一佈線結構。
  4. 如請求項1所述之電子封裝件，復包括包覆該複數第二電子元件之第二封裝層。
  5. 如請求項1所述之電子封裝件，復包括形成於該第一封裝層之第二側上之第二佈線結構，以令該複數導電柱電性連接該第二佈線結構。
  6. 如請求項5所述之電子封裝件，其中，該第二佈線結構係包含至少一絕緣層及至少一結合該絕緣層之佈線層，且最外層之佈線層係具有電性接觸墊或凸塊底下金屬層。
  7. 如請求項1所述之電子封裝件，復包括形成於該第一封裝層之第二側上之複數導電元件，其電性連接該複數導電柱及/或該電子模組。
  8. 如請求項1所述之電子封裝件，其中，該電子模組之第一線路結構係包含複數錯位之導電盲孔。
  9. 一種電子封裝件之製法，係包括：提供一電子模組，其包含有一包覆層、嵌埋於該包覆層中之第一電子元件與複數導電通孔、及形成於該包覆層上之第一線路結構，且該第一線路結構係電性連接該第一電子元件與該複數導電通孔；將該電子模組設於一承載板上，且於該承載板上形成有複數導電柱；形成第一封裝層於該承載板上，以包覆該電子模組與複數導電柱，其中，該第一封裝層係具有相對之第一側與第二側，且該第一封裝層以其第二側結合該承載板；移除該承載板； 形成第一佈線結構於該第一封裝層之第一側上，以令該第一佈線結構電性連接該複數導電柱與該電子模組之第一線路結構；以及將複數第二電子元件設於該第一佈線結構上並電性連接該第一佈線結構，其中，該複數第二電子元件之至少兩者係藉由該第一佈線結構電性導通至該電子模組，使該電子模組電性橋接該複數第二電子元件之至少兩者。
  10. 如請求項9所述之電子封裝件之製法，其中，該電子模組之包覆層係具有相對之第一表面與第二表面，以於該第一表面上形成該第一線路結構，且於該第二表面上形成第二線路結構，以令該複數導電通孔電性連接該第二線路結構。
  11. 如請求項9所述之電子封裝件之製法，其中，該電子模組之第一電子元件係具有相對之作用面與非作用面，且其作用面具有複數電性連接該第一線路結構之電極墊。
  12. 如請求項9所述之電子封裝件之製法，其中，該第二電子元件係藉由複數導電凸塊電性連接該第一佈線結構。
  13. 如請求項9所述之電子封裝件之製法，復包括以第二封裝層包覆該複數第二電子元件。
  14. 如請求項9所述之電子封裝件之製法，復包括於移除該承載板後，於該第一封裝層之第二側上形成第二佈線結構，以令該複數導電柱電性連接該第二佈線結構。
  15. 如請求項14所述之電子封裝件之製法，其中，該第二佈線結構係包含至少一絕緣層及至少一結合該絕緣層之佈線層，且最外層之佈線層係具有電性接觸墊或凸塊底下金屬層。
  16. 如請求項9所述之電子封裝件之製法，復包括形成複數導電元件於該第一封裝層之第二側上，以令該複數導電元件電性連接該複數導電柱及/或該電子模組。
  17. 如請求項9所述之電子封裝件之製法，其中，該電子模組之第一線路結構係包含複數錯位之導電盲孔。
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