CN117116895A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

Info

Publication number
CN117116895A
CN117116895A CN202210554028.4A CN202210554028A CN117116895A CN 117116895 A CN117116895 A CN 117116895A CN 202210554028 A CN202210554028 A CN 202210554028A CN 117116895 A CN117116895 A CN 117116895A
Authority
CN
China
Prior art keywords
layer
electronic
conductive
wiring structure
electronic module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210554028.4A
Other languages
English (en)
Inventor
林欣柔
王隆源
林志男
高沣
陈秋铃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN117116895A publication Critical patent/CN117116895A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5381—Crossover interconnections, e.g. bridge stepovers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Credit Cards Or The Like (AREA)
  • Containers And Plastic Fillers For Packaging (AREA)

Abstract

一种电子封装件及其制法，包括将一作为桥接元件的电子模组及多个导电柱嵌埋于封装层中，并于该封装层上形成布线结构，以供设置多个电子元件于该布线结构上，使该些电子元件通过该布线结构电性桥接该电子模组。

Description

电子封装件及其制法
技术领域
本发明有关一种电子封装件及其制法，尤指一种具有桥接元件的电子封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。同时，目前应用于芯片封装领域的技术，包含有例如芯片尺寸构装(Chip Scale Package，简称CSP)、芯片直接贴附封装(Direct Chip Attached，简称DCA)或多芯片模组封装(Multi-Chip Module，简称MCM)等覆晶型态的封装模组等。
图1A为现有半导体封装件1的剖面示意图，该半导体封装件1包括：第一封装层15、一嵌埋于该第一封装层15中的桥接芯片10与多个导电柱13、一设于该第一封装层15上侧15a并电性连接该桥接芯片10与多个导电柱13的第一布线结构11、多个设于该第一布线结构11上的电子元件19、用以包覆多个该电子元件19的第二封装层18、一设于该第一封装层15下侧15b并电性连接该多个导电柱13的第二布线结构12、以及多个设于该第二布线结构12上且电性连接该第二布线结构12的导电元件17。
如图1B所示，所述的桥接芯片10具有多个外露于钝化层10a的电极垫100，并结合有多个铜凸块101。
所述的第一布线结构11包括多个绝缘层110、设于该多个绝缘层110上的多个布线层111及电性连接各该布线层111的多个导电盲孔112，以令该多个导电盲孔112电性连接该多个铜凸块101与该多个布线层111，且最外层的布线层111具有多个微垫(u-pad)规格的电性接触垫113，如图1A及图1B所示。
所述的电子元件19为功能芯片，其具有多个多个外露于钝化层19a的电极垫190，如图1B所示，以结合如微凸块(u-bump)规格的导电凸块193，使该电子元件19通过覆晶方式将导电凸块193与焊锡材料191焊接于该电性接触垫113上，再以底胶192包覆该些导电凸块193与焊锡材料191。
现有半导体封装件1通过配置该桥接芯片10，以作为两个电子元件19的间的信号水平方向的电性连接路径，且通过该多个导电柱13作为垂直电性连接的路径。
然而，现有半导体封装件1中，该桥接芯片10需通过第一布线结构11与该多个导电柱13，才能将信号传递至该第二布线结构12，致使该桥接芯片10对外的电性信号传输路径过长，且信号传递速度过慢。
再者，该桥接芯片10无法采用大尺寸规格，因而其仅能以小尺寸规格进行设计，导致该第一布线结构11受限于该桥接芯片10的尺寸而使其配线设计不易，因而容易产生各层导电盲孔112相互叠合(如图1B所示的垂直投影重叠区域P)而形成叠孔结构，造成应力集中的现象，导致该第一布线结构11容易因应力分布不均而发生碎裂的问题。
因此，如何克服上述现有技术的种种问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种电子封装件及其制法，以至少部分地解决现有技术中的问题。
本发明的电子封装件，包括：第一封装层，其具有相对的第一侧与第二侧；多个导电柱，其嵌埋于该第一封装层中并连通该第一封装层的第一侧与第二侧；电子模组，其嵌埋于该第一封装层中且包含：包覆层，其具有相对的第一表面与第二表面；第一电子元件，其嵌埋于该包覆层中；多个导电通孔，其嵌埋于该包覆层中并连通该第一表面与第二表面；及第一线路结构，其形成于该包覆层的第一表面上以电性连接该第一电子元件与该多个导电通孔；第一布线结构，其设于该第一封装层的第一侧上并电性连接该多个导电柱与该电子模组的第一线路结构；以及多个第二电子元件，其设于该第一布线结构上并电性连接该第一布线结构，其中，该多个第二电子元件的至少两者通过该第一布线结构电性导通至该电子模组，使该电子模组电性桥接该多个第二电子元件的至少两者。
本发明还提供一种电子封装件的制法，包括：提供一电子模组，其包含有一包覆层、嵌埋于该包覆层中的第一电子元件与多个导电通孔、及形成于该包覆层上的第一线路结构，且该第一线路结构电性连接该第一电子元件与该多个导电通孔；将该电子模组设于一承载板上，且于该承载板上形成有多个导电柱；形成第一封装层于该承载板上，以包覆该电子模组与多个导电柱，其中，该第一封装层具有相对的第一侧与第二侧，且该第一封装层以其第二侧结合该承载板；移除该承载板；形成第一布线结构于该第一封装层的第一侧上，以令该第一布线结构电性连接该多个导电柱与该电子模组的第一线路结构；以及将多个第二电子元件设于该第一布线结构上并电性连接该第一布线结构，其中，该多个第二电子元件的至少两者通过该第一布线结构电性导通至该电子模组，使该电子模组电性桥接该多个第二电子元件的至少两者。
前述的电子封装件及其制法中，该电子模组的包覆层具有相对的第一表面与第二表面，以于该第一表面上形成该第一线路结构，且于该第二表面上形成第二线路结构，以令该多个导电通孔电性连接该第二线路结构。
前述的电子封装件及其制法中，该电子模组的第一电子元件具有相对的作用面与非作用面，且其作用面具有多个电性连接该第一线路结构的电极垫。
前述的电子封装件及其制法中，该第二电子元件通过多个导电凸块电性连接该第一布线结构。
前述的电子封装件及其制法中，还包括以第二封装层包覆该多个第二电子元件。
前述的电子封装件及其制法中，还包括于移除该承载板后，于该第一封装层的第二侧上形成第二布线结构，以令该多个导电柱电性连接该第二布线结构。例如，该第二布线结构包含至少一绝缘层及至少一结合该绝缘层的布线层，且最外层的布线层具有电性接触垫或凸块底下金属层。
前述的电子封装件及其制法中，还包括形成多个导电元件于该第一封装层的第二侧上，以令该多个导电元件电性连接该多个导电柱及/或该电子模组。
前述的电子封装件及其制法中，该电子模组的第一线路结构包含多个错位的导电盲孔。
由上可知，本发明的电子封装件及其制法中，主要通过该电子模组具有导电通孔的设计，以作为该电子模组对外的电性传输路径，故相比于现有技术，该电子模组对外的电性信号传输路径将大幅缩短，且信号传递速度将大幅增快。
再者，该电子模组通过配置该导电通孔，使该包覆层可采用大尺寸规格进行封装，以于该包覆层上进行RDL制程，且第一线路结构的配线设计不会受限于该第一电子元件的尺寸，因而可将各层的第一导电盲孔采用错位设计，以避免应力集中的现象，故相比于现有技术，该第一线路结构可有效避免因应力分布不均而发生碎裂的问题。
附图说明
图1A为现有半导体封装件的剖视示意图。
图1B为图1A的局部放大剖视示意图。
图2A至图2G为本发明的电子封装件的制法的剖视示意图。
图2H为图2G的后续制程的剖视示意图。
主要组件符号说明
1:半导体封装件
10:桥接芯片
10a,19a:钝化层
100,190,200,290:电极垫
101:铜凸块
11,31:第一布线结构
110,30:绝缘层
111:布线层
112:导电盲孔
113,213,323:电性接触垫
12,32:第二布线结构
13,33:导电柱
15,25:第一封装层
15a:上侧
15b:下侧
17,27:导电元件
18,28:第二封装层
19:电子元件
191:焊锡材料
192,292:底胶
193,223,291:导电凸块
2:电子封装件
2a:电子模组
20:第一电子元件
20a,29a:作用面
20b,29b:非作用面
201:绝缘膜
202:导电体
21:第一线路结构
210:第一介电层
211:第一线路层
212:第一导电盲孔
22:第二线路结构
220:第二介电层
221:第二线路层
222:第二导电盲孔
23:导电通孔
24:包覆层
24a:第一表面
24b:第二表面
25a:第一侧
25b:第二侧
270:凸块底下金属层
29:第二电子元件
300,340:开孔
310:第一绝缘层
311:第一布线层
320:第二绝缘层
321:第二布线层
33a:端面
34:绝缘保护层
8:布线板件
9:承载板
90:离形层
91:黏着层
A:配线区域
P:垂直投影重叠区域
P1,P2:位置
S:切割路径。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2G为本发明的电子封装件2的制法的剖面示意图。
如图2A所示，提供一作为桥接元件的电子模组2a，其包括：一包覆层24、至少一嵌埋于该包覆层24中的第一电子元件20、多个嵌埋于该包覆层24中的导电通孔23、分别设于该包覆层24相对两侧的第一线路结构21及第二线路结构22。
所述的包覆层24为绝缘材，如环氧树脂的封装胶体，其具有相对的第一表面24a及第二表面24b，以令该第一线路结构21设于该包覆层24的第一表面24a上并电性连接该多个导电通孔23，且该第二线路结构22设于该包覆层24的第二表面24b上并电性连接该多个导电通孔23。
所述的第一电子元件20为主动元件、被动元件或其二者组合等，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。于本实施例中，该第一电子元件20为半导体芯片，如桥接芯片，其具有相对的作用面20a与非作用面20b，且其作用面20a具有多个电极垫200，其中，该多个电极垫200上形成有如铜凸块的多个导电体202，并于该作用面20a上形成一绝缘膜201，且令该导电体202外露于该绝缘膜201。
所述的导电通孔23连通该包覆层24的第一表面24a与第二表面24b，且可为如铜柱体的金属柱、焊锡凸块或其它可垂直电性导通信号的适当结构，并无特别限制。
所述的第一线路结构21电性连接该多个导电通孔23与该多个电极垫200，且该第一线路结构21包含至少一第一介电层210、结合该第一介电层210的第一线路层211及多个电性连接该第一线路层211的第一导电盲孔212，并可使最外层的第一线路层211外露出该第一介电层210，供作为电性接触垫213，如微垫(u-pad)规格。
于本实施例中，以线路重布层(redistribution layer，简称RDL)的制作方式形成该第一线路层211与该第一导电盲孔212，其材质为铜，且形成该第一介电层210的材质为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)等的介电材。应可理解地，该第一线路结构21亦可仅包括单一介电层及单一线路层。
再者，若具有至少两层盲孔配置，则上下两层的第一导电盲孔212的位置P1,P2相互错开，如图2A所示的左右两侧的电性接触垫213所电性连接的配线区域A。
所述的第二线路结构22电性连接该些导电通孔23，且该第二线路结构22包含至少一第二介电层220、结合该第二介电层220的第二线路层221及多个电性连接该第二线路层221的第二导电盲孔222，并可使最外层的第二介电层220作为防焊层，以令最外层的第二线路层221部分外露出该防焊层，供结合多个如焊锡凸块的导电凸块223。
于本实施例中，以线路重布层(RDL)的制作方式形成该第二线路层221与该第二导电盲孔222，其材质为铜，且形成该第二介电层220的材质为如聚对二唑苯(PBO)、聚酰亚胺(PI)、预浸材(PP)等的介电材，而该导电凸块223为如铜柱、焊锡球等金属凸块。应可理解地，该第二线路结构22亦可仅包括单一介电层及单一线路层，且若具有至少两层盲孔配置，则上下两层的第二导电盲孔222可相互错位。
如图2B所示，提供一设有绝缘层30的承载板9，其中，该绝缘层30上形成多个开孔300，并于该绝缘层30的部分开孔300上形成导电柱33，且将该电子模组2a通过该些导电凸块223嵌入部分该开孔300中而设于该绝缘层30上。
于本实施例中，该绝缘层30的材质如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等的介电材。
再者，该承载板9例如为半导体材质(如硅或玻璃)的板体，其上可依需求依序形成有一离形层90与一黏着层91，以供该绝缘层30设于该黏着层91上。
另外，该导电柱33以电镀方式形成于该绝缘层30上，且形成该导电柱33的材质为如铜的金属材或焊锡材。
如图2C所示，形成一第一封装层25于该绝缘层30上，以令该第一封装层25包覆该电子模组2a与该些导电柱33，其中，该第一封装层25具有相对的第一侧25a与第二侧25b，且其以第二侧25b结合该绝缘层30。接着，通过整平制程，使该第一封装层25的第一侧25a的表面齐平该导电柱33的端面33a，令该导电柱33的端面33a与该电子模组2a的第一线路层211的电性接触垫213外露出该第一封装层25的第一侧25a。
于本实施例中，该第一封装层25为绝缘材，如聚酰亚胺(PI)、干膜(dry film)、环氧树脂(epoxy)等的封装胶体或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该绝缘层30上。
再者，该整平制程通过研磨方式，移除该导电柱33的部分材质与该第一封装层25的部分材质。
另外，该第一封装层25接触该电子模组2a的包覆层24。
如图2D所示，形成一第一布线结构31于该第一封装层25的第一侧25a上，且令该第一布线结构31电性连接该多个导电柱33与该电子模组2a的第一线路层211的多个电性接触垫213。
于本实施例中，该第一布线结构31以线路重布层(redistribution layer，简称RDL)的制作方式，其包括多个第一绝缘层310、及设于该第一绝缘层310上的多个第一布线层311，且最外层的第一绝缘层310可作为防焊层，以令最外层的第一布线层311部分外露出该防焊层。或者，该第一布线结构31亦可仅包括单一绝缘层及单一布线层。
再者，形成该第一布线层311的材质为铜，且形成该第一绝缘层310的材质为如聚对二唑苯(PBO)、聚酰亚胺(PI)、预浸材(PP)或其它等的介电材。
如图2E所示，移除该承载板9及其上的离形层90与黏着层91，以外露该绝缘层30，且使该多个导电柱33与该多个导电凸块223外露于该绝缘层30。
如图2F所示，于最外层的第一布线层311上接置多个第二电子元件29，并以一第二封装层28包覆该多个第二电子元件29，且可形成多个如焊球的导电元件27于该第一封装层25的第二侧25b上，以令该多个导电元件27电性连接该多个导电柱33及/或该电子模组2a的多个导电凸块223。
于本实施例中，可于该绝缘层30上以线路重布层(redistribution layer，简称RDL)的制作方式形成第二布线结构32，其包含第二绝缘层320及结合该第二绝缘层320与绝缘层30的第二布线层321。例如，形成该第二布线层321的材质为铜，且形成该第二绝缘层320的材质如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等的介电材，并可形成一如防焊层的绝缘保护层34于该第二绝缘层320上，且于该绝缘保护层34上形成多个开孔340，以令该第二布线层321外露出该些开孔，从而供结合该多个导电元件27，使该多个导电元件27通过该第二布线结构32电性连接该多个导电柱33及/或该电子模组2a的第二线路层221的多个导电凸块223。
进一步，最外层的第二布线层321可具有多个电性接触垫323及/或最外层的第二布线层321上可形成有凸块底下金属层(Under Bump Metallurgy，简称UBM)270，以利于结合该导电元件27。
再者，该第二电子元件29为主动元件、被动元件或其二者组合等，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。例如，该第二电子元件29为半导体芯片，如系统单芯片(System-On-Chip，简称SOC)型的功能芯片，其具有相对的作用面29a与非作用面29b，且以其作用面29a的电极垫290通过多个如焊锡材料的导电凸块291采用覆晶方式设于该第一布线层311上并电性连接该第一布线层311，并以底胶292包覆该些导电凸块291；或者，该第二电子元件29以其非作用面29b设于该第一布线结构31上，并可通过多个焊线(图略)以打线方式电性连接该第一布线层311；亦或通过如导电胶或焊锡等导电材料(图略)电性连接该第一布线层311。然而，有关该第二电子元件29电性连接该第一布线层311的方式不限于上述。
另外，该多个第二电子元件29的至少两者通过该第一布线结构31电性导通至该电子模组2a的第一线路层211的多个电性接触垫213，使该电子模组2a作为两第二电子元件29的电性接桥元件，以增加该些第二电子元件29的接点数量(即增加该电子封装件2的功能)。
另外，该第二封装层28为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dryfilm)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该第一布线结构31上。因此，该第二封装层28、第一封装层25与包覆层24的至少二者的材质可相同或相异。
进一步，可通过整平制程，如研磨方式，使该第二封装层28齐平该第二电子元件29的非作用面29b，以令该第二电子元件29的非作用面29b外露于该第二封装层28的上表面(未图示)。
应可理解地，于其它实施例中，亦可省略制作该底胶292，而依需求以该第二封装层28包覆该导电凸块291与该第二电子元件29。
如图2G所示，沿图2F中所示的切割路径S进行切单制程，以获取该电子封装件2，且于后续制程中，如图2H所示，该电子封装件2可通过该些导电元件27接置于一布线板件8的上侧，其中，该布线板件8例如有机材板体(如具有核心层与线路的封装基板(substrate)或具有线路的无核心层式(coreless)封装基板)或无机材板体(如硅板材)，且该布线板件8的下侧可接置于一如电路板的电子装置(图未示)上。
因此，本发明的制法主要通过该电子模组2a具有导电通孔23的设计，以作为该电子模组2a对外的电性传输路径，使该电子模组2a通过该导电通孔23，即可将信号传递至该第二布线结构32，故相比于现有技术，该电子模组2a对外的电性信号传输路径大幅缩短，且信号传递速度大幅增快。
再者，该电子模组2a通过配置该导电通孔23，使该包覆层24可采用大尺寸规格进行封装，因而该电子模组2a能以大尺寸规格进行设计，以于该包覆层24上进行RDL制程，且第一线路结构21的配线设计不会受限于该第一电子元件20的尺寸，因而能将各层的第一导电盲孔212采用错位设计，以避免应力集中的现象，故相比于现有技术，该第一线路结构21能有效避免因应力分布不均而发生碎裂的问题。
应可理解地，由于该电子模组2a的第一线路结构21可依需求进行配线设计，故该第一布线结构31更能于该第一封装层25上依需求进行配线设计，完全不受限于该电子模组2a的尺寸，因而该第一布线结构31不会发生如现有因应力分布不均而发生碎裂的问题。
另外，将作为辅助功能的电子模组2a嵌埋于该第一封装层25中以对接该第二电子元件29，以利于配合不同功能的第二电子元件29。
另外，本发明的第二电子元件29的部分电性功能(如电源或接地)可通过电子模组2a的导电通孔23作为电性传输路径。
本发明还提供一种电子封装件2，包括：一第一封装层25、多个导电柱33、至少一电子模组2a、第一布线结构31以及多个第二电子元件29，且该电子模组2a包含有一包覆层24、第一电子元件20、多个导电通孔23及一第一线路结构21。
所述的第一封装层25具有相对的第一侧25a与第二侧25b。
所述的导电柱33嵌埋于该第一封装层25中并连通该第一封装层25的第一侧25a与第二侧25b。
所述的电子模组2a嵌埋于该第一封装层25中。
所述的包覆层24具有相对的第一表面24a与第二表面24b。
所述的第一电子元件20嵌埋于该包覆层24中。
所述的导电通孔23嵌埋于该包覆层24中并连通该第一表面24a与第二表面24b。
所述的第一线路结构21形成于该包覆层24的第一表面24a上以电性连接该第一电子元件20与该多个导电通孔23。
所述的第一布线结构31设于该第一封装层25的第一侧25a上并电性连接该多个导电柱33与该电子模组2a的第一线路结构21。
所述的第二电子元件29设于该第一布线结构31上并电性连接该第一布线结构31，其中，该多个第二电子元件29的至少两者通过该第一布线结构31电性导通至该电子模组2a，使该电子模组2a电性桥接该多个第二电子元件29的至少两者。
于一实施例中，该电子模组2a的包覆层24的第二表面24b上形成有第二线路结构22，以令该多个导电通孔23电性连接该第二线路结构22。
于一实施例中，该电子模组2a的第一电子元件20具有相对的作用面20a与非作用面20b，且其作用面20a具有多个电性连接该第一线路结构21的电极垫200。
于一实施例中，该第二电子元件29通过多个导电凸块291电性连接该第一布线结构31。
于一实施例中，所述的电子封装件2还包括包覆该多个第二电子元件29的第二封装层28。
于一实施例中，所述的电子封装件2还包括形成于该第一封装层25的第二侧25b上的第二布线结构32，以令该多个导电柱33电性连接该第二布线结构32。例如，该第二布线结构32包含至少一第二绝缘层320及至少一结合该第二绝缘层320的第二布线层321，且最外层的第二布线层321具有电性接触垫322或凸块底下金属层270。
于一实施例中，所述的电子封装件2还包括形成于该第一封装层25的第二侧25b上的多个导电元件27，其电性连接该多个导电柱33及/或该电子模组2a。例如，该电子封装件2通过该多个导电元件27接置于一布线板件8上。
于一实施例中，该电子模组2a的第一线路结构21包含多个错位的导电盲孔212。
综上所述，本发明的电子封装件及其制法，通过该电子模组具有导电通孔的设计，以作为该电子模组对外的电性传输路径，故该电子模组对外的电性信号传输路径能大幅缩短，且信号传递速度能大幅增快。
再者，该电子模组通过配置该导电通孔，使该电子模组能以大尺寸规格进行封装设计，以于该包覆层上进行RDL制程，且第一线路结构的配线设计不会受限于该第一电子元件的尺寸，故能将各层的第一导电盲孔采用错位设计，以避免应力集中的现象，使该第一线路结构能有效避免因应力分布不均而发生碎裂的问题。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (18)

1.一种电子封装件，包括：
第一封装层，其具有相对的第一侧与第二侧；
多个导电柱，其嵌埋于该第一封装层中并连通该第一封装层的第一侧与第二侧；
电子模组，其嵌埋于该第一封装层中且包含：
包覆层，其具有相对的第一表面与第二表面；
第一电子元件，其嵌埋于该包覆层中；
多个导电通孔，其嵌埋于该包覆层中并连通该第一表面与第二表面；及
第一线路结构，其形成于该包覆层的第一表面上以电性连接该第一电子元件与该多个导电通孔；
第一布线结构，其设于该第一封装层的第一侧上并电性连接该多个导电柱与该电子模组的第一线路结构；以及
多个第二电子元件，其设于该第一布线结构上并电性连接该第一布线结构，其中，该多个第二电子元件的至少两者通过该第一布线结构电性导通至该电子模组，使该电子模组电性桥接该多个第二电子元件的至少两者。
2.如权利要求1所述的电子封装件，其中，该电子模组的包覆层的第二表面上形成有第二线路结构，以令该多个导电通孔电性连接该第二线路结构。
3.如权利要求1所述的电子封装件，其中，该电子模组的第一电子元件具有相对的作用面与非作用面，且其作用面具有多个电性连接该第一线路结构的电极垫。
4.如权利要求1所述的电子封装件，其中，该第二电子元件通过多个导电凸块电性连接该第一布线结构。
5.如权利要求1所述的电子封装件，其中，还包括包覆该多个第二电子元件的第二封装层。
6.如权利要求1所述的电子封装件，其中，还包括形成于该第一封装层的第二侧上的第二布线结构，以令该多个导电柱电性连接该第二布线结构。
7.如权利要求6所述的电子封装件，其中，该第二布线结构包含至少一绝缘层及至少一结合该绝缘层的布线层，且最外层的布线层具有电性接触垫或凸块底下金属层。
8.如权利要求1所述的电子封装件，其中，还包括形成于该第一封装层的第二侧上的多个导电元件，其电性连接该多个导电柱及/或该电子模组。
9.如权利要求1所述的电子封装件，其中，该电子模组的第一线路结构包含多个错位的导电盲孔。
10.一种电子封装件的制法，包括：
提供一电子模组，其包含有一包覆层、嵌埋于该包覆层中的第一电子元件与多个导电通孔、及形成于该包覆层上的第一线路结构，且该第一线路结构电性连接该第一电子元件与该多个导电通孔；
将该电子模组设于一承载板上，且于该承载板上形成有多个导电柱；
形成第一封装层于该承载板上，以包覆该电子模组与多个导电柱，其中，该第一封装层具有相对的第一侧与第二侧，且该第一封装层以其第二侧结合该承载板；
移除该承载板；
形成第一布线结构于该第一封装层的第一侧上，以令该第一布线结构电性连接该多个导电柱与该电子模组的第一线路结构；以及
将多个第二电子元件设于该第一布线结构上并电性连接该第一布线结构，其中，该多个第二电子元件的至少两者通过该第一布线结构电性导通至该电子模组，使该电子模组电性桥接该多个第二电子元件的至少两者。
11.如权利要求10所述的电子封装件的制法，其中，该电子模组的包覆层具有相对的第一表面与第二表面，以于该第一表面上形成该第一线路结构，且于该第二表面上形成第二线路结构，以令该多个导电通孔电性连接该第二线路结构。
12.如权利要求10所述的电子封装件的制法，其中，该电子模组的第一电子元件具有相对的作用面与非作用面，且其作用面具有多个电性连接该第一线路结构的电极垫。
13.如权利要求10所述的电子封装件的制法，其中，该第二电子元件通过多个导电凸块电性连接该第一布线结构。
14.如权利要求10所述的电子封装件的制法，其中，还包括以第二封装层包覆该多个第二电子元件。
15.如权利要求10所述的电子封装件的制法，其中，还包括于移除该承载板后，于该第一封装层的第二侧上形成第二布线结构，以令该多个导电柱电性连接该第二布线结构。
16.如权利要求15所述的电子封装件的制法，其中，该第二布线结构包含至少一绝缘层及至少一结合该绝缘层的布线层，且最外层的布线层具有电性接触垫或凸块底下金属层。
17.如权利要求10所述的电子封装件的制法，其中，还包括形成多个导电元件于该第一封装层的第二侧上，以令该多个导电元件电性连接该多个导电柱及/或该电子模组。
18.如权利要求10所述的电子封装件的制法，其中，该电子模组的第一线路结构包含多个错位的导电盲孔。
CN202210554028.4A 2022-05-13 2022-05-20 电子封装件及其制法 Pending CN117116895A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW111118103A TWI807827B (zh) 2022-05-13 2022-05-13 電子封裝件及其製法
TW111118103 2022-05-13

Publications (1)

Publication Number Publication Date
CN117116895A true CN117116895A (zh) 2023-11-24

Family

ID=88149259

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210554028.4A Pending CN117116895A (zh) 2022-05-13 2022-05-20 电子封装件及其制法

Country Status (3)

Country Link
US (1) US20230369229A1 (zh)
CN (1) CN117116895A (zh)
TW (1) TWI807827B (zh)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9601463B2 (en) * 2014-04-17 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) and the methods of making the same
US20160343685A1 (en) * 2015-05-21 2016-11-24 Mediatek Inc. Semiconductor package assembly and method for forming the same
US10032756B2 (en) * 2015-05-21 2018-07-24 Mediatek Inc. Semiconductor package assembly with facing active surfaces of first and second semiconductor die and method for forming the same
US20170338204A1 (en) * 2016-05-17 2017-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Device and Method for UBM/RDL Routing
KR20210157781A (ko) * 2020-06-22 2021-12-29 삼성전자주식회사 반도체 패키지
CN115547981A (zh) * 2021-06-30 2022-12-30 联发科技股份有限公司 半导体封装结构

Also Published As

Publication number Publication date
TW202345322A (zh) 2023-11-16
US20230369229A1 (en) 2023-11-16
TWI807827B (zh) 2023-07-01

Similar Documents

Publication Publication Date Title
CN111952274B (zh) 电子封装件及其制法
CN114121869A (zh) 电子封装件及其制法
CN111987048A (zh) 电子封装件及其制法
TWI728936B (zh) 電子封裝件及其製法
US20230395571A1 (en) Electronic package and manufacturing method thereof
CN115312487A (zh) 电子封装件及其制法
CN217062063U (zh) 堆叠封装体
TWI753561B (zh) 電子封裝件及其製法
CN117153805A (zh) 电子封装件及其制法
CN117116895A (zh) 电子封装件及其制法
TWI832571B (zh) 電子封裝件及其製法
TWI825790B (zh) 電子封裝件及其製法
TWI847335B (zh) 電子封裝件及其製法
TWI819440B (zh) 電子封裝件及其製法
TWI778406B (zh) 電子封裝件及其製法
US20230343691A1 (en) Electronic package
US20240145455A1 (en) Electronic package and manufacturing method thereof
CN117672984A (zh) 电子封装件及其制法
CN118039572A (zh) 电子封装件及其制法
CN117673031A (zh) 电子封装件及其制法
CN116682802A (zh) 电子封装件及其制法
CN116759410A (zh) 电子封装件及其制法
CN117558689A (zh) 电子封装件及其制法与电子结构及其制法
CN116798962A (zh) 电子封装件及其制法
CN118280958A (zh) 电子封装件及其制法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination