TWI832571B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

Info

Publication number
TWI832571B
TWI832571B TW111144450A TW111144450A TWI832571B TW I832571 B TWI832571 B TW I832571B TW 111144450 A TW111144450 A TW 111144450A TW 111144450 A TW111144450 A TW 111144450A TW I832571 B TWI832571 B TW I832571B
Authority
TW
Taiwan
Prior art keywords
component
electronic
semiconductor substrate
conductors
electronic package
Prior art date
Application number
TW111144450A
Other languages
English (en)
Other versions
TW202422841A (zh
Inventor
邱志賢
蔡文榮
張克維
林建成
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW111144450A priority Critical patent/TWI832571B/zh
Priority to CN202211493052.8A priority patent/CN118099136A/zh
Priority to US18/173,883 priority patent/US20240170355A1/en
Application granted granted Critical
Publication of TWI832571B publication Critical patent/TWI832571B/zh
Publication of TW202422841A publication Critical patent/TW202422841A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

一種電子封裝件，係於承載結構上設置電子元件，且將中介元件堆疊於該電子元件上，以令導線連接該中介元件及接地該承載結構，使該導線與該中介元件圍繞該電子元件，故於該電子封裝件運作時，該導線能作為屏蔽元件，以避免該電子元件遭受外界之電磁干擾。

Description

電子封裝件及其製法
本發明係有關一種半導體封裝技術，尤指一種可防電磁干擾之電子封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足電子產品及設於其中之電子封裝件微型化(miniaturization)的需求，遂發展出晶片尺寸封裝(Chip Scale Package，簡稱CSP)之技術，其特徵在於此種晶片尺寸封裝之封裝結構僅具有與晶片尺寸相等或略大之尺寸。
圖1A至圖1E係為習知晶片尺寸封裝之半導體封裝件1之製法之剖面示意圖。
如圖1A所示，形成一熱化離形膠層(thermal release tape)100於一承載件10上。
接著，置放複數半導體元件11於該熱化離形膠層100上，該些半導體元件11具有相對之作用面11a與非作用面11b，各該作用面11a上均具有複數電極墊110，且各該作用面11a黏著於該熱化離形膠層100上。
如圖1B所示，形成一封裝膠體14於該熱化離形膠層100上，以包覆該複數半導體元件11。
如圖1C所示，烘烤該封裝膠體14以硬化該熱化離形膠層100，並移除該熱化離形膠層100與該承載件10，以外露出該半導體元件11之作用面1la。
如圖1D所示，形成一線路結構16於該封裝膠體14與該半導體元件11之作用面11a上，令該線路結構16電性連接該複數電極墊110。接著，形成一絕緣保護層18於該線路結構16上，且該絕緣保護層18外露該線路結構16之部分表面，以供結合如銲球之導電元件17。
如圖1E所示，沿如圖1D所示之切割路徑L進行切單製程，以獲取複數個半導體封裝件1。
惟，習知半導體封裝件1於運作時，該半導體元件11對於外界電磁波非常敏感，不僅會使該半導體元件11無法進行正常運作，且外界電磁波亦有可能損毀該半導體元件11。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：具有佈線層之承載結構；電子元件，係設於該承載結構上並電性連接該佈線層；中介元件，係堆疊於該電子元件上且包含有一半導體基板，該半導體基板係具有相對之第一表面與第二表面，以令該半導體基板以其第二表面結合於 該電子元件上，其中，該半導體基板之第一表面上係配置有複數第一接點及至少一第二接點，並於該複數第一接點上形成複數導電體；以及至少一導線，係連接該至少一第二接點與該承載結構並接地該承載結構。
本發明亦提供一種電子封裝件之製法，係包括：提供一具有佈線層之承載結構、一電子元件及一包含有一半導體基板之中介元件，其中，該半導體基板係具有相對之第一表面與第二表面，且該半導體基板之第一表面上係配置有複數第一接點及至少一第二接點，並於該複數第一接點上形成複數導電體；將該電子元件與該中介元件設於該承載結構上，且該中介元件堆疊於該電子元件上，其中，該電子元件係電性連接該佈線層，且該半導體基板以其第二表面結合於該電子元件上；以及將至少一導線連接該至少一第二接點與該承載結構，並使該至少一導線接地該承載結構。
於一實施例中，該中介元件復包含有一結合於該半導體基板之第一表面上的佈線結構，以令該複數第一接點及該第二接點佈設於該佈線結構上。
於一實施例中，該中介元件復包含有一結合該電子元件之金屬層。例如，該金屬層係位於該中介元件之半導體基板之第二表面上。
於一實施例中，該半導體基板係具有至少一連通該第一表面與第二表面之導電穿孔，以令該導電穿孔藉由該第二接點接地該導線。
於一實施例中，該至少一第二接點係為複數第二接點，且該至少一導線係為複數導線，以令該複數導線之至少其中一者係通訊連接該複數第二接點之至少其中一者與該承載結構，且該複數導線之另一者係接地連接該複數第二接點之另一者與該承載結構。
於一實施例中，該中介元件之寬度係大於該電子元件之寬度。
於一實施例中，復包括形成包覆層於該承載結構上，以令該包覆層包覆該電子元件、中介元件及導線。例如，該導電體與該包覆層係共平面。又可包括形成線路結構於該包覆層上，以令該線路結構電性連接該中介元件之導電體。
由上可知，本發明之電子封裝件及其製法中，主要藉由該導線連接該中介元件及接地該承載結構，以圍繞該電子元件，故相較於習知技術，本發明之電子封裝件於運作時，該導線能作為屏蔽元件，以避免該電子元件遭受外界之電磁干擾，使該電子元件得以進行正常運作及避免該電子元件之損毀，因而使該電子封裝件能有效維持產品之正常運作，以提升產品之可靠性。
1:半導體封裝件
10:承載件
100:熱化離形膠層
11:半導體元件
11a,21a:作用面
11b,21b:非作用面
110,210,221,310:電極墊
14:封裝膠體
16,26:線路結構
17,27:導電元件
18:絕緣保護層
2:電子封裝件
2a:中介元件
2b:屏蔽結構
20:承載結構
20a:第一側
20b:第二側
200,201:電性接觸墊
202:植球墊
21:電子元件
211:導電凸塊
212,380:銲錫材料
22:半導體基板
22a:第一表面
22b:第二表面
220,320:導電穿孔
23:佈線結構
230:絕緣層
231:線路重佈層
232:第一接點
233:第二接點
234:導電體
24a,24b:導線
25:包覆層
25a:表面
260:介電層
261:線路層
270:凸塊底下金屬層
28:金屬層
280:結合層
29:被動元件
311:導電通孔
312,321:銅墊
381,382:銅凸塊
4:電子裝置
D1,D2:寬度
L,S:切割路徑
圖1A至圖1E係為習知半導體封裝件之製法之剖面示意圖。
圖2A至圖2E係為本發明之電子封裝件之製法的剖面示意圖。
圖2F係為圖2E之後續製程之剖視示意圖。
圖3A及圖3B係為圖2E之其它實施例的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例 關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2E係為本發明之電子封裝件2之製法的剖面示意圖。
如圖2A所示，提供一中介元件(interposer)2a，其包含有一半導體基板22、一金屬層28及一佈線結構23。
所述之半導體基板22係具有相對之第一表面22a與第二表面22b，且該第一表面22a上設有複數電極墊221。
於本實施例中，該半導體基板22係具有至少一連通該第一表面22a與第二表面22b之導電穿孔220，如導電矽穿孔(Through Silicon Via，簡稱TSV)，以令部分電極墊221電性連接該導電穿孔220。
所述之金屬層28係形成於該半導體基板22之第二表面22b上，以接觸及電性連接該導電穿孔220。
於本實施例中，該金屬層28係為銅層，可採用如濺鍍(sputtering)、蒸鍍(vaporing)、電鍍、無電電鍍或化鍍等方式形成於該半導體基板22之第二表面22b上；或者，該金屬層28可利用銅片或貼膜(foiling)式薄膜等設置方式固定於該半導體基板22之第二表面22b上。
所述之佈線結構23係形成於該半導體基板22之第一表面22a上以電性連接該些電極墊221。
於本實施例中，該佈線結構23係包括複數絕緣層230、及設於該絕緣層230上並電性連接該些電極墊221之複數線路重佈層(Redistribution layer，簡稱RDL)231。例如，形成該線路重佈層231之材質係為銅，且形成該絕緣層230之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它介電材。
再者，該佈線結構23於最外層之線路重佈層231上可具有外露於該絕緣層230之複數第一接點232及至少一第二接點233，以令該些第一接點232上結合如銅柱或錫球之凸塊狀導電體234。
如圖2B所示，將該中介元件2a、至少一電子元件21與至少一被動元件29設於一承載結構20上，以令該電子元件21與被動元件29電性連接該承載結構20，且該中介元件2a係以其金屬層28堆疊結合於該電子元件21上。之後，利用導線24a,24b連接該第二接點233與該承載結構20，使該中介元件2a電性連接該承載結構20。
所述之承載結構20係為封裝用載板形式，例如為具有核心層與線路結構之封裝基板、無核心層(coreless)形式線路結構之封裝基板、具導電矽穿孔(Through-silicon via，簡稱TSV)之矽中介板(Through Silicon interposer，簡稱TSI)或其它板型，其包含至少一佈線層，如至少一扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)。應可理解地，該承載結構20亦可為其它承載晶片之板材，如導線架(lead frame)、晶圓(wafer)、或其它具有金屬佈線(routing)之板體等，並不限於上述。
於本實施例中，該承載結構20係定義有相對之第一側20a與第二側20b，且該承載結構20係於其第一側20a上之佈線層具有複數電性接觸墊 200,201，並於該第二側20b上之佈線層配置有複數植球墊202，其中，形成該電性接觸墊200,201與該植球墊202之材質係為如銅材之金屬材。應可理解地，該承載結構20內部具有複數線路層(圖略))，以電性連接該些電性接觸墊200,201與該植球墊202。
所述之電子元件21係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
於本實施例中，該電子元件21係為半導體晶片，如微控制器(Microcontroller Unit，簡稱MCU)或特殊應用積體電路(Application Specific Integrated Circuit，簡稱ASIC)，其具有相對之作用面21a與非作用面21b，該作用面21a具有複數電極墊210，且該電子元件21以覆晶方式藉由複數可含銲錫材料212之導電凸塊211接置於部分該電性接觸墊200上以電性連接該承載結構20。應可理解地，有關電子元件21電性連接該承載結構20之方式繁多，如打線方式，並不限於上述。
所述之被動元件29係例如電阻、電容及電感，但不限於上述者，其亦電性連接部分該電性接觸墊200。
所述之導線24a,24b係為複數條打線製程用之銲線(如金線或銅線)，其中一部分之導線24b係通訊連接其中一部分之第二接點233與該承載結構20之其中一部分電性接觸墊201，且另一部分之導線24a係接地連接另一部分之第二接點233與該承載結構20之另一部分電性接觸墊201。
於本實施例中，該導線24a係藉由該線路重佈層231及其第二接點233接地該導電穿孔220，使該金屬層28接地該承載結構20。
另外，該中介元件2a係以其上金屬層28藉由一如黏膠之結合層280黏固於該電子元件21之非作用面21b上。例如，先於該中介元件2a之金屬層28上形成該結合層280，如圖2A所示，再將該中介元件2a黏固於該承載結構20上之電子元件21上。應可理解地，亦可先於該電子元件21上形成該結合層280，再將該中介元件2a黏固於該結合層280上。或者，先將該中介元件2a以該結合層280黏固於該電子元件21上，再將連接有該中介元件2a之電子元件21結合至該承載結構20之第一側20a上。
如圖2C所示，形成一包覆層25於該承載結構20之第一側20a上，以令該包覆層25包覆該電子元件21、被動元件29、導線24a,24b與該中介元件2a，且令該中介元件2a之導電體234之端面外露於該包覆層25。
於本實施例中，該包覆層25係為絕緣材，如聚醯亞胺、乾膜、如環氧樹脂之封裝膠體或封裝材，其可用壓合或模壓之方式形成於該承載結構20之第一側20a上。
再者，可藉由整平製程，如蝕刻或研磨方式，移除該包覆層25之部分材質，甚至該導電體234之部分材質，使該導電體234之端面與該包覆層25之上表面共平面，即該包覆層25之上表面25a齊平該導電體234之端面。應可理解地，該包覆層25外露該導電體234之方式並不限於採用整平製程之方式，例如，可於該包覆層25上形成外露該導電體234之開孔。
又，該導線24a,24b未外露於該包覆層25；然而，於其它實施例中，該導線24a,24b可外露於該包覆層25。
如圖2D所示，形成一線路結構26於該包覆層25上，且令該線路結構26電性連接該些導電體234。
於本實施例中，該線路結構26係包括複數介電層260及設於該介電層260上之複數如RDL規格之線路層261，以令該線路層261電性連接該些導電體234。例如，形成該線路層261之材質係為銅，且形成該介電層260之材質係為如聚對二唑苯(PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)之介電材。
再者，該導線24a,24b未接觸該線路結構26；然而，於其它實施例中，該導線24a,24b可接觸該介電層260而未接觸該線路層261。
如圖2E所示，沿如圖2D所示之切割路徑S進行切單製程，以完成本發明之電子封裝件2。
於後續製程中，可形成複數如銲球之導電元件27於該線路結構26最外層之線路層261上，俾供後續接置如封裝結構或其它結構(如另一封裝件或晶片)之電子裝置4(如圖2F所示)。另可形成一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)270於該線路結構26最外層之線路層261上，以利於結合該導電元件27。
再者，該中介元件2a亦可藉由導電材堆疊於該電子元件21之非作用面21b上。例如，如圖3A所示，該半導體基板22之部分導電穿孔320之端面上形成有銅凸塊382，以令該銅凸塊382未接觸及未電性連接該金屬層28，且該電子元件21復具有至少一連通該作用面21a與非作用面21b之導電通孔311，以令該導電通孔311電性連接部分電極墊310，且該導電通孔311於非作用面21b上之端面亦形成有銅凸塊381，再將該中介元件2a之銅凸塊382接觸抵靠該電子元件21之銅凸塊381，使該中介元件2a與該電子元件21電性導通。
或者，如圖3B所示，該半導體基板22之部分導電穿孔320之端面上形成有銅墊321，以令該銅墊321未接觸及未電性連接該金屬層28，且該電子元件21之導電通孔311於非作用面21b上之端面亦形成有銅墊312，再將該中介元件2a之銅墊321藉由銲錫材料380結合該電子元件21之銅墊312，使該中介元件2a與該電子元件21電性導通。
另外，亦可形成複數如銲球之導電元件27於該承載結構20之第二側20b之植球墊202上，俾供後續接置如封裝結構或其它結構(如電路板、另一封裝件或晶片)之電子裝置(圖略)。
因此，本發明之電子封裝件2之製法係藉由該導線24a,24b連接該中介元件2a與該承載結構20，以圍繞該電子元件21，並使該導線24a接地該承載結構20，故相較於習知技術，本發明之電子封裝件2於運作時，非通訊用之導線24a能作為屏蔽元件，以避免該電子元件21遭受外界之電磁干擾，使該電子元件21得以進行正常運作及避免該電子元件21之損毀，因而使該電子封裝件2能有效維持產品之正常運作，以提升產品之可靠性。
再者，該金屬層28與該導線24a可形成一環繞該電子元件21周圍之屏蔽結構2b，以於該電子封裝件2運作時，該屏蔽結構2b能保護該電子元件21免於遭受外界之電磁干擾，使該電子元件21得以進行正常運作及避免該電子元件21之損毀。
又，該中介元件2a之寬度D1可大於該電子元件21之寬度D2，以利於進行該導線24a,24b之打線作業。
另外，該中介元件2a亦可藉由該些導電體234與通訊用之導線24b傳輸訊號於該承載結構20與該線路結構26之間，以增加該電子封裝件2之功能需求。
本發明復提供一種電子封裝件2，係包括：一具有佈線層之承載結構20、至少一電子元件21、至少一中介元件2a以及至少一導線24a,24b；
所述之承載結構20係具有相對之第一側20a與第二側20b，且該第一側20a上之佈線層係具有複數電性接觸墊200,201。
所述之電子元件21係設於該承載結構20上並電性連接該佈線層之部分電性接觸墊200。
所述之中介元件2a係堆疊於該電子元件21上且包含有一半導體基板22，該半導體基板22係具有相對之第一表面22a與第二表面22b，以令該半導體基板22以其第二表面22b結合於該電子元件21上，其中，該半導體基板22之第一表面22a上係配置有複數第一接點232及至少一第二接點233，並於該複數第一接點232上形成複數導電體234。
所述之導線24a,24b係連接該第二接點233與該承載結構20之部分電性接觸墊201並使該導線24a接地該承載結構20之部分電性接觸墊201。
於一實施例中，該中介元件2a復包含有一結合於該半導體基板22之第一表面22a上的佈線結構23，以令該複數第一接點232及該第二接點233佈設於該佈線結構23上。
於一實施例中，該中介元件2a復包含有一結合該電子元件21之金屬層28。例如，該金屬層28係位於該中介元件2a之半導體基板22之第二表面22b上。
於一實施例中，該半導體基板22係具有至少一連通該第一表面22a與第二表面22b之導電穿孔220，以令該導電穿孔220藉由該第二接點233接地該導線24a。
於一實施例中，該至少一第二接點233係為複數第二接點233，且該至少一導線24a,24b係為複數導線24a,24b，以令部分該複數導線24b係通訊連接該複數第二接點233之至少其中一者與該承載結構20，且部分該複數導線24a係接地連接該複數第二接點233之另一者與該承載結構20。
於一實施例中，該中介元件2a之寬度D1係大於該電子元件21之寬度D2。
於一實施例中，所述之電子封裝件2復包括一形成於該承載結構20第一側20a上之包覆層25，以令該包覆層25包覆該電子元件21、中介元件2a及導線24a,24b。例如，該導電體234之端面與該包覆層25之上表面係共平面。進一步，所述之電子封裝件2復包括形成於該包覆層25上之線路結構26，以電性連接該中介元件2a之導電體234。
綜上所述，本發明之電子封裝件及其製法，係藉由該導線連接該中介元件及接地該承載結構，以圍繞該電子元件，故本發明之電子封裝件於運作時，該導線能作為屏蔽元件，以避免該電子元件遭受外界之電磁干擾，使該電子元件得以進行正常運作及避免該電子元件之損毀，因而使該電子封裝件能有效維持產品之正常運作，以提升產品之可靠性。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對 上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2a:中介元件
20:承載結構
21:電子元件
24a:導線
25:包覆層
26:線路結構
27:導電元件
4:電子裝置

Claims (18)

  1. 一種電子封裝件，係包括：具有佈線層之承載結構；電子元件，係設於該承載結構上並電性連接該佈線層；中介元件，係堆疊於該電子元件上且包含有一半導體基板，該半導體基板係具有相對之第一表面與第二表面，以令該半導體基板以其第二表面結合於該電子元件上，其中，該半導體基板之第一表面上係配置有複數第一接點及至少一第二接點，並於該複數第一接點上形成複數導電體；以及至少一導線，係連接該至少一第二接點與該承載結構並接地該承載結構；其中，該中介元件復包含有一結合該電子元件之金屬層。
  2. 如請求項1所述之電子封裝件，其中，該中介元件復包含有一結合於該半導體基板之第一表面上的佈線結構，以令該複數第一接點及該至少一第二接點佈設於該佈線結構上。
  3. 如請求項1所述之電子封裝件，其中，該金屬層係位於該中介元件之半導體基板之第二表面上。
  4. 如請求項1所述之電子封裝件，其中，該半導體基板係具有至少一連通該第一表面與第二表面之導電穿孔，以令該導電穿孔藉由該至少一第二接點接地該導線。
  5. 如請求項1所述之電子封裝件，其中，該至少一第二接點係為複數第二接點，且該至少一導線係為複數導線，以令部分該複數導線係通訊連接該複數第二接點之至少其中一者與該承載結構，且部分該複數導線係接地連接該複數第二接點之另一者與該承載結構。
  6. 如請求項1所述之電子封裝件，其中，該中介元件之寬度係大於該電子元件之寬度。
  7. 如請求項1所述之電子封裝件，復包括形成於該承載結構上之包覆層，以令該包覆層包覆該電子元件、中介元件及導線。
  8. 如請求項7所述之電子封裝件，其中，該複數導電體之端面與該包覆層之上表面係共平面。
  9. 如請求項7所述之電子封裝件，復包括形成於該包覆層上之線路結構，以電性連接該中介元件之複數導電體。
  10. 一種電子封裝件之製法，係包括：提供一具有佈線層之承載結構、一電子元件及一包含有一半導體基板之中介元件，其中，該半導體基板係具有相對之第一表面與第二表面，且該半導體基板之第一表面上係配置有複數第一接點及至少一第二接點，並於該複數第一接點上形成複數導電體；將該電子元件與該中介元件設於該承載結構上，且該中介元件堆疊於該電子元件上，其中，該電子元件係電性連接該佈線層，且該半導體基板以其第二表面結合於該電子元件上；以及將至少一導線連接該至少一第二接點與該承載結構，並使該至少一導線接地該承載結構；其中，該中介元件復包含有一結合該電子元件之金屬層。
  11. 如請求項10所述之電子封裝件之製法，其中，該中介元件復包含有一結合於該半導體基板之第一表面上的佈線結構，以令該複數第一接點及該至少一第二接點佈設於該佈線結構上。
  12. 如請求項10所述之電子封裝件之製法，其中，該金屬層係位於該中介元件之半導體基板之第二表面上。
  13. 如請求項10所述之電子封裝件之製法，其中，該半導體基板係具有至少一連通該第一表面與第二表面之導電穿孔，以令該導電穿孔藉由該至少一第二接點接地該導線。
  14. 如請求項10所述之電子封裝件之製法，其中，該至少一第二接點係為複數第二接點，且該至少一導線係為複數導線，以令該複數導線之至少其中一者係通訊連接該複數第二接點之至少其中一者與該承載結構，且該複數導線之另一者係接地連接該複數第二接點之另一者與該承載結構。
  15. 如請求項10所述之電子封裝件之製法，其中，該中介元件之寬度係大於該電子元件之寬度。
  16. 如請求項10所述之電子封裝件之製法，復包括形成包覆層於該承載結構上，以令該包覆層包覆該電子元件、中介元件及導線。
  17. 如請求項16所述之電子封裝件之製法，其中，該複數導電體之端面與該包覆層之上表面係共平面。
  18. 如請求項16所述之電子封裝件之製法，復包括形成線路結構於該包覆層上，以令該線路結構電性連接該中介元件之複數導電體。
TW111144450A 2022-11-21 2022-11-21 電子封裝件及其製法 TWI832571B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW111144450A TWI832571B (zh) 2022-11-21 2022-11-21 電子封裝件及其製法
CN202211493052.8A CN118099136A (zh) 2022-11-21 2022-11-25 电子封装件及其制法
US18/173,883 US20240170355A1 (en) 2022-11-21 2023-02-24 Electronic package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW111144450A TWI832571B (zh) 2022-11-21 2022-11-21 電子封裝件及其製法

Publications (2)

Publication Number Publication Date
TWI832571B true TWI832571B (zh) 2024-02-11
TW202422841A TW202422841A (zh) 2024-06-01

Family

ID=90824916

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111144450A TWI832571B (zh) 2022-11-21 2022-11-21 電子封裝件及其製法

Country Status (3)

Country Link
US (1) US20240170355A1 (zh)
CN (1) CN118099136A (zh)
TW (1) TWI832571B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230282586A1 (en) * 2022-03-04 2023-09-07 Siliconware Precision Industries Co., Ltd. Electronic package and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW454989U (en) * 1998-05-19 2001-09-11 Molex Inc Integrated circuit test socket
US20060097402A1 (en) * 2004-11-08 2006-05-11 Siliconware Precision Industries Co., Ltd. Semiconductor device having flip-chip package and method for fabricating the same
TW200901411A (en) * 2007-06-20 2009-01-01 Stats Chippac Ltd Wafer level integration package
TW202036739A (zh) * 2019-03-28 2020-10-01 台灣積體電路製造股份有限公司 封裝結構及其形成方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW454989U (en) * 1998-05-19 2001-09-11 Molex Inc Integrated circuit test socket
US20060097402A1 (en) * 2004-11-08 2006-05-11 Siliconware Precision Industries Co., Ltd. Semiconductor device having flip-chip package and method for fabricating the same
TW200901411A (en) * 2007-06-20 2009-01-01 Stats Chippac Ltd Wafer level integration package
TW202036739A (zh) * 2019-03-28 2020-10-01 台灣積體電路製造股份有限公司 封裝結構及其形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230282586A1 (en) * 2022-03-04 2023-09-07 Siliconware Precision Industries Co., Ltd. Electronic package and manufacturing method thereof

Also Published As

Publication number Publication date
US20240170355A1 (en) 2024-05-23
CN118099136A (zh) 2024-05-28
TW202422841A (zh) 2024-06-01

Similar Documents

Publication Publication Date Title
CN111952274B (zh) 电子封装件及其制法
TW202101713A (zh) 電子封裝件及其製法
US9548283B2 (en) Package redistribution layer structure and method of forming same
TWI765778B (zh) 電子封裝件及其製法
CN107403785B (zh) 电子封装件及其制法
US20230343691A1 (en) Electronic package
CN111987048A (zh) 电子封装件及其制法
TWI832571B (zh) 電子封裝件及其製法
US20160079148A1 (en) Substrate structure and method of manufacturing the same
US20230411364A1 (en) Electronic package and manufacturing method thereof
TWI712149B (zh) 電子封裝件及其製法
US20240047420A1 (en) Electronic package and manufacturing method thereof, and electronic structure and manufacturing method thereof
TWI827335B (zh) 電子封裝件及其製法
TWI807827B (zh) 電子封裝件及其製法
US20230268262A1 (en) Electronic package and manufacturing method thereof
TWI766192B (zh) 電子封裝件及其製法
TW202333311A (zh) 電子封裝件及其製法
TW202029448A (zh) 電子封裝件及其封裝基板與製法
TWI815639B (zh) 電子封裝件及其製法
TWI818458B (zh) 電子封裝件及其製法
TWI831241B (zh) 電子封裝件及其製法
CN111354686B (zh) 电子封装件及其制法暨封装用基板及其制法
CN217641291U (zh) 封装模组
US20240071939A1 (en) Semiconductor structure and manufacturing method thereof
TW202407955A (zh) 電子封裝件及其製法