TWI825790B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

Info

Publication number
TWI825790B
TWI825790B TW111122668A TW111122668A TWI825790B TW I825790 B TWI825790 B TW I825790B TW 111122668 A TW111122668 A TW 111122668A TW 111122668 A TW111122668 A TW 111122668A TW I825790 B TWI825790 B TW I825790B
Authority
TW
Taiwan
Prior art keywords
electronic
conductive
package
electrically connected
module
Prior art date
Application number
TW111122668A
Other languages
English (en)
Other versions
TW202401684A (zh
Inventor
黃柏凱
李泳達
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW111122668A priority Critical patent/TWI825790B/zh
Priority to CN202210749644.5A priority patent/CN117316884A/zh
Priority to US18/310,072 priority patent/US20230411364A1/en
Application granted granted Critical
Publication of TWI825790B publication Critical patent/TWI825790B/zh
Publication of TW202401684A publication Critical patent/TW202401684A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5381—Crossover interconnections, e.g. bridge stepovers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一種電子封裝件，係將電子模組與封裝模組相互堆疊，該電子模組係包括一橋接組件、複數導電柱以及一包覆該橋接組件與該複數導電柱之包覆層，且該封裝模組係包括有一線路結構及複數設於該線路結構上之電子元件，以將該封裝模組藉由複數支撐元件堆疊於該電子模組上，並使該複數電子元件藉由該線路結構、該複數支撐元件及該橋接組件而相互電性橋接，俾藉由分開製作完成該電子模組與封裝模組，可避免該橋接組件經過太多次之熱製程，故能避免該橋接組件之氣泡轉移至該封裝模組中之問題。

Description

電子封裝件及其製法
本發明係有關一種半導體裝置，尤指一種電子封裝件及其製法。
為了確保電子產品和通信設備的持續小型化和多功能性，半導體封裝需朝尺寸微小化發展，以利於多引腳之連接，並具備高功能性。例如，於先進製程封裝中，常用的封裝型式如2.5D封裝製程、扇出(Fan-Out)佈線配合嵌埋橋接(Embedded Bridge)元件之製程(簡稱FO-EB)等，其中，FO-EB相對於2.5D封裝製程係具有低成本及材料供應商多等優勢。
圖1係習知FO-EB之半導體封裝件1之剖面示意圖。該半導體封裝件1係於一具有線路層140之基板結構14上設置一具有複數導電體110之第一半導體晶片11(藉由黏膠12)與複數導電柱13，再以一第一封裝層15包覆該第一半導體晶片11與該些導電柱13，之後於該第一封裝層15上形成一電性連接該第一半導體晶片11與該些導電柱13之線路結構10，以於該線路結構10上設置(藉由銲錫凸塊160)複數電性連接該線路結構10之第二半導體晶片16，並以一第二封裝層18包覆該些第二半導體晶片16，其中，該線路層140與該線路結構10係採用扇出型重佈線路層(redistribution layer，簡稱RDL)之規格，且該第一半導體晶片 11係作為嵌埋於該第一封裝層15中之橋接元件(Bridge die)，以電性橋接兩相鄰之第二半導體晶片16。
前述半導體封裝件1主要以該基板結構14藉由複數銲球17接置於一封裝基板1a上，且該些導電柱13係電性連接該線路層140，並使該封裝基板1a藉由銲球19接置於一電路板(圖略)上。
然而，習知半導體封裝件1中，該第一半導體晶片11藉由保護層111包覆該些導電體110，且於該第一封裝層15上製作該線路結構10之多層線路時，需熱固該線路結構10之每一層介電層100，惟該導電體110於熱製程中將產生氣泡(void)，而該導電體110中所殘留之氣泡可能造成導電體110與線路結構接合問題。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：電子模組，係包含有一包覆層、至少一嵌埋於該包覆層中之橋接組件及至少一嵌埋於該包覆層中之導電柱；以及封裝模組，係藉由複數支撐元件堆疊於該電子模組上，且該封裝模組係包含有一線路結構及複數設於該線路結構上之電子元件，以令該線路結構藉由該複數支撐元件電性連接該橋接組件與該導電柱，並使該複數電子元件藉由該線路結構、該複數支撐元件及該橋接組件而相互電性橋接。
本發明復提供一種電子封裝件之製法，係包括：提供電子模組與封裝模組，該電子模組係包含有一包覆層、至少一嵌埋於該包覆層中之橋接組件及至少一嵌埋於該包覆層中之導電柱，且該封裝模組係包含有一線路結構及複數設於該線路結構上之電子元件；以及將該封裝模組以其線路結構藉由複數支撐元件堆疊於該電子模組上，以令該線路結構藉由該複數支撐元件電性連接該橋接組件與該導電柱，使該複數電子元件藉由該線路結構與該支撐元件電性橋接該橋接組件。
前述之電子封裝件及其製法中，該線路結構係定義有對應該橋接組件配置之第一區塊及對應該導電柱配置之第二區塊，以令該第一區塊具有電性連接該橋接組件之第一導電部，且該第二區塊具有電性連接該導電柱之第二導電部。例如，該第一導電部及/或該第二導電部之線寬係至多為45微米。或者，該複數支撐元件係定義有至少一電性連接該第一區塊與該橋接組件之第一連接部及至少一電性連接該第二區塊與該導電柱之第二連接部，以令該第一連接部之寬度不同於該第一導電部之線寬。
前述之電子封裝件及其製法中，該複數支撐元件係定義有至少一電性連接該橋接組件之第一連接部與至少一電性連接該導電柱之第二連接部，以令該第一連接部電性連接該橋接組件與該線路結構，且該第二連接部電性連接該導電柱與該線路結構。例如，該第一連接部之寬度係至多55微米，且該第二連接部之寬度係至少100微米，即該第一連接部之寬度與該第二連接部之寬度係不相同。或者，該第一連接部之寬度係等於該橋接組件之線寬。
前述之電子封裝件及其製法中，該電子模組復包含有形成於該包覆層上之佈線結構，且令該佈線結構電性連接該導電柱與該橋接組件。該電子模組復包含有形成於該佈線結構上且電性連接該佈線結構之複數導電元件。
前述之電子封裝件及其製法中，該電子模組復包含形成於該包覆層上之線路增層結構，以令該線路增層結構電性連接該橋接組件與該導電柱，且該封裝模組以其線路結構藉由該複數支撐元件堆疊於該線路增層結構上。
前述之電子封裝件及其製法中，該封裝模組復包含有一包覆該複數電子元件之封裝層。
前述之電子封裝件及其製法中，復包括形成封裝材於該封裝模組與該電子模組之間，使該封裝材包覆該複數支撐元件。
由上可知，本發明之電子封裝件及其製法中，主要藉由分開製作完成該電子模組與封裝模組，再將該電子模組與封裝模組藉由該些支撐元件相互堆疊，以避免該橋接組件經過太多次之熱製程，故相較於習知技術，本發明能避免該橋接組件產生氣泡之問題。
1:半導體封裝件
1a,31:封裝基板
10,20:線路結構
100:介電層
102:導電盲孔
11:第一半導體晶片
110,21a:導電體
111,29:保護層
12:黏膠
13,23:導電柱
14:基板結構
140,241,401:線路層
15:第一封裝層
16:第二半導體晶片
160:銲錫凸塊
17,19,310:銲球
18:第二封裝層
2,4:電子封裝件
2a:橋接組件
200:絕緣層
201:線路重佈層
201a:第一導電部
201b:第二導電部
202:電性接觸墊
21:電子主體
210:導電穿孔
22:線路部
22a:外接凸塊
22b:結合層
220:鈍化層
221:導電跡線
23a,23b:端部
24:佈線結構
24a:第一側
24b:第二側
240,400:介電層
25:包覆層
25a:第一表面
25b:第二表面
26:電子元件
26a:導電凸塊
260:銲錫材料
262:底膠
27:導電元件
27a:凸塊底下金屬層
270:金屬凸塊
271:銲錫材料
28:封裝層
3a,4a:電子模組
3b:封裝模組
30:支撐元件
30a:第一連接部
30b:第二連接部
300,38:封裝材
32:強固件
40:線路增層結構
9:承載件
90:離型層
91:金屬層
A:第一區塊
B:第二區塊
S:切割路徑
圖1係為習知半導體封裝件之剖視示意圖。
圖2A至圖2E係為本發明之電子封裝件之製法之剖視示意圖。
圖2F係為圖2E之後續製程之剖視示意圖。
圖3A至圖3B係為圖2C之另一方式之剖視示意圖。
圖4係為圖2B之另一方式之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2E係為本發明之電子封裝件2之製法的剖面示意圖。
如圖2A所示，提供一設有佈線結構24之承載件9，並於該佈線結構24上配置一橋接組件2a及複數導電柱23。
所述之承載件9例如為半導體材質(如矽或玻璃)之板體，其上以例如塗佈方式依序形成有一離型層90與一如鈦/銅之金屬層91，以令該佈線結構24形成於該金屬層91上。
所述之佈線結構24係具有相對之第一側24a與第二側24b，且該佈線結構24以其第二側24b結合該金屬層91。
再者，該佈線結構24係包含至少一介電層240及結合該介電層240之線路層241。例如，形成該介電層240之材質係如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材，且可採用線路重佈層(redistribution layer，簡稱RDL)製程形成該線路層241與該介電層240。
所述之橋接組件2a係包含一電子主體21、一線路部22、複數形成於該電子主體21上之導電體21a及複數形成於該線路部22上且電性連接該線路部22與該線路層241之外接凸塊22a，其中，將一結合層22b形成於該線路部22上 以包覆該些外接凸塊22a，使該橋接組件2a以該結合層22b結合於該佈線結構24之第一側24a上，且令該外接凸塊22a接合該線路層241。
於本實施例中，該電子主體21係為矽基材，如半導體晶片，其具有複數貫穿該電子主體21之導電穿孔210，如導電矽穿孔(Through-silicon via，簡稱TSV)，以電性連接該線路部22與該複數導電體21a。例如，該線路部22係包含至少一鈍化層220及結合該鈍化層220之導電跡線221，以令該導電跡線221電性連接該導電穿孔210與該複數外接凸塊22a。應可理解地，有關具有該導電穿孔210之元件結構之態樣繁多，並無特別限制。
再者，該導電體21a與外接凸塊22a係為如銅柱之金屬柱，且該結合層22b係為非導電膜(Non-Conductive Film，簡稱NCF)或其它易於黏著該介電層240之材質。
又，可依需求形成一保護層29形成於該電子主體21上以包覆該複數導電體21a。例如，該保護層29係為絕緣材，如氮化矽(SiN)等之氮化物。
所述之複數導電柱23係設於該佈線結構24之第一側24a上並電性連接該線路層241。
於本實施例中，形成該複數導電柱23之材質係為如銅之金屬材或銲錫材。例如，藉由曝光顯影方式，於該線路層241上電鍍形成該些導電柱23。
如圖2B所示，形成一包覆層25於該佈線結構24之第一側24a上，使該包覆層25包覆該橋接組件2a、該保護層29與該些導電柱23，以形成一電子模組3a，其中，該包覆層25係具有相對之第一表面25a與第二表面25b，且令該保護層29、該導電體21a之端面與該導電柱23之端部23a外露出該包覆層25之第一表面25a，並令該包覆層25以其第二表面25b結合至該佈線結構24之第一側24a上。
於本實施例中，該包覆層25係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)。例如，該包覆層25之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成於該佈線結構24上。
再者，可藉由整平製程，使該包覆層25之第一表面25a齊平該保護層29之頂面、該導電柱23之端部23a之表面與該導電體21a之端面，以令該導電柱23之端部23a之表面與該導電體21a之端面外露出該包覆層25之第一表面25a。例如，該整平製程係藉由研磨方式，移除該保護層29之部分材質、該導電柱23之部分材質、該導電體21a之部分材質與該包覆層25之部分材質。
如圖2C所示，提供一封裝模組3b，並將該封裝模組3b藉由複數支撐元件30堆疊於該電子模組3a之包覆層25之第一表面25a上，其中，該封裝模組3b係包含一堆疊於該電子模組3a上之線路結構20、複數設於該線路結構20上之電子元件26、以及一包覆該些電子元件26之封裝層28，以令該線路結構20藉由該些支撐元件30電性連接該複數導電柱23與該複數導電體21a。
所述之線路結構20係為基板規格，如具有核心層之載板(substrate)、無核心層(coreless)之載板，或包括至少一絕緣層200及設於該絕緣層200上之線路重佈層(redistribution layer，簡稱RDL)201，較佳為至少兩層之線路重佈層201，其中，最外層之絕緣層200可作為防銲層，且令最外層之線路重佈層201外露出該防銲層，俾供作為電性接觸墊202，如微墊(micro pad，俗稱μ-pad)。
於本實施例中，形成該線路重佈層201之材質係為銅，且形成該絕緣層200之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)等之介電材、或如綠漆、油墨等之防銲材。
再者，該線路結構20係定義有第一區塊A與第二區塊B，以令該第一區塊A之線路重佈層201具有第一導電部201a，且該第二區塊B之線路重佈層 201具有第二導電部201b。例如，該第一導電部201a或該第二導電部201b之線寬(pitch)為45微米(um)以下。
所述之電子元件26係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
於本實施中，該電子元件26係例如為圖形處理器(graphics processing unit，簡稱GPU)、高頻寬記憶體(High Bandwidth Memory，簡稱HBM)等半導體晶片，且該橋接組件2a係作為橋接元件(Bridge die)，其藉由該複數導電體21a電性連接該線路結構20，進而電性橋接至少二電子元件26。
再者，該電子元件26係具有複數如銅柱之導電凸塊26a，以藉由複數如銲錫凸塊之銲錫材料260電性連接該電性接觸墊202。
又，可形成一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)(圖略)於該電性接觸墊202或該電子元件26上，以利於結合該銲錫材料260或該導電凸塊26a。
所述之封裝層28係為絕緣材，如聚醯亞胺(PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該線路結構20上。應可理解地，形成該封裝層28之材質可相同或不相同該包覆層25之材質。
於本實施例中，先形成底膠262於該電子元件26與該線路結構20之間以包覆該些導電凸塊26a與銲錫材料260，再形成該封裝層28以包覆該底膠262與該電子元件26。於其它實施例中，該封裝層28係同時包覆該些電子元件26與該些導電凸塊26a，而無需使用底膠262。
所述之支撐元件30係定義有複數對應該第一區塊A之第一連接部30a與複數對應該第二區塊B之第二連接部30b，以令該第一連接部30a電性連接 該橋接組件2a之導電體21a與該線路重佈層201之第一導電部201a，且該第二連接部30b電性連接該導電柱23與該線路重佈層201之第二導電部201b。
於本實施例中，該支撐元件30係為導電凸塊、導電柱或導接墊等，其包含銲錫材料及/銅材等之金屬材質，但無特別限制。
再者，該些電子元件26之橋接路徑係從該線路結構20之第一區塊A之第一導電部201a經由該支撐元件30之第一連接部30a而導通至該電子模組3a之橋接組件2a，且該些電子元件26之電性路徑係從該線路結構20之第二區塊B之第二導電部201b經由該支撐元件30之第二連接部30b而導通至該電子模組3a之導電柱23。
又，該第一連接部30a之寬度(如55微米以下)與該第二連接部30b之寬度(如100微米以上)互不相同。進一步，該第一連接部30a之寬度(直徑或尺寸最大處)不同於該第一導電部201a之線寬，且該第一連接部30a之寬度同於該橋接組件2a(如導電體21a、導電穿孔210或導電跡線221)之線寬。
應可理解地，該封裝模組3b並非於該電子模組3a上製作，因而該封裝模組3b之製程不受限於該承載件9或該電子模組3a之規格，故有關該封裝模組2b之製程形式繁多，並無特別限制。
如圖2D所示，移除該承載件9及其上之離型層90，再移除該金屬層91，以外露出該佈線結構24之第二側24b。
於本實施例中，於剝離該離型層90時，藉由該金屬層91作為阻障之用，以避免破壞該佈線結構24之介電層240，且待移除該承載件9及其上之離型層90後，再以蝕刻方式移除該金屬層91，使該線路層241外露。
如圖2E所示，沿如圖2D所示之切割路徑S進行切單製程，且形成複數導電元件27於該佈線結構24之第二側24b上，使該些導電元件27電性連接該線路層241，以製得電子封裝件2。
於本實施例中，該導電元件27係包含一如銅材之金屬凸塊270及形成於該金屬凸塊270上之銲錫材料271。例如，該線路層241上可形成凸塊底下金屬層(Under Bump Metallization，簡稱UBM)27a，以利於結合該金屬凸塊270。應可理解地，當該接點(IO)之數量不足時，仍可藉由RDL製程進行增層作業，以重新配置該佈線結構24之IO數量及其位置。
於後續製程中，如圖2F所示，該電子封裝件2可藉由該些導電元件27設置於一封裝基板31上。進一步，該封裝基板31下側進行植球製程以形成複數銲球310，供於後續製程中，該封裝基板31以其下側之銲球310設於一電路板(圖略)上。
再者，於製作該封裝模組3b時，可依需求藉由整平製程，如研磨方式，移除該封裝層28之部分材質，使該封裝層28之上表面齊平該電子元件26之上表面，如圖2F所示，以令該電子元件26外露出該封裝層28。
又，於圖2C所示之製程中，該封裝模組3b係以該些支撐元件30堆疊於該電子模組3a上，故可依需求形成一如底膠之封裝材300於該封裝模組3b與該電子模組3a之間，如圖2F所示，以包覆該些支撐元件30。於另一方式中，如圖3A及圖3B所示，亦可採用如封裝膠體之封裝材38一併包覆該封裝模組3b與該些支撐元件30。
另外，該封裝基板31上可依需求設置一強固件32，如圖3所示之金屬框，以消除應力集中之問題而避免電子封裝件2發生翹曲之情況。
因此，本發明之製法，主要藉由分開製作完成該電子模組3a與封裝模組3b，再將該電子模組3a與封裝模組3b藉由該些支撐元件30相互堆疊，以避免該橋接組件2a經過太多次之熱製程，故相較於習知技術，本發明之製法僅需於該橋接組件2a上進行一次熱製程(如回銲該些支撐元件30)，且於回銲該些支撐 元件30時，該導電體21a不會產生氣泡(void)，因而能避免多次熱製程造成該導電體21a氣泡之問題。
另請配合參閱圖4之電子封裝件4，由於前述該電子模組3a與封裝模組3b係分開製作，故可將該封裝模組3b之線路結構20之線路重佈層201之配線層數分配至圖4之該電子模組4a之製程中，以於該電子模組4a之包覆層25第一表面25a上形成一線路增層結構40，且該線路增層結構40係包含至少一介電層400及結合該介電層400之線路層401，以令該線路層401電性連接該複數導電體21a與該複數導電柱23，使該封裝模組3b以其線路結構20藉由複數支撐元件30堆疊於該線路增層結構40上。於本實施例中，該線路增層結構40可為具有核心或無核心的基板線路結構或重分佈線路結構。
因此，藉由將預計層數之配線(線路層400與線路重佈層201)分別佈設於該線路增層結構40與該線路結構20中，以提升線路製程之良率，降低該電子封裝件4之製作成本。
例如，以預計五層配線為例，可將三層之線路重佈層201配置於該線路結構20中，而將兩層之線路層401配置於該線路增層結構40，若每一層之配線之製作良率約為95%，則該線路結構20之良率為85.7%(即0.8573)，而該線路增層結構40之良率為90.1%(即0.9025)，故相較於將五層之線路重佈層201配置於該線路結構20中之良率為77.4%(即0.7737)，本方式之整體良率較佳，以利於降低製程成本。
本發明亦提供一種電子封裝件2,4，係包括：一電子模組3a,4a、以及一藉由複數支撐元件30堆疊於該電子模組3a上之封裝模組3b。
所述之電子模組3a,4a係包含有一包覆層25、至少一嵌埋於該包覆層25中之橋接組件2a及至少一嵌埋於該包覆層25中之導電柱23，其中，該橋接組件2a係具有複數導電體21a及一包覆該複數導電體21a之保護層29。
所述之封裝模組3b係包含有一線路結構20及複數設於該線路結構20上之電子元件26，以令該線路結構20藉由該複數支撐元件30電性連接該橋接組件2a與該導電柱23，使該複數電子元件26藉由該線路結構20與該支撐元件30電性橋接該橋接組件2a。
於一實施例中，該線路結構20係定義有對應該橋接組件2a配置之第一區塊A及對應該導電柱23配置之第二區塊B，以令該第一區塊A具有電性連接該橋接組件2a之第一導電部201a，且該第二區塊B具有電性連接該導電柱23之第二導電部201b。例如，該第一導電部201a及/或該第二導電部201b之線寬係至多為45微米。或者，該複數支撐元件30係定義有至少一電性連接該第一區塊A與該橋接組件2a之第一連接部30a及至少一電性連接該第二區塊B與該導電柱23之第二連接部30b，以令該第一連接部30a之寬度不同於該第一導電部201a之線寬。
於一實施例中，該複數支撐元件30係定義有至少一電性連接該橋接組件2a之第一連接部30a與至少一電性連接該導電柱23之第二連接部30b，以令該第一連接部30a電性連接該橋接組件2a與該線路結構20，且該第二連接部30b電性連接該導電柱23與該線路結構20。例如，該第一連接部30a之寬度(直徑或尺寸最大處)係至多55微米，且該第二連接部30b之寬度(直徑或尺寸最大處)係至少100微米，即該第一連接部30a之寬度與該第二連接部30b之寬度係不相同。或者，該第一連接部30a之寬度係等於該橋接組件2a之線寬。
於一實施例中，該電子模組3a,4a復包含有形成於該包覆層25上之佈線結構24，且令該佈線結構24電性連接該導電柱23與該橋接組件2a。進一步，該電子模組3a復包含有形成於該佈線結構24上且電性連接該佈線結構24之複數導電元件27。
於一實施例中，該電子模組4a復包含形成於該包覆層25上之線路增層結構40，以令該線路增層結構40電性連接該橋接組件2a與該導電柱23，且該 封裝模組3b以其線路結構20藉由該複數支撐元件30堆疊於該線路增層結構40上。
於一實施例中，該封裝模組3b復包含有一包覆該複數電子元件26之封裝層28。
於一實施例中，所述之電子封裝件2復包括形成於該封裝模組3b與該電子模組3a之間的封裝材300，係包覆該複數支撐元件30。
綜上所述，本發明之電子封裝件及其製法，係藉由分開製作完成該電子模組與該封裝模組，再將該電子模組與封裝模組藉由該些支撐元件相互堆疊，以避免該橋接組件經過太多次之熱製程，故相較於習知技術，本發明能避免該橋接組件產生氣泡之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2a:橋接組件
20:線路結構
21a:導電體
23:導電柱
24:佈線結構
241:線路層
25:包覆層
26:電子元件
27:導電元件
27a:凸塊底下金屬層
270:金屬柱
271:銲錫材料
28:封裝層
29:保護層
3a:電子模組
3b:封裝模組
30:支撐元件
30a:第一連接部
30b:第二連接部

Claims (26)

  1. 一種電子封裝件，係包括：電子模組，係包含有一包覆層、至少一嵌埋於該包覆層中之橋接組件及至少一嵌埋於該包覆層中之導電柱；封裝模組，係藉由複數支撐元件堆疊於該電子模組上，且該封裝模組係包含有一線路結構及複數設於該線路結構上之電子元件，以令該線路結構藉由該複數支撐元件電性連接該橋接組件與該導電柱，並使該複數電子元件藉由該線路結構、該複數支撐元件及該橋接組件而相互電性橋接；以及封裝材，係形成於該封裝模組與該電子模組之間，以包覆該複數支撐元件。
  2. 如請求項1所述之電子封裝件，其中，該線路結構係定義有對應該橋接組件配置之第一區塊及對應該導電柱配置之第二區塊，以令該第一區塊具有電性連接該橋接組件之第一導電部，且該第二區塊具有電性連接該導電柱之第二導電部。
  3. 如請求項2所述之電子封裝件，其中，該第一導電部及/或該第二導電部之線寬係至多為45微米。
  4. 如請求項2所述之電子封裝件，其中，該複數支撐元件係定義有至少一電性連接該第一區塊與該橋接組件之第一連接部及至少一電性連接該第二區塊與該導電柱之第二連接部，且令該第一連接部之寬度不同於該第一導電部之線寬。
  5. 如請求項1所述之電子封裝件，其中，該複數支撐元件係定義有至少一電性連接該橋接組件之第一連接部與至少一電性連接該導電柱之第二 連接部，以令該第一連接部電性連接該橋接組件與該線路結構，且該第二連接部電性連接該導電柱與該線路結構。
  6. 如請求項5所述之電子封裝件，其中，該第一連接部之寬度係至多55微米。
  7. 如請求項5所述之電子封裝件，其中，該第二連接部之寬度係至少100微米。
  8. 如請求項5所述之電子封裝件，其中，該第一連接部之寬度與該第二連接部之寬度係不相同。
  9. 如請求項5所述之電子封裝件，其中，該第一連接部之寬度係等於該橋接組件之線寬。
  10. 如請求項1所述之電子封裝件，其中，該電子模組復包含有形成於該包覆層上之佈線結構，且令該佈線結構電性連接該導電柱與該橋接組件。
  11. 如請求項10所述之電子封裝件，該電子模組復包含有形成於該佈線結構上且電性連接該佈線結構之複數導電元件。
  12. 如請求項1所述之電子封裝件，其中，該電子模組復包含形成於該包覆層上之線路增層結構，以令該線路增層結構電性連接該橋接組件與該導電柱，且該封裝模組以其線路結構藉由該複數支撐元件堆疊於該線路增層結構上。
  13. 如請求項1所述之電子封裝件，其中，該封裝模組復包含有一包覆該複數電子元件之封裝層。
  14. 一種電子封裝件之製法，係包括： 提供電子模組與封裝模組，該電子模組係包含有一包覆層、至少一嵌埋於該包覆層中之橋接組件及至少一嵌埋於該包覆層中之導電柱，且該封裝模組係包含有一線路結構及複數設於該線路結構上之電子元件；將該封裝模組以其線路結構藉由複數支撐元件堆疊於該電子模組上，以令該線路結構藉由該複數支撐元件電性連接該橋接組件與該導電柱，並使該複數電子元件藉由該線路結構、該複數支撐元件及該橋接組件而相互電性橋接；以及形成封裝材於該封裝模組與該電子模組之間，使該封裝材包覆該複數支撐元件。
  15. 如請求項14所述之電子封裝件之製法，其中，該線路結構係定義有對應該橋接組件配置之第一區塊及對應該導電柱配置之第二區塊，以令該第一區塊具有電性連接該橋接組件之第一導電部，且該第二區塊具有電性連接該導電柱之第二導電部。
  16. 如請求項15所述之電子封裝件之製法，其中，該第一導電部及/或該第二導電部之線寬係至多為45微米。
  17. 如請求項15所述之電子封裝件之製法，其中，該複數支撐元件係定義有至少一電性連接該第一區塊與該橋接組件之第一連接部及至少一電性連接該第二區塊與該導電柱之第二連接部，以令該第一連接部之寬度不同於該第一導電部之線寬。
  18. 如請求項14所述之電子封裝件之製法，其中，該複數支撐元件係定義有至少一電性連接該橋接組件之第一連接部與至少一電性連接該導電柱之第二連接部，以令該第一連接部電性連接該橋接組件與該線路結構，且該第二連接部電性連接該導電柱與該線路結構。
  19. 如請求項18所述之電子封裝件之製法，其中，該第一連接部之寬度係至多55微米。
  20. 如請求項18所述之電子封裝件之製法，其中，該第二連接部之寬度係至少100微米。
  21. 如請求項18所述之電子封裝件之製法，其中，該第一連接部之寬度與該第二連接部之寬度係不相同。
  22. 如請求項18所述之電子封裝件之製法，其中，該第一連接部之寬度係等於該橋接組件之線寬。
  23. 如請求項14所述之電子封裝件之製法，其中，該電子模組復包含有形成於該包覆層上之佈線結構，且令該佈線結構電性連接該導電柱與該橋接組件。
  24. 如請求項23所述之電子封裝件之製法，該電子模組復包含有形成於該佈線結構上且電性連接該佈線結構之複數導電元件。
  25. 如請求項14所述之電子封裝件之製法，其中，該電子模組復包含形成於該包覆層上之線路增層結構，以令該線路增層結構電性連接該橋接組件與該導電柱，且該封裝模組以其線路結構藉由該複數支撐元件堆疊於該線路增層結構上。
  26. 如請求項14所述之電子封裝件之製法，其中，該封裝模組復包含有一包覆該複數電子元件之封裝層。
TW111122668A 2022-06-17 2022-06-17 電子封裝件及其製法 TWI825790B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW111122668A TWI825790B (zh) 2022-06-17 2022-06-17 電子封裝件及其製法
CN202210749644.5A CN117316884A (zh) 2022-06-17 2022-06-28 电子封装件及其制法
US18/310,072 US20230411364A1 (en) 2022-06-17 2023-05-01 Electronic package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW111122668A TWI825790B (zh) 2022-06-17 2022-06-17 電子封裝件及其製法

Publications (2)

Publication Number Publication Date
TWI825790B true TWI825790B (zh) 2023-12-11
TW202401684A TW202401684A (zh) 2024-01-01

Family

ID=89169331

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111122668A TWI825790B (zh) 2022-06-17 2022-06-17 電子封裝件及其製法

Country Status (3)

Country Link
US (1) US20230411364A1 (zh)
CN (1) CN117316884A (zh)
TW (1) TWI825790B (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202010078A (zh) * 2018-08-15 2020-03-01 矽品精密工業股份有限公司 電子封裝件及其製法
TW202044517A (zh) * 2019-05-23 2020-12-01 矽品精密工業股份有限公司 電子封裝件及其製法
TW202101713A (zh) * 2019-06-20 2021-01-01 矽品精密工業股份有限公司 電子封裝件及其製法
US20210134724A1 (en) * 2019-11-01 2021-05-06 International Business Machines Corporation Multi-chip package structures formed with interconnect bridge devices and chip packages with discrete redistribution layers
TWI758167B (zh) * 2021-04-21 2022-03-11 欣興電子股份有限公司 封裝結構及其製作方法
CN114171469A (zh) * 2021-12-30 2022-03-11 长电集成电路(绍兴)有限公司 晶圆级扇出的多芯片封装结构及其制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202010078A (zh) * 2018-08-15 2020-03-01 矽品精密工業股份有限公司 電子封裝件及其製法
TW202044517A (zh) * 2019-05-23 2020-12-01 矽品精密工業股份有限公司 電子封裝件及其製法
TW202101713A (zh) * 2019-06-20 2021-01-01 矽品精密工業股份有限公司 電子封裝件及其製法
US20210134724A1 (en) * 2019-11-01 2021-05-06 International Business Machines Corporation Multi-chip package structures formed with interconnect bridge devices and chip packages with discrete redistribution layers
TWI758167B (zh) * 2021-04-21 2022-03-11 欣興電子股份有限公司 封裝結構及其製作方法
CN114171469A (zh) * 2021-12-30 2022-03-11 长电集成电路(绍兴)有限公司 晶圆级扇出的多芯片封装结构及其制备方法

Also Published As

Publication number Publication date
CN117316884A (zh) 2023-12-29
TW202401684A (zh) 2024-01-01
US20230411364A1 (en) 2023-12-21

Similar Documents

Publication Publication Date Title
KR102060624B1 (ko) 더미 커넥터를 구비한 반도체 패키지와 이를 형성하는 방법
KR20190055690A (ko) 반도체 패키지 및 그 형성 방법
US9754928B2 (en) SMD, IPD, and/or wire mount in a package
US11355428B2 (en) Semiconductor package
US20220302009A1 (en) Semiconductor package and method of manufacture
US11145614B2 (en) Semiconductor device and method of manufacture
CN107403785B (zh) 电子封装件及其制法
US20230386866A1 (en) Semiconductor Package and Method of Forming Thereof
US20220359489A1 (en) Semiconductor Devices and Methods of Manufacturing
TWI825790B (zh) 電子封裝件及其製法
TWI766192B (zh) 電子封裝件及其製法
TW202303881A (zh) 電子封裝件及其製法
TWI819440B (zh) 電子封裝件及其製法
TWI767770B (zh) 電子封裝件及其製法
TWI790916B (zh) 電子封裝件及其製法
TWI790962B (zh) 電子封裝件
TWI814524B (zh) 電子封裝件及其製法與電子結構及其製法
TWI839093B (zh) 電子結構之製法
TWI806263B (zh) 電子封裝件及其製法
CN217641291U (zh) 封装模组
US20240063130A1 (en) Package structure and fabricating method thereof
US11133283B2 (en) Integrated fan-out device
US20240071939A1 (en) Semiconductor structure and manufacturing method thereof
CN117766505A (zh) 封装基板及其制法
TW202414701A (zh) 封裝基板及其製法