CN117316884A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN117316884A
CN117316884A CN202210749644.5A CN202210749644A CN117316884A CN 117316884 A CN117316884 A CN 117316884A CN 202210749644 A CN202210749644 A CN 202210749644A CN 117316884 A CN117316884 A CN 117316884A
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China
Prior art keywords
electronic
conductive
package
module
layer
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CN202210749644.5A
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English (en)
Inventor
黄柏凯
林泳达
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN117316884A publication Critical patent/CN117316884A/zh
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Abstract

一种电子封装件及其制法，包括将电子模块与封装模块相互堆叠，该电子模块包括一桥接组件、多个导电柱以及一包覆该桥接组件与该多个导电柱的包覆层，且该封装模块包括有一线路结构及多个设于该线路结构上的电子元件，以将该封装模块通过多个支撑元件堆叠于该电子模块上，并使该多个电子元件通过该线路结构、该多个支撑元件及该桥接组件而相互电性桥接，以通过分开制作完成该电子模块与封装模块，可避免该桥接组件经过太多次的热制程，故能避免该桥接组件的气泡转移至该封装模块中的问题。

Description

电子封装件及其制法
技术领域
本发明有关一种半导体装置，尤指一种电子封装件及其制法。
背景技术
为了确保电子产品和通信设备的持续小型化和多功能性，半导体封装需朝尺寸微小化发展，以利于多引脚的连接，并具备高功能性。例如，于先进制程封装中，常用的封装型式如2.5D封装制程、扇出(Fan-Out)布线配合嵌埋桥接(Embedded Bridge)元件的制程(简称FO-EB)等，其中，FO-EB相对于2.5D封装制程具有低成本及材料供应商多等优势。
图1现有FO-EB的半导体封装件1的剖面示意图。该半导体封装件1于一具有线路层140的基板结构14上设置一具有多个导电体110的第一半导体芯片11(通过粘胶12)与多个导电柱13，再以一第一封装层15包覆该第一半导体芯片11与该些导电柱13，之后于该第一封装层15上形成一电性连接该第一半导体芯片11与该些导电柱13的线路结构10，以于该线路结构10上设置(通过焊锡凸块160)多个电性连接该线路结构10的第二半导体芯片16，并以一第二封装层18包覆该些第二半导体芯片16，其中，该线路层140与该线路结构10采用扇出型重布线路层(redistribution layer，简称RDL)的规格，且该第一半导体芯片11作为嵌埋于该第一封装层15中的桥接元件(Bridge die)，以电性桥接两相邻的第二半导体芯片16。
前述半导体封装件1主要以该基板结构14通过多个焊球17接置于一封装基板1a上，且该些导电柱13电性连接该线路层140，并使该封装基板1a通过焊球19接置于一电路板(图略)上。
然而，现有半导体封装件1中，该第一半导体芯片11通过保护层111包覆该些导电体110，且于该第一封装层15上制作该线路结构10的多层线路时，需热固该线路结构10的每一层介电层100，然而，该导电体110于热制程中将产生气泡(void)，而该导电体110中所残留的气泡可能造成导电体110与线路结构接合问题。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷，本发明提供一种电子封装件及其制法，能避免该桥接组件的气泡转移至该封装模块中的问题。
本发明的电子封装件，包括：电子模块，其包含有一包覆层、至少一嵌埋于该包覆层中的桥接组件及至少一嵌埋于该包覆层中的导电柱；以及封装模块，其通过多个支撑元件堆叠于该电子模块上，且该封装模块包含有一线路结构及多个设于该线路结构上的电子元件，以令该线路结构通过该多个支撑元件电性连接该桥接组件与该导电柱，并使该多个电子元件通过该线路结构、该多个支撑元件及该桥接组件而相互电性桥接。
本发明还提供一种电子封装件的制法，包括：提供电子模块与封装模块，该电子模块包含有一包覆层、至少一嵌埋于该包覆层中的桥接组件及至少一嵌埋于该包覆层中的导电柱，且该封装模块包含有一线路结构及多个设于该线路结构上的电子元件；以及将该封装模块以其线路结构通过多个支撑元件堆叠于该电子模块上，以令该线路结构通过该多个支撑元件电性连接该桥接组件与该导电柱，使该多个电子元件通过该线路结构与该支撑元件电性桥接该桥接组件。
前述的电子封装件及其制法中，该线路结构定义有对应该桥接组件配置的第一区块及对应该导电柱配置的第二区块，以令该第一区块具有电性连接该桥接组件的第一导电部，且该第二区块具有电性连接该导电柱的第二导电部。例如，该第一导电部及/或该第二导电部的线宽至多为45微米。或者，该多个支撑元件定义有至少一电性连接该第一区块与该桥接组件的第一连接部及至少一电性连接该第二区块与该导电柱的第二连接部，以令该第一连接部的宽度不同于该第一导电部的线宽。
前述的电子封装件及其制法中，该多个支撑元件定义有至少一电性连接该桥接组件的第一连接部与至少一电性连接该该导电柱的第二连接部，以令该第一连接部电性连接该桥接组件与该线路结构，且该第二连接部电性连接该导电柱与该线路结构。例如，该第一连接部的宽度至多55微米，且该第二连接部的宽度至少100微米，即该第一连接部的宽度与该第二连接部的宽度不相同。或者，该第一连接部的宽度等于该桥接组件的线宽。
前述的电子封装件及其制法中，该电子模块还包含有形成于该包覆层上的布线结构，且令该布线结构电性连接该导电柱与该桥接组件。该电子模块还包含有形成于该布线结构上且电性连接该布线结构的多个导电元件。
前述的电子封装件及其制法中，该电子模块还包含形成于该包覆层上的线路增层结构，以令该线路增层结构电性连接该桥接组件与该导电柱，且该封装模块以其线路结构通过该多个支撑元件堆叠于该线路增层结构上。
前述的电子封装件及其制法中，该封装模块还包含有一包覆该多个电子元件的封装层。
前述的电子封装件及其制法中，还包括形成封装材于该封装模块与该电子模块之间，使该封装材包覆该多个支撑元件。
由上可知，本发明的电子封装件及其制法中，主要通过分开制作完成该电子模块与封装模块，再将该电子模块与封装模块通过该些支撑元件相互堆叠，以避免该桥接组件经过太多次的热制程，故相比于现有技术，本发明能避免该桥接组件产生气泡的问题。
附图说明
图1为现有半导体封装件的剖视示意图。
图2A至图2E为本发明的电子封装件的制法的剖视示意图。
图2F为图2E的后续制程的剖视示意图。
图3A至图3B为图2C的另一方式的剖视示意图。
图4为图2B的另一方式的剖视示意图。
主要组件符号说明
1 半导体封装件
1a,31 封装基板
10,20 线路结构
100 介电层
102 导电盲孔
11 第一半导体芯片
110,21a 导电体
111,29 保护层
12 粘胶
13,23 导电柱
14 基板结构
140,241,401 线路层
15 第一封装层
16 第二半导体芯片
160 焊锡凸块
17,19,310 焊球
18 第二封装层
2,4 电子封装件
2a 桥接组件
200 绝缘层
201 线路重布层
201a 第一导电部
201b 第二导电部
202 电性接触垫
21 电子主体
210 导电穿孔
22 线路部
22a 外接凸块
22b 结合层
220 钝化层
221 导电迹线
23a,23b 端部
24 布线结构
24a 第一侧
24b 第二侧
240,400 介电层
25 包覆层
25a 第一表面
25b 第二表面
26 电子元件
26a 导电凸块
260 焊锡材料
262 底胶
27 导电元件
27a 凸块底下金属层
270 金属凸块
271 焊锡材料
28 封装层
3a,4a 电子模块
3b 封装模块
30 支撑元件
30a 第一连接部
30b 第二连接部
300,38 封装材
32 强固件
40 线路增层结构
9 承载件
90 离型层
91 金属层
A 第一区块
B 第二区块
S 切割路径。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2E为本发明的电子封装件2的制法的剖面示意图。
如图2A所示，提供一设有布线结构24的承载件9，并于该布线结构24上配置一桥接组件2a及多个导电柱23。
所述的承载件9例如为半导体材料(如硅或玻璃)的板体，其上以例如涂布方式依序形成有一离型层90与一如钛/铜的金属层91，以令该布线结构24形成于该金属层91上。
所述的布线结构24具有相对的第一侧24a与第二侧24b，且该布线结构24以其第二侧24b结合该金属层91。
再者，该布线结构24包含至少一介电层240及结合该介电层240的线路层241。例如，形成该介电层240的材料如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等的介电材，且可采用线路重布层(redistribution layer，简称RDL)制程形成该线路层241与该介电层240。
所述的桥接组件2a包含一电子主体21、一线路部22、多个形成于该电子主体21上的导电体21a及多个形成于该线路部22上且电性连接该线路部22与该线路层241的外接凸块22a，其中，将一结合层22b形成于该线路部22上以包覆该些外接凸块22a，使该桥接组件2a以该结合层22b结合于该布线结构24的第一侧24a上，且令该外接凸块22a接合该线路层241。
于本实施例中，该电子主体21为硅基材，如半导体芯片，其具有多个贯穿该电子主体21的导电穿孔210，如导电硅穿孔(Through-silicon via，简称TSV)，以电性连接该线路部22与该多个导电体21a。例如，该线路部22包含至少一钝化层220及结合该钝化层220的导电迹线221，以令该导电迹线221电性连接该导电穿孔210与该多个外接凸块22a。应可理解地，有关具有该导电穿孔210的元件结构的态样繁多，并无特别限制。
再者，该导电体21a与外接凸块22a为如铜柱的金属柱，且该结合层22b为非导电膜(Non-Conductive Film，简称NCF)或其它易于粘着该介电层240的材料。
另外，可依需求形成一保护层29形成于该电子主体21上以包覆该多个导电体21a。例如，该保护层29为绝缘材，如氮化硅(SiN)等的氮化物。
所述的多个导电柱23设于该布线结构24的第一侧24a上并电性连接该线路层241。
于本实施例中，形成该多个导电柱23的材料为如铜的金属材或焊锡材。例如，通过曝光显影方式，于该线路层241上电镀形成该些导电柱23。
如图2B所示，形成一包覆层25于该布线结构24的第一侧24a上，使该包覆层25包覆该桥接组件2a、该保护层29与该些导电柱23，以形成一电子模块3a，其中，该包覆层25具有相对的第一表面25a与第二表面25b，且令该保护层29、该导电体21a的端面与该导电柱23的端部23a外露出该包覆层25的第一表面25a，并令该包覆层25以其第二表面25b结合至该布线结构24的第一侧24a上。
于本实施例中，该包覆层25为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dryfilm)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)。例如，该包覆层25的制程可选择液态封胶(liquid compound)、喷涂(injection)、压合(lamination)或模压(compression molding)等方式形成于该布线结构24上。
再者，可通过整平制程，使该包覆层25的第一表面25a齐平该保护层29的顶面、该导电柱23的端部23a的表面与该导电体21a的端面，以令该导电柱23的端部23a的表面与该导电体21a的端面外露出该包覆层25的第一表面25a。例如，该整平制程通过研磨方式，移除该保护层29的部分材料、该导电柱23的部分材料、该导电体21a的部分材料与该包覆层25的部分材料。
如图2C所示，提供一封装模块3b，并将该封装模块3b通过多个支撑元件30堆叠于该电子模块3a的包覆层25的第一表面25a上，其中，该封装模块3b包含一堆叠于该电子模块3a上的线路结构20、多个设于该线路结构20上的电子元件26、以及一包覆该些电子元件26的封装层28，以令该线路结构20通过该些支撑元件30电性连接该多个导电柱23与该多个导电体21a。
所述的线路结构20为基板规格，如具有核心层的载板(substrate)、无核心层(coreless)的载板，或包括至少一绝缘层200及设于该绝缘层200上的线路重布层(redistribution layer，简称RDL)201，较佳为至少两层的线路重布层201，其中，最外层的绝缘层200可作为防焊层，且令最外层的线路重布层201外露出该防焊层，以供作为电性接触垫202，如微垫(micro pad，俗称μ-pad)。
于本实施例中，形成该线路重布层201的材料为铜，且形成该绝缘层200的材料为如聚对二唑苯(PBO)、聚酰亚胺(PI)、预浸材(PP)等的介电材、或如绿漆、油墨等的防焊材。
再者，该线路结构20定义有第一区块A与第二区块B，以令该第一区块A的线路重布层201具有第一导电部201a，且该第二区块B的线路重布层201具有第二导电部201b。例如，该第一导电部201a或该第二导电部201b的线宽(pitch)为45微米(um)以下。
所述的电子元件26为主动元件、被动元件或其二者组合，且该主动元件例如半导体芯片，而该被动元件例如电阻、电容及电感。
于本实施中，该电子元件26例如为图形处理器(graphics processing unit，简称GPU)、高频宽存储器(High Bandwidth Memory，简称HBM)等半导体芯片，且该桥接组件2a作为桥接元件(Bridge die)，其通过该多个导电体21a电性连接该线路结构20，进而电性桥接至少二电子元件26。
再者，该电子元件26具有多个如铜柱的导电凸块26a，以通过多个如焊锡凸块的焊锡材料260电性连接该电性接触垫202。
另外，可形成一凸块底下金属层(Under Bump Metallurgy，简称UBM)(图略)于该电性接触垫202或该电子元件26上，以利于结合该焊锡材料260或该导电凸块26a。
所述的封装层28为绝缘材，如聚酰亚胺(PI)、干膜(dry film)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该线路结构20上。应可理解地，形成该封装层28的材料可相同或不相同该包覆层25的材料。
于本实施例中，先形成底胶262于该电子元件26与该线路结构20之间以包覆该些导电凸块26a与焊锡材料260，再形成该封装层28以包覆该底胶262与该电子元件26。于其它实施例中，该封装层28同时包覆该些电子元件26与该些导电凸块26a，而无需使用底胶262。
所述的支撑元件30定义有多个对应该第一区块A的第一连接部30a与多个对应该第二区块B的第二连接部30b，以令该第一连接部30a电性连接该桥接组件2a的导电体21a与该线路重布层201的第一导电部201a，且该第二连接部30b电性连接该导电柱23与该线路重布层201的第二导电部201b。
于本实施例中，该支撑元件30为导电凸块、导电柱或导接垫等，其包含焊锡材料及/铜材等的金属材料，但无特别限制。
再者，该些电子元件26的桥接路径从该线路结构20的第一区块A的第一导电部201a经由该支撑元件30的第一连接部30a而导通至该电子模块3a的桥接组件2a，且该些电子元件26的电性路径从该线路结构20的第二区块B的第二导电部201b经由该支撑元件30的第二连接部30b而导通至该电子模块3a的导电柱23。
另外，该第一连接部30a的宽度(如55微米以下)与该第二连接部30b的宽度(如100微米以上)互不相同。进一步，该第一连接部30a的宽度(直径或尺寸最大处)不同于该第一导电部201a的线宽，且该第一连接部30a的宽度同于该桥接组件2a(如导电体21a、导电穿孔210或导电迹线221)的线宽。
应可理解地，该封装模块3b并非于该电子模块3a上制作，因而该封装模块3b的制程不受限于该承载件9或该电子模块3a的规格，故有关该封装模块2b的制程形式繁多，并无特别限制。
如图2D所示，移除该承载件9及其上的离型层90，再移除该金属层91，以外露出该布线结构24的第二侧24b。
于本实施例中，于剥离该离型层90时，通过该金属层91作为阻障之用，以避免破坏该布线结构24的介电层240，且待移除该承载件9及其上的离型层90后，再以蚀刻方式移除该金属层91，使该线路层241外露。
如图2E所示，沿如图2D所示的切割路径S进行切单制程，且形成多个导电元件27于该布线结构24的第二侧24b上，使该些导电元件27电性连接该线路层241，以制得电子封装件2。
于本实施例中，该导电元件27包含一如铜材的金属凸块270及形成于该金属凸块270上的焊锡材料271。例如，该线路层241上可形成凸块底下金属层(Under BumpMetallization，简称UBM)27a，以利于结合该金属凸块270。应可理解地，当该接点(IO)的数量不足时，仍可通过RDL制程进行增层作业，以重新配置该布线结构24的IO数量及其位置。
于后续制程中，如图2F所示，该电子封装件2可通过该些导电元件27设置于一封装基板31上。进一步，该封装基板30下侧进行植球制程以形成多个焊球310，供于后续制程中，该封装基板31以其下侧的焊球310设于一电路板(图略)上。
再者，于制作该封装模块3b时，可依需求通过整平制程，如研磨方式，移除该封装层28的部分材料，使该封装层28的上表面齐平该电子元件26的上表面，如图2F所示，以令该电子元件26外露出该封装层28。
另外，于图2C所示的制程中，该封装模块3b以该些支撑元件30堆叠于该电子模块3a上，故可依需求形成一如底胶的封装材300于该封装模块3b与该电子模块3a之间，如图2F所示，以包覆该些支撑元件30。于另一方式中，如图3A及图3B所示，亦可采用如封装胶体的封装材38一并包覆该封装模块3b与该些支撑元件30。
另外，该封装基板31上可依需求设置一强固件32，如图3所示的金属框，以消除应力集中的问题而避免电子封装件2发生翘曲的情况。
因此，本发明的制法，主要通过分开制作完成该电子模块3a与封装模块3b，再将该电子模块3a与封装模块3b通过该些支撑元件30相互堆叠，以避免该桥接组件2a经过太多次的热制程，故相比于现有技术，本发明的制法仅需于该桥接组件2a上进行一次热制程(如回焊该些支撑元件30)，且于回焊该些支撑元件30时，该导电体21a不会产生气泡(void)，因而能避免多次热制程造成该导电体21a气泡的问题。
另请配合参阅图4的电子封装件4，由于前述该电子模块3a与封装模块3b分开制作，故可将该封装模块3b的线路结构20的线路重布层201的配线层数分配至图4的该电子模块4a的制程中，以于该电子模块4a的包覆层25第一表面25a上形成一线路增层结构40，且该线路增层结构40包含至少一介电层400及结合该介电层400的线路层401，以令该线路层401电性连接该多个导电体21a与该多个导电柱23，使该封装模块3b以其线路结构20通过多个支撑元件30堆叠于该线路增层结构40上。于本实施例中，该线路增层结构40可为具有核心或无核心的基板线路结构或重分布线路结构。
因此，通过将预计层数的配线(线路层400与线路重布层201)分别布设于该线路增层结构40与该线路结构20中，以提升线路制程的良率，降低该电子封装件4的制作成本。
例如，以预计五层配线为例，可将三层的线路重布层201配置于该线路结构20中，而将两层的线路层401配置于该线路增层结构40，若每一层的配线的制作良率约为95％，则该线路结构20的良率为85.7％(即0.8573)，而该线路增层结构40的良率为90.1％(即0.9025)，故相比于将五层的线路重布层201配置于该线路结构20中的良率为77.4％(即0.7737)，本方式的整体良率较佳，以利于降低制程成本。
本发明亦提供一种电子封装件2,4，包括：一电子模块3a,4a、以及一通过多个支撑元件30堆叠于该电子模块3a上的封装模块3b。
所述的电子模块3a,4a包含有一包覆层25、至少一嵌埋于该包覆层25中的桥接组件2a及至少一嵌埋于该包覆层25中的导电柱23，其中，该桥接组件2a具有多个导电体21a及一包覆该多个导电体21a的保护层29。
所述的封装模块3b包含有一线路结构20及多个设于该线路结构20上的电子元件26，以令该线路结构20通过该多个支撑元件30电性连接该桥接组件2a与该导电柱23，使该多个电子元件26通过该线路结构20与该支撑元件30电性桥接该桥接组件2a。
于一实施例中，该线路结构20定义有对应该桥接组件2a配置的第一区块A及对应该导电柱23配置的第二区块B，以令该第一区块A具有电性连接该桥接组件2a的第一导电部201a，且该第二区块B具有电性连接该导电柱23的第二导电部201b。例如，该第一导电部201a及/或该第二导电部201b的线宽至多为45微米。或者，该多个支撑元件30定义有至少一电性连接该第一区块A与该桥接组件2a的第一连接部30a及至少一电性连接该第二区块B与该导电柱23的第二连接部30b，以令该第一连接部30a的宽度不同于该第一导电部201a的线宽。
于一实施例中，该多个支撑元件30定义有至少一电性连接该桥接组件2a的第一连接部30a与至少一电性连接该该导电柱23的第二连接部30b，以令该第一连接部30a电性连接该桥接组件2a与该线路结构20，且该第二连接部30b电性连接该导电柱23与该线路结构20。例如，该第一连接部30a的宽度(直径或尺寸最大处)至多55微米，且该第二连接部30b的宽度(直径或尺寸最大处)至少100微米，即该第一连接部30a的宽度与该第二连接部30b的宽度不相同。或者，该第一连接部30a的宽度等于该桥接组件2a的线宽。
于一实施例中，该电子模块3a,4a还包含有形成于该包覆层25上的布线结构24，且令该布线结构24电性连接该导电柱23与该桥接组件2a。进一步，该电子模块3a还包含有形成于该布线结构24上且电性连接该布线结构24的多个导电元件27。
于一实施例中，该电子模块4a还包含形成于该包覆层25上的线路增层结构40，以令该线路增层结构40电性连接该桥接组件2a与该导电柱23，且该封装模块3b以其线路结构20通过该多个支撑元件30堆叠于该线路增层结构40上。
于一实施例中，该封装模块3b还包含有一包覆该多个电子元件26的封装层28。
于一实施例中，所述的电子封装件2还包括形成于该封装模块3b与该电子模块3a之间的封装材300，包覆该多个支撑元件30。
综上所述，本发明的电子封装件及其制法，通过分开制作完成该电子模块与该封装模块，再将该电子模块与封装模块通过该些支撑元件相互堆叠，以避免该桥接组件经过太多次的热制程，故相比于现有技术，本发明能避免该桥接组件产生气泡的问题。
上述实施例用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (28)

1.一种电子封装件，包括：
电子模块，其包含有一包覆层、至少一嵌埋于该包覆层中的桥接组件及至少一嵌埋于该包覆层中的导电柱；以及
封装模块，其通过多个支撑元件堆叠于该电子模块上，且该封装模块包含有一线路结构及多个设于该线路结构上的电子元件，以令该线路结构通过该多个支撑元件电性连接该桥接组件与该导电柱，并使该多个电子元件通过该线路结构、该多个支撑元件及该桥接组件而相互电性桥接。
2.如权利要求1所述的电子封装件，其中，该线路结构定义有对应该桥接组件配置的第一区块及对应该导电柱配置的第二区块，以令该第一区块具有电性连接该桥接组件的第一导电部，且该第二区块具有电性连接该导电柱的第二导电部。
3.如权利要求2所述的电子封装件，其中，该第一导电部及/或该第二导电部的线宽至多为45微米。
4.如权利要求2所述的电子封装件，其中，该多个支撑元件定义有至少一电性连接该第一区块与该桥接组件的第一连接部及至少一电性连接该第二区块与该导电柱的第二连接部，且令该第一连接部的宽度不同于该第一导电部的线宽。
5.如权利要求1所述的电子封装件，其中，该多个支撑元件定义有至少一电性连接该桥接组件的第一连接部与至少一电性连接该该导电柱的第二连接部，以令该第一连接部电性连接该桥接组件与该线路结构，且该第二连接部电性连接该导电柱与该线路结构。
6.如权利要求5所述的电子封装件，其中，该第一连接部的宽度至多55微米。
7.如权利要求5所述的电子封装件，其中，该第二连接部的宽度至少100微米。
8.如权利要求5所述的电子封装件，其中，该第一连接部的宽度与该第二连接部的宽度不相同。
9.如权利要求5所述的电子封装件，其中，该第一连接部的宽度等于该桥接组件的线宽。
10.如权利要求1所述的电子封装件，其中，该电子模块还包含有形成于该包覆层上的布线结构，且令该布线结构电性连接该导电柱与该桥接组件。
11.如权利要求10所述的电子封装件，其中，该电子模块还包含有形成于该布线结构上且电性连接该布线结构的多个导电元件。
12.如权利要求1所述的电子封装件，其中，该电子模块还包含形成于该包覆层上的线路增层结构，以令该线路增层结构电性连接该桥接组件与该导电柱，且该封装模块以其线路结构通过该多个支撑元件堆叠于该线路增层结构上。
13.如权利要求1所述的电子封装件，其中，该封装模块还包含有一包覆该多个电子元件的封装层。
14.如权利要求1所述的电子封装件，其中，该电子封装件还包括形成于该封装模块与该电子模块的间的封装材，包覆该多个支撑元件。
15.一种电子封装件的制法，包括：
提供电子模块与封装模块，该电子模块包含有一包覆层、至少一嵌埋于该包覆层中的桥接组件及至少一嵌埋于该包覆层中的导电柱，且该封装模块包含有一线路结构及多个设于该线路结构上的电子元件；以及
将该封装模块以其线路结构通过多个支撑元件堆叠于该电子模块上，以令该线路结构通过该多个支撑元件电性连接该桥接组件与该导电柱，并使该多个电子元件通过该线路结构、该多个支撑元件及该桥接组件而相互电性桥接。
16.如权利要求15所述的电子封装件的制法，其中，该线路结构定义有对应该桥接组件配置的第一区块及对应该导电柱配置的第二区块，以令该第一区块具有电性连接该桥接组件的第一导电部，且该第二区块具有电性连接该导电柱的第二导电部。
17.如权利要求16所述的电子封装件的制法，其中，该第一导电部及/或该第二导电部的线宽至多为45微米。
18.如权利要求16所述的电子封装件的制法，其中，该多个支撑元件定义有至少一电性连接该第一区块与该桥接组件的第一连接部及至少一电性连接该第二区块与该导电柱的第二连接部，以令该第一连接部的宽度不同于该第一导电部的线宽。
19.如权利要求15所述的电子封装件的制法，其中，该多个支撑元件定义有至少一电性连接该桥接组件的第一连接部与至少一电性连接该该导电柱的第二连接部，以令该第一连接部电性连接该桥接组件与该线路结构，且该第二连接部电性连接该导电柱与该线路结构。
20.如权利要求19所述的电子封装件的制法，其中，该第一连接部的宽度至多55微米。
21.如权利要求19所述的电子封装件的制法，其中，该第二连接部的宽度至少100微米。
22.如权利要求19所述的电子封装件的制法，其中，该第一连接部的宽度与该第二连接部的宽度不相同。
23.如权利要求19所述的电子封装件的制法，其中，该第一连接部的宽度等于该桥接组件的线宽。
24.如权利要求15所述的电子封装件的制法，其中，该电子模块还包含有形成于该包覆层上的布线结构，且令该布线结构电性连接该导电柱与该桥接组件。
25.如权利要求24所述的电子封装件的制法，其中，该电子模块还包含有形成于该布线结构上且电性连接该布线结构的多个导电元件。
26.如权利要求15所述的电子封装件的制法，其中，该电子模块还包含形成于该包覆层上的线路增层结构，以令该线路增层结构电性连接该桥接组件与该导电柱，且该封装模块以其线路结构通过该多个支撑元件堆叠于该线路增层结构上。
27.如权利要求15所述的电子封装件的制法，其中，该封装模块还包含有一包覆该多个电子元件的封装层。
28.如权利要求15所述的电子封装件的制法，其中，该制法还包括形成封装材于该封装模块与该电子模块之间，使该封装材包覆该多个支撑元件。
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