CN116936487A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN116936487A
CN116936487A CN202210368964.6A CN202210368964A CN116936487A CN 116936487 A CN116936487 A CN 116936487A CN 202210368964 A CN202210368964 A CN 202210368964A CN 116936487 A CN116936487 A CN 116936487A
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CN
China
Prior art keywords
layer
circuit structure
packaging layer
conductive
electrically connected
Prior art date
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Pending
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CN202210368964.6A
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English (en)
Inventor
柯仲禹
陈亮斌
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN116936487A publication Critical patent/CN116936487A/zh
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract

一种电子封装件及其制法，包括于线路结构上形成第一封装层，再将导电柱的部分柱体插入该第一封装层中，使该导电柱的剩余柱体凸出该第一封装层，之后以第二封装层包覆该导电柱的剩余柱体，使该导电柱一体成型于该第一封装层与第二封装层中，故该导电柱可降低其受该第二封装层的冲击，避免该导电柱倾斜的问题。

Description

电子封装件及其制法
技术领域
本发明有关一种半导体装置，尤指一种可提高可靠度的电子封装件及其制法。
背景技术
随着半导体封装技术的演进，半导体装置(Semiconductor device)已开发出不同的封装型态，而为提升电性功能及节省封装空间，遂开发出不同的立体封装技术，以将不同功能的集成电路整合于单一封装结构，例如将不同功用的电子元件(如存储器、中央处理器、绘图处理器、影像应用处理器等)，通过堆叠设计达到系统的整合，以应用于轻薄型电子产品。
图1为现有半导体封装件1的剖面示意图。如图1所示，该半导体封装件1的制法于该线路结构10上配置第一半导体芯片11与导电柱13，再以封装胶体15包覆该第一半导体芯片11与该导电柱13，之后，于该封装胶体15上形成一布线结构14，以于该布线结构14上配置第二半导体芯片12。该导电柱13电性连接该线路结构10与布线结构14，且该线路结构10电性连接该第一半导体芯片11，而该布线结构14电性连接该第二半导体芯片12，并于该线路结构10下侧形成多个焊球19，以供接合一电路板(图略)。
然而，现有半导体封装件1的制法中，先于该线路结构10上电镀形成该导电柱13，再以该封装胶体15包覆该导电柱13，故该导电柱13易受该封装胶体15冲击而倾斜，甚至断裂，导致该布线结构14形成于该封装胶体15上时，无法有效对位该导电柱13，造成该线路结构10与该布线结构14之间无法有效电性导通。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷，本发明提供一种半导体封装件及其制法，可避免该导电柱倾斜的问题。
本发明的电子封装件，包括：线路结构；第一电子元件，其设于该线路结构上并电性连接该线路结构；第一封装层，其设于该线路结构上以包覆该第一电子元件；导电柱，其插入该第一封装层中以设于该线路结构上并电性连接该线路结构，且令该导电柱的部分凸出该第一封装层；第二封装层，其设于该第一封装层上且包覆该导电柱凸出该第一封装层的部分，且令该导电柱的端面外露于该第二封装层；以及布线结构，其结合于该第二封装层上且电性连接该导电柱。
本发明亦提供一种电子封装件的制法，包括：于线路结构上设置至少一电性连接该线路结构的第一电子元件；将第一封装层形成于该线路结构上，以令该第一封装层包覆该第一电子元件；将导电柱形成于该第一封装层中，使该导电柱设于该线路结构上并电性连接该线路结构，且令该导电柱的部分凸出该第一封装层；形成第二封装层于该第一封装层上，使该第二封装层包覆该导电柱凸出该第一封装层的部分，且令该导电柱的端面外露于该第二封装层；以及形成布线结构于该第二封装层上，以令该布线结构电性连接该导电柱。
前述的制法中，该导电柱的制程包含：形成一阻层于该第一封装层上；形成连通该阻层与该第一封装层的穿孔，使该线路结构外露于该穿孔；形成该导电柱于该穿孔中，使该导电柱电性连接该线路结构；以及移除该阻层，使该导电柱的部分凸出该第一封装层。
前述的电子封装件及其制法中，该线路结构的其中一侧配置该第一电子元件与该第一封装层，而另一侧配置至少一功能元件。
前述的电子封装件及其制法中，该线路结构具有第一接地层，且该布线结构具有第二接地层，以令该第一接地层与该第二接地层电性连接该导电柱。
前述的电子封装件及其制法中，该第一封装层与第二封装层的材料相同。
前述的电子封装件及其制法中，该第一封装层与第二封装层的材料相异。
前述的电子封装件及其制法中，该第一封装层的硬度不同于该第二封装层的硬度。
前述的电子封装件及其制法中，还包括于该布线结构上设置至少一电性连接该布线结构的第二电子元件。
由上可知，本发明的电子封装件及其制法中，主要通过先于该线路结构上形成第一封装层，再将该导电柱的部分柱体形成于该第一封装层中，使该导电柱的剩余柱体凸出该第一封装层，之后以该第二封装层包覆该导电柱的剩余柱体，使该导电柱一体成型于该第一封装层与第二封装层中，故相比于现有技术，本发明可使该导电柱降低其受该第二封装层的冲击，因而可避免该导电柱倾斜或断裂等问题，以当该布线结构形成于该第二封装层上时，可有效对位该导电柱，使该线路结构与该布线结构之间得以有效电性导通。
附图说明
图1为现有半导体封装件的剖视示意图。
图2A至图2G为本发明的电子封装件的制法的剖视示意图。
主要组件符号说明
1 半导体封装件
10,20 线路结构
11 第一半导体芯片
12 第二半导体芯片
13,23 导电柱
14,24 布线结构
15 封装胶体
19 焊球
2 电子封装件
20a 第一侧
20b 第二侧
200 介电层
201 线路层
21 第一电子元件
21a 作用面
21b 非作用面
210 电极垫
211,221 导电凸块
212 底胶
22 第二电子元件
23a 端面
240 绝缘层
241 布线层
25 第一封装层
250 穿孔
26 第二封装层
26a 表面
28 功能元件
29 导电元件
8 阻层
9 承载件
90 离型层
S 切割路径。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2G为本发明的电子封装件2的制法的剖面示意图。
如图2A所示，于一承载件9上形成一线路结构20，该线路结构20具有相对的第一侧20a与第二侧20b，以令该线路结构20的第一侧20a上设置至少一第一电子元件21，且以一第一封装层25包覆该第一电子元件21，并使该线路结构20以其第二侧20b结合该承载件9。
于本实施例中，该线路结构20如具有核心层与线路层的封装基板(substrate)或无核心层(coreless)的基板结构，其包含至少一介电层200及结合该介电层200的线路层201。例如，以线路重布层(redistribution layer，简称RDL)的制作方式形成无核心层基板结构，其中，形成该线路层201的材料为铜，且形成该介电层200的材料为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)等的介电材。应可理解地，该线路结构20亦可为其它可供承载如芯片等电子元件的载板，如硅中介板(interposer)，并不限于上述。
再者，该承载件9例如为半导体材料(如硅或玻璃)的板体，其上形成有一离型层90，使该线路结构20结合于该离型层90上。
又，该第一电子元件21为主动元件、被动元件或其二者组合，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容或电感。于本实施例中，该第一电子元件21为半导体芯片，其具有相对的作用面21a与非作用面21b，且该作用面21a具有多个电极垫210，使该电子元件21以其电极垫210通过覆晶方式(透过如图所示的多个导电凸块211)电性连接该线路层201，再以底胶212包覆该些导电凸块211；或者，该第一电子元件21亦可通过多个焊线(图略)以打线方式电性连接该线路层201；亦或，该第一电子元件21可直接接触该线路层201以电性连接该线路层201。然而，有关该第一电子元件21电性连接线路层201的方式不限于上述。
另外，该第一封装层25为绝缘材，如聚酰亚胺(PI)、干膜(dryfilm)、环氧树脂(epoxy)环氧树脂的封装胶体或封装材(moldingcompound)，其可用压合(lamination)或模压(molding)的方式形成于该线路结构20的第一侧20a上。例如，该第一封装层25覆盖该第一电子元件21的非作用面21b；或者，可通过整平制程，如蚀刻或研磨方式，移除该第一封装层25的部分材料，以令该第一封装层25的上侧的表面齐平该第一电子元件21的非作用面21b。
如图2B所示，形成一阻层8于该第一封装层25上，再形成至少一穿孔250连通该阻层8与该第一封装层25，使该线路层201外露于该穿孔250。
如图2C所示，形成导电柱23于该穿孔250中，使该导电柱23电性连接该线路结构20的第一侧20a的线路层201。
于本实施例中，该导电柱23为如铜柱的金属柱或其它材料的柱体。
如图2D所示，移除该阻层8，使该导电柱23凸出该第一封装层25。
如图2E所示，形成第二封装层26于该第一封装层25上，以令该第二封装层26包覆该导电柱23。
于本实施例中，该第二封装层26为绝缘材，如聚酰亚胺、干膜、如环氧树脂的封装胶体或封装材，其可用压合或模压的方式形成于该布线结构24上。应可理解地，形成该第二封装层26的材料可相同或相异于该第一封装层25的材料，例如，该第一封装层25的硬度不同于(或大于)该第二封装层26的硬度。
再者，可通过整平制程，如蚀刻或研磨方式，移除该第二封装层26的部分材料，甚至该导电柱23的部分材料，使该第二封装层26的上侧的表面26a齐平该导电柱23的端面23a，以令该导电柱23的端面23a外露于该第二封装层26。或者，可于该第二封装层26的上侧的表面上形成开孔，以令该导电柱23的端面23a外露于该第二封装层26的开孔。
如图2F所示，形成一布线结构24于该第二封装层26上，使该布线结构24电性连接该导电柱23。之后，移除该承载件9与离型层90，以外露出该线路结构20的第二侧20b。
于本实施例中，该布线结构24如具有核心层与线路层的封装基板或无核心层的基板结构，其包含至少一绝缘层240及结合该绝缘层240且电性连接该导电柱23的布线层241。例如，以线路重布层(RDL)的制作方式形成无核心层基板结构，其中，形成该布线层241的材料为铜，且形成该绝缘层240的材料为如聚对二唑苯(PBO)、聚酰亚胺(PI)、预浸材(PP)等的介电材。
再者，该导电柱23电性连接该线路结构20的线路层201与该布线结构24的布线层241，故可将该线路结构20的部分线路层201作为第一接地层，且将该布线结构24的部分布线层241作为第二接地层，以令该第一接地层与该第二接地层电性连接该导电柱23。
另外，可于该线路结构20的第二侧20b进行植球制程以形成多个如焊球的导电元件29，供后续接置一电路板(图略)。进一步，亦可于该线路结构20的第二侧20b上配置一如被动元件的功能元件28。
如图2G所示，于该布线结构24上设置第二电子元件22，再沿如图2F所示的切割路径S进行切单制程，以获取所需的电子封装件2。
于本实施例中，该第二电子元件22为主动元件、被动元件或其二者组合，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容或电感。于本实施例中，该第二电子元件22为半导体芯片，其通过覆晶方式(透过如图所示的多个导电凸块221)电性连接该布线层241；或者，该第二电子元件22亦可通过多个焊线(图略)以打线方式电性连接该布线层241；亦或，该第二电子元件22可直接接触该布线层241以电性连接该布线层241。然而，有关该第二电子元件22电性连接布线层241的方式不限于上述。
因此，本发明的制法，主要通过先于该线路结构20上形成第一封装层25，再将该导电柱23的部分柱体形成于该第一封装层25中，使该导电柱23的剩余柱体凸出该第一封装层25，之后以该第二封装层26包覆该导电柱23的剩余柱体，使该导电柱23一体成型于该第一封装层25与第二封装层26中，故相比于现有技术，本发明的制法能使该导电柱23降低其受该第二封装层26的冲击，因而能避免该导电柱23倾斜或断裂等问题，以当该布线结构24形成于该第二封装层26上时，能有效对位该导电柱23，使该线路结构20与该布线结构24之间得以有效电性导通。
另一方面，通过该第一封装层25的硬度不同于该第二封装层26的硬度，以分散应力，故当该第二封装层26结合至该第一封装层25上后，能有效分散该布线结构24与该线路结构20的应力，以减少应力集中，因而能避免该线路层201与该布线层241因无法承受应力集中而断裂的问题。
本发明亦提供一种电子封装件2，包括：一线路结构20、至少一第一电子元件21、多个导电柱23、一第一封装层25、一第二封装层26以及一布线结构24。
所述的第一电子元件21设于该线路结构20上并电性连接该线路结构20。
所述的第一封装层25设于该线路结构20上，且包覆该第一电子元件21。
所述的导电柱23插入该第一封装层25中，以设于该线路结构20上并电性连接该线路结构20，且令该导电柱23的部分凸出该第一封装层25。
所述的第二封装层26设于该第一封装层25上，并包覆该导电柱23凸出该第一封装层25的部分，且令该导电柱23的端面23a外露于该第二封装层26。
所述的布线结构24结合于该第二封装层26上且电性连接该导电柱23。
于一实施例中，该线路结构20的第一侧20a配置该第一电子元件21与该第一封装层25，而第二侧20b配置至少一功能元件28。
于一实施例中，该线路结构20具有可供作为第一接地层的线路层201，且该布线结构24具有可供作为第二接地层的布线层241，以令该第一接地层与该第二接地层电性连接该导电柱23。
于一实施例中，该第一封装层25与第二封装层26的材料相同。
于一实施例中，该第一封装层25与第二封装层26的材料相异。
于一实施例中，该第一封装层25的硬度不同于该第二封装层26的硬度。
于一实施例中，所述的电子封装件2还包括至少一设于该布线结构24上并电性连接该布线结构24的第二电子元件22。
综上所述，本发明的电子封装件及其制法，通过该导电柱一体成型于该第一封装层与第二封装层中，使该导电柱能降低其受该第二封装层的冲击，因而能避免该导电柱倾斜或断裂等问题，故当该布线结构形成于该第二封装层上时，能有效对位该导电柱，使该线路结构与该布线结构的间得以有效电性导通，因而能提高该电子封装件的可靠度。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (15)

1.一种电子封装件，包括：
线路结构；
第一电子元件，其设于该线路结构上并电性连接该线路结构；
第一封装层，其设于该线路结构上并包覆该第一电子元件；
导电柱，其插入该第一封装层中以设于该线路结构上，并电性连接该线路结构，且令该导电柱的部分凸出该第一封装层；
第二封装层，其设于该第一封装层上并包覆该导电柱凸出该第一封装层的部分，且令该导电柱的端面外露于该第二封装层；以及
布线结构，其结合于该第二封装层上且电性连接该导电柱。
2.如权利要求1所述的电子封装件，其中，该线路结构的其中一侧配置该第一电子元件与该第一封装层，而另一侧配置至少一功能元件。
3.如权利要求1所述的电子封装件，其中，该线路结构具有第一接地层，且该布线结构具有第二接地层，以令该第一接地层与该第二接地层电性连接该导电柱。
4.如权利要求1所述的电子封装件，其中，该第一封装层与第二封装层的材料相同。
5.如权利要求1所述的电子封装件，其中，该第一封装层与第二封装层的材料相异。
6.如权利要求1所述的电子封装件，其中，该第一封装层的硬度不同于该第二封装层的硬度。
7.如权利要求1所述的电子封装件，其中，该电子封装件还包括至少一设于该布线结构上并电性连接该布线结构的第二电子元件。
8.一种电子封装件的制法，包括：
于线路结构上设置至少一电性连接该线路结构的第一电子元件；
将第一封装层形成于该线路结构上，以令该第一封装层包覆该第一电子元件；
将导电柱形成于该第一封装层中，使该导电柱设于该线路结构上并电性连接该线路结构，且令该导电柱的部分凸出该第一封装层；
形成第二封装层于该第一封装层上，使该第二封装层包覆该导电柱凸出该第一封装层的部分，且令该导电柱的端面外露于该第二封装层；以及
形成布线结构于该第二封装层上，以令该布线结构电性连接该导电柱。
9.如权利要求8所述的电子封装件的制法，其中，该导电柱的制程包含：
形成一阻层于该第一封装层上；
形成连通该阻层与该第一封装层的穿孔，使该线路结构外露于该穿孔；
形成该导电柱于该穿孔中，使该导电柱电性连接该线路结构；以及
移除该阻层，使该导电柱的部分凸出该第一封装层。
10.如权利要求8所述的电子封装件的制法，其中，该线路结构的其中一侧配置该第一电子元件与该第一封装层，而另一侧配置至少一功能元件。
11.如权利要求8所述的电子封装件的制法，其中，该线路结构具有第一接地层，且该布线结构具有第二接地层，以令该第一接地层与该第二接地层电性连接该导电柱。
12.如权利要求8所述的电子封装件的制法，其中，该第一封装层与第二封装层的材料相同。
13.如权利要求8所述的电子封装件的制法，其中，该第一封装层与第二封装层的材料相异。
14.如权利要求8所述的电子封装件的制法，其中，该第一封装层的硬度不同于该第二封装层的硬度。
15.如权利要求8所述的电子封装件的制法，其中，该制法还包括于该布线结构上设置至少一电性连接该布线结构的第二电子元件。
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