TW202339016A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TW202339016A
TW202339016A TW111111933A TW111111933A TW202339016A TW 202339016 A TW202339016 A TW 202339016A TW 111111933 A TW111111933 A TW 111111933A TW 111111933 A TW111111933 A TW 111111933A TW 202339016 A TW202339016 A TW 202339016A
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Taiwan
Prior art keywords
layer
encapsulation layer
conductive pillar
circuit structure
electrically connected
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TW111111933A
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English (en)
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TWI809787B (zh
Inventor
柯仲禹
陳亮斌
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矽品精密工業股份有限公司
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Priority to TW111111933A priority Critical patent/TWI809787B/zh
Priority to CN202210368964.6A priority patent/CN116936487A/zh
Priority to US17/750,711 priority patent/US20230317565A1/en
Application granted granted Critical
Publication of TWI809787B publication Critical patent/TWI809787B/zh
Publication of TW202339016A publication Critical patent/TW202339016A/zh

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Abstract

一種電子封裝件，係於線路結構上形成第一封裝層，再將導電柱之部分柱體插入該第一封裝層中，使該導電柱之剩餘柱體凸出該第一封裝層，之後以第二封裝層包覆該導電柱之剩餘柱體，使該導電柱一體成型於該第一封裝層與第二封裝層中，故該導電柱可降低其受該第二封裝層之衝擊，避免該導電柱傾斜之問題。

Description

電子封裝件及其製法
本發明係有關一種半導體裝置，尤指一種可提高可靠度之電子封裝件及其製法。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，遂開發出不同的立體封裝技術，以將不同功能之積體電路整合於單一封裝結構，例如將不同功用之電子元件(如記憶體、中央處理器、繪圖處理器、影像應用處理器等)，藉由堆疊設計達到系統的整合，以應用於輕薄型電子產品。
圖1係為習知半導體封裝件1之剖面示意圖。如圖1所示，該半導體封裝件1之製法係於該線路結構10上配置第一半導體晶片11與導電柱13，再以封裝膠體15包覆該第一半導體晶片11與該導電柱13，之後，於該封裝膠體15上形成一佈線結構14，以於該佈線結構14上配置第二半導體晶片12。該導電柱13係電性連接該線路結構10與佈線結構14，且該線路結構10係電性連接該第一半導體晶片11，而該佈線結構14 係電性連接該第二半導體晶片12，並於該線路結構10下側形成複數銲球19，以供接合一電路板(圖略)。
然而，習知半導體封裝件1之製法中，係先於該線路結構10上電鍍形成該導電柱13，再以該封裝膠體15包覆該導電柱13，故該導電柱13易受該封裝膠體15衝擊而傾斜，甚至斷裂，導致該佈線結構14形成於該封裝膠體15上時，無法有效對位該導電柱13，造成該線路結構10與該佈線結構14之間無法有效電性導通。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：線路結構；第一電子元件，係設於該線路結構上並電性連接該線路結構；第一封裝層，係設於該線路結構上以包覆該第一電子元件；導電柱，係插入該第一封裝層中以設於該線路結構上並電性連接該線路結構，且令該導電柱之部分凸出該第一封裝層；第二封裝層，係設於該第一封裝層上且包覆該導電柱凸出該第一封裝層之部分，且令該導電柱之端面外露於該第二封裝層；以及佈線結構，係結合於該第二封裝層上且電性連接該導電柱。
本發明亦提供一種電子封裝件之製法，係包括：於線路結構上設置至少一電性連接該線路結構之第一電子元件；將第一封裝層形成於該線路結構上，以令該第一封裝層包覆該第一電子元件；將導電柱形成於該第一封裝層中，使該導電柱設於該線路結構上並電性連接該線路結構， 且令該導電柱之部分凸出該第一封裝層；形成第二封裝層於該第一封裝層上，使該第二封裝層包覆該導電柱凸出該第一封裝層之部分，且令該導電柱之端面外露於該第二封裝層；以及形成佈線結構於該第二封裝層上，以令該佈線結構電性連接該導電柱。
前述之製法中，該導電柱之製程係包含：形成一阻層於該第一封裝層上；形成連通該阻層與該第一封裝層之穿孔，使該線路結構外露於該穿孔；形成該導電柱於該穿孔中，使該導電柱電性連接該線路結構；以及移除該阻層，使該導電柱之部分凸出該第一封裝層。
前述之電子封裝件及其製法中，該線路結構之其中一側配置該第一電子元件與該第一封裝層，而另一側配置至少一功能元件。
前述之電子封裝件及其製法中，該線路結構係具有第一接地層，且該佈線結構係具有第二接地層，以令該第一接地層與該第二接地層電性連接該導電柱。
前述之電子封裝件及其製法中，該第一封裝層與第二封裝層之材質相同。
前述之電子封裝件及其製法中，該第一封裝層與第二封裝層之材質相異。
前述之電子封裝件及其製法中，該第一封裝層之硬度不同於該第二封裝層之硬度。
前述之電子封裝件及其製法中，復包括於該佈線結構上設置至少一電性連接該佈線結構之第二電子元件。
由上可知，本發明之電子封裝件及其製法中，主要藉由先於該線路結構上形成第一封裝層，再將該導電柱之部分柱體形成於該第一封裝層中，使該導電柱之剩餘柱體凸出該第一封裝層，之後以該第二封裝層 包覆該導電柱之剩餘柱體，使該導電柱一體成型於該第一封裝層與第二封裝層中，故相較於習知技術，本發明可使該導電柱降低其受該第二封裝層之衝擊，因而可避免該導電柱傾斜或斷裂等問題，以當該佈線結構形成於該第二封裝層上時，可有效對位該導電柱，使該線路結構與該佈線結構之間得以有效電性導通。
1:半導體封裝件
10,20:線路結構
11:第一半導體晶片
12:第二半導體晶片
13,23:導電柱
14,24:佈線結構
15:封裝膠體
19:銲球
2:電子封裝件
20a:第一側
20b:第二側
200:介電層
201:線路層
21:第一電子元件
21a:作用面
21b:非作用面
210:電極墊
211,221:導電凸塊
212:底膠
22:第二電子元件
23a:端面
240:絕緣層
241:佈線層
25:第一封裝層
250:穿孔
26:第二封裝層
26a:表面
28:功能元件
29:導電元件
8:阻層
9:承載件
90:離型層
S:切割路徑
圖1係為習知半導體封裝件之剖視示意圖。
圖2A至圖2G係為本發明之電子封裝件之製法之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2G係為本發明之電子封裝件2之製法的剖面示意圖。
如圖2A所示，於一承載件9上形成一線路結構20，該線路結構20係具有相對之第一側20a與第二側20b，以令該線路結構20之第一側20a上設置至少一第一電子元件21，且以一第一封裝層25包覆該第一電子元件21，並使該線路結構20以其第二側20b結合該承載件9。
於本實施例中，該線路結構20係如具有核心層與線路層之封裝基板(substrate)或無核心層(coreless)之基板結構，其包含至少一介電層200及結合該介電層200之線路層201。例如，以線路重佈層(redistribution layer，簡稱RDL)之製作方式形成無核心層基板結構，其中，形成該線路層201之材質係為銅，且形成該介電層200之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。應可理解地，該線路結構20亦可為其它可供承載如晶片等電子元件之載板，如矽中介板(interposer)，並不限於上述。
再者，該承載件9例如為半導體材質(如矽或玻璃)之板體，其上形成有一離型層90，使該線路結構20結合於該離型層90上。
又，該第一電子元件21係為主動元件、被動元件或其二者組合，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容或電感。於本實施例中，該第一電子元件21係為半導體晶片，其具有相對之作用面21a與非作用面21b，且該作用面21a具有複數電極墊210，使該電子元件21以其電極墊210藉由覆晶方式(透過如圖所示之複數導電凸塊211)電性連接該線路層201，再以底膠212包覆該些導電凸塊211；或者，該第一電子元件21亦可藉由複數銲線(圖略)以打線方式電性連接 該線路層201；亦或，該第一電子元件21可直接接觸該線路層201以電性連接該線路層201。然而，有關該第一電子元件21電性連接線路層201之方式不限於上述。
另外，該第一封裝層25係為絕緣材，如聚醯亞胺(PI)、乾膜(dry film)、環氧樹脂(epoxy)環氧樹脂之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該線路結構20之第一側20a上。例如，該第一封裝層25覆蓋該第一電子元件21之非作用面21b；或者，可藉由整平製程，如蝕刻或研磨方式，移除該第一封裝層25之部分材質，以令該第一封裝層25之上側之表面齊平該第一電子元件21之非作用面21b。
如圖2B所示，形成一阻層8於該第一封裝層25上，再形成至少一穿孔250連通該阻層8與該第一封裝層25，使該線路層201外露於該穿孔250。
如圖2C所示，形成導電柱23於該穿孔250中，使該導電柱23電性連接該線路結構20之第一側20a之線路層201。
於本實施例中，該導電柱23係為如銅柱之金屬柱或其它材質之柱體。
如圖2D所示，移除該阻層8，使該導電柱23凸出該第一封裝層25。
如圖2E所示，形成第二封裝層26於該第一封裝層25上，以令該第二封裝層26包覆該導電柱23。
於本實施例中，該第二封裝層26係為絕緣材，如聚醯亞胺、乾膜、如環氧樹脂之封裝膠體或封裝材，其可用壓合或模壓之方式形成於該佈線結構24上。應可理解地，形成該第二封裝層26之材質可相同或相 異於該第一封裝層25之材質，例如，該第一封裝層25之硬度不同於(或大於)該第二封裝層26之硬度。
再者，可藉由整平製程，如蝕刻或研磨方式，移除該第二封裝層26之部分材質，甚至該導電柱23之部分材質，使該第二封裝層26之上側之表面26a齊平該導電柱23之端面23a，以令該導電柱23之端面23a外露於該第二封裝層26。或者，可於該第二封裝層26之上側之表面上形成開孔，以令該導電柱23之端面23a外露於該第二封裝層26之開孔。
如圖2F所示，形成一佈線結構24於該第二封裝層26上，使該佈線結構24電性連接該導電柱23。之後，移除該承載件9與離型層90，以外露出該線路結構20之第二側20b。
於本實施例中，該佈線結構24係如具有核心層與線路層之封裝基板或無核心層之基板結構，其包含至少一絕緣層240及結合該絕緣層240且電性連接該導電柱23之佈線層241。例如，以線路重佈層(RDL)之製作方式形成無核心層基板結構，其中，形成該佈線層241之材質係為銅，且形成該絕緣層240之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)等之介電材。
再者，該導電柱23係電性連接該線路結構20之線路層201與該佈線結構24之佈線層241，故可將該線路結構20之部分線路層201作為第一接地層，且將該佈線結構24之部分佈線層241作為第二接地層，以令該第一接地層與該第二接地層電性連接該導電柱23。
另外，可於該線路結構20之第二側20b進行植球製程以形成複數如銲球之導電元件29，供後續接置一電路板(圖略)。進一步，亦可於該線路結構20之第二側20b上配置一如被動元件之功能元件28。
如圖2G所示，於該佈線結構24上設置第二電子元件22，再沿如圖2F所示之切割路徑S進行切單製程，以獲取所需之電子封裝件2。
於本實施例中，該第二電子元件22係為主動元件、被動元件或其二者組合，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容或電感。於本實施例中，該第二電子元件22係為半導體晶片，其藉由覆晶方式(透過如圖所示之複數導電凸塊221)電性連接該佈線層241；或者，該第二電子元件22亦可藉由複數銲線(圖略)以打線方式電性連接該佈線層241；亦或，該第二電子元件22可直接接觸該佈線層241以電性連接該佈線層241。然而，有關該第二電子元件22電性連接佈線層241之方式不限於上述。
因此，本發明之製法，主要藉由先於該線路結構20上形成第一封裝層25，再將該導電柱23之部分柱體形成於該第一封裝層25中，使該導電柱23之剩餘柱體凸出該第一封裝層25，之後以該第二封裝層26包覆該導電柱23之剩餘柱體，使該導電柱23一體成型於該第一封裝層25與第二封裝層26中，故相較於習知技術，本發明之製法能使該導電柱23降低其受該第二封裝層26之衝擊，因而能避免該導電柱23傾斜或斷裂等問題，以當該佈線結構24形成於該第二封裝層26上時，能有效對位該導電柱23，使該線路結構20與該佈線結構24之間得以有效電性導通。
另一方面，藉由該第一封裝層25之硬度不同於該第二封裝層26之硬度，以分散應力，故當該第二封裝層26結合至該第一封裝層25上後，能有效分散該佈線結構24與該線路結構20之應力，以減少應力集中，因而能避免該線路層201與該佈線層241因無法承受應力集中而斷裂之問題。
本發明亦提供一種電子封裝件2，係包括：一線路結構20、至少一第一電子元件21、複數導電柱23、一第一封裝層25、一第二封裝層26以及一佈線結構24。
所述之第一電子元件21係設於該線路結構20上並電性連接該線路結構20。
所述之第一封裝層25係設於該線路結構20上，且包覆該第一電子元件21。
所述之導電柱23係插入該第一封裝層25中，以設於該線路結構20上並電性連接該線路結構20，且令該導電柱23之部分凸出該第一封裝層25。
所述之第二封裝層26係設於該第一封裝層25上，並包覆該導電柱23凸出該第一封裝層25之部分，且令該導電柱23之端面23a外露於該第二封裝層26。
所述之佈線結構24係結合於該第二封裝層26上且電性連接該導電柱23。
於一實施例中，該線路結構20之第一側20a配置該第一電子元件21與該第一封裝層25，而第二側20b配置至少一功能元件28。
於一實施例中，該線路結構20係具有可供作為第一接地層之線路層201，且該佈線結構24係具有可供作為第二接地層之佈線層241，以令該第一接地層與該第二接地層電性連接該導電柱23。
於一實施例中，該第一封裝層25與第二封裝層26之材質相同。
於一實施例中，該第一封裝層25與第二封裝層26之材質相異。
於一實施例中，該第一封裝層25之硬度不同於該第二封裝層26之硬度。
於一實施例中，所述之電子封裝件2復包括至少一設於該佈線結構24上並電性連接該佈線結構24之第二電子元件22。
綜上所述，本發明之電子封裝件及其製法，係藉由該導電柱一體成型於該第一封裝層與第二封裝層中，使該導電柱能降低其受該第二封裝層之衝擊，因而能避免該導電柱傾斜或斷裂等問題，故當該佈線結構形成於該第二封裝層上時，能有效對位該導電柱，使該線路結構與該佈線結構之間得以有效電性導通，因而能提高該電子封裝件之可靠度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
20:線路結構
20a:第一側
20b:第二側
21:第一電子元件
22:第二電子元件
221:導電凸塊
23:導電柱
24:佈線結構
241:佈線層
25:第一封裝層
26:第二封裝層
28:功能元件
29:導電元件

Claims (15)

  1. 一種電子封裝件，係包括：
    線路結構；
    第一電子元件，係設於該線路結構上並電性連接該線路結構；
    第一封裝層，係設於該線路結構上並包覆該第一電子元件；
    導電柱，係插入該第一封裝層中以設於該線路結構上，並電性連接該線路結構，且令該導電柱之部分凸出該第一封裝層；
    第二封裝層，係設於該第一封裝層上並包覆該導電柱凸出該第一封裝層之部分，且令該導電柱之端面外露於該第二封裝層；以及
    佈線結構，係結合於該第二封裝層上且電性連接該導電柱。
  2. 如請求項1所述之電子封裝件，其中，該線路結構之其中一側配置該第一電子元件與該第一封裝層，而另一側配置至少一功能元件。
  3. 如請求項1所述之電子封裝件，其中，該線路結構係具有第一接地層，且該佈線結構係具有第二接地層，以令該第一接地層與該第二接地層電性連接該導電柱。
  4. 如請求項1所述之電子封裝件，其中，該第一封裝層與第二封裝層之材質相同。
  5. 如請求項1所述之電子封裝件，其中，該第一封裝層與第二封裝層之材質相異。
  6. 如請求項1所述之電子封裝件，其中，該第一封裝層之硬度不同於該第二封裝層之硬度。
  7. 如請求項1所述之電子封裝件，復包括至少一設於該佈線結構上並電性連接該佈線結構之第二電子元件。
  8. 一種電子封裝件之製法，係包括：
    於線路結構上設置至少一電性連接該線路結構之第一電子元件；
    將第一封裝層形成於該線路結構上，以令該第一封裝層包覆該第一電子元件；
    將導電柱形成於該第一封裝層中，使該導電柱設於該線路結構上並電性連接該線路結構，且令該導電柱之部分係凸出該第一封裝層；
    形成第二封裝層於該第一封裝層上，使該第二封裝層包覆該導電柱凸出該第一封裝層之部分，且令該導電柱之端面外露於該第二封裝層；以及
    形成佈線結構於該第二封裝層上，以令該佈線結構電性連接該導電柱。
  9. 如請求項8所述之電子封裝件之製法，其中，該導電柱之製程係包含：
    形成一阻層於該第一封裝層上；
    形成連通該阻層與該第一封裝層之穿孔，使該線路結構外露於該穿孔；
    形成該導電柱於該穿孔中，使該導電柱電性連接該線路結構；以及
    移除該阻層，使該導電柱之部分凸出該第一封裝層。
  10. 如請求項8所述之電子封裝件之製法，其中，該線路結構之其中一側配置該第一電子元件與該第一封裝層，而另一側配置至少一功能元件。
  11. 如請求項8所述之電子封裝件之製法，其中，該線路結構係具有第一接地層，且該佈線結構係具有第二接地層，以令該第一接地層與該第二接地層電性連接該導電柱。
  12. 如請求項8所述之電子封裝件之製法，其中，該第一封裝層與第二封裝層之材質相同。
  13. 如請求項8所述之電子封裝件之製法，其中，該第一封裝層與第二封裝層之材質相異。
  14. 如請求項8所述之電子封裝件之製法，其中，該第一封裝層之硬度不同於該第二封裝層之硬度。
  15. 如請求項8所述之電子封裝件之製法，復包括於該佈線結構上設置至少一電性連接該佈線結構之第二電子元件。
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