TWI776747B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TWI776747B
TWI776747B TW110145273A TW110145273A TWI776747B TW I776747 B TWI776747 B TW I776747B TW 110145273 A TW110145273 A TW 110145273A TW 110145273 A TW110145273 A TW 110145273A TW I776747 B TWI776747 B TW I776747B
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Taiwan
Prior art keywords
heat dissipation
wiring structure
electronic
electronic package
opening
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TW110145273A
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English (en)
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TW202324629A (zh
Inventor
林欣柔
王隆源
高灃
陳秋鈴
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矽品精密工業股份有限公司
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Priority to TW110145273A priority Critical patent/TWI776747B/zh
Priority to CN202111549978.XA priority patent/CN116230656A/zh
Application granted granted Critical
Publication of TWI776747B publication Critical patent/TWI776747B/zh
Priority to US17/944,464 priority patent/US20230178451A1/en
Publication of TW202324629A publication Critical patent/TW202324629A/zh

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Abstract

一種電子封裝件之製法，係將一包含有佈線結構之封裝模組藉由複數導電元件疊設於一承載結構上，且將一散熱件遮蓋該佈線結構之其中一部分表面，而將一電子模組接置於該佈線結構之另一部分表面上，以令該佈線結構形成有至少一結合該散熱件之散熱墊，使該電子模組與該封裝模組可經由該散熱墊及該散熱件進行散熱。

Description

電子封裝件及其製法
本發明係有關一種半導體裝置，尤指一種電子封裝件及其製法。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，遂開發出不同的立體封裝技術，以將不同功能之積體電路整合於單一封裝結構，例如將不同功用之電子元件(如：記憶體、中央處理器、繪圖處理器、影像應用處理器等)，藉由堆疊設計達到系統的整合，以應用於輕薄型電子產品。
圖1係為習知半導體封裝件1之剖面示意圖。該半導體封裝件1係包括：一第一封裝膠體15、一嵌埋於該第一封裝膠體15中之第一半導體晶片11、一設於該第一封裝膠體15相對兩側之線路結構10與佈線結構14、複數嵌埋於該第一封裝膠體15中以電性連接該線路結構10與佈線結構14之導電柱13、複數設於該線路結構10上之第二半導體晶片12以及一包覆該第二半導體晶片12之第二封裝膠體18，且該佈線結構14係電性連接該第一半導體晶片11，而該線路結構10係電性連接該第二半導體晶片12，並於該佈線結構14下側形成複數銲球19，以供接合一電路板(圖略)。
惟，習知半導體封裝件1，因該第一與第二半導體晶片11,12運轉時所產生的熱，需先透過第一與第二封裝膠體15,18，才能將熱傳導至電路板上或傳導至外部，因而散熱效果不佳。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：承載結構；封裝模組，係藉由複數導電元件疊設於該承載結構上且包含一包覆層、埋設於該包覆層中之至少一電子元件與複數導電柱、及形成於該包覆層上之佈線結構，以令該複數導電元件與該佈線結構分別設於該包覆層之相對兩側，且該至少一電子元件與該複數導電柱係藉由該複數導電元件電性連接該承載結構，並使該佈線結構電性連接該複數導電柱，其中，該佈線結構係具有至少一散熱墊；散熱件，係設於該至少一散熱墊上且結合該承載結構，以令該散熱件遮蓋該佈線結構之一部分表面；以及至少一電子模組，係接置於該佈線結構之另一部分表面上且電性連接該佈線結構。
本發明亦提供一種電子封裝件之製法，係包括：提供一封裝模組，其包含一包覆層、埋設於該包覆層中之至少一電子元件與複數導電柱、及形成於該包覆層上之佈線結構，且該佈線結構係電性連接該複數導電柱，其中，該佈線結構係具有至少一散熱墊；將該封裝模組藉由複數導電元件疊設於一承載結構上，以令該複數導電元件與該佈線結構分別設於該包覆層之相對兩側，且該至少一電子元件與該複數導電柱係藉由該複數導電元件電性連接該承載結構；將散熱件設於該至少一散熱墊上且結合該承載結構，以令該散熱件遮蓋該佈線結構 之一部分表面；以及將至少一電子模組接置於該佈線結構之另一部分表面上，以令該至少一電子模組電性連接該佈線結構。
前述之電子封裝件及其製法中，該至少一散熱墊係為無電性功能之虛設墊。
前述之電子封裝件及其製法中，該佈線結構係具有接地線路，以令該至少一散熱墊作為連接該接地線路之接地墊。
前述之電子封裝件及其製法中，該佈線結構係具有複數散熱墊，其排設方式係呈環狀，且該散熱件係具有一結合該複數散熱墊之環體，其具有一開口，以令該佈線結構之另一部分表面外露於該開口，使該至少一電子模組設於該開口中之佈線結構上以電性連接該佈線結構。例如，該環體與該複數散熱墊之間係配置有散熱材。進一步，該複數散熱墊係環繞於該開口周圍，以作為擋牆，供防止該散熱材溢流至該開口區域，且該複數散熱墊係排設呈多環狀，並依距離該開口的遠近關係定義出內環與外環，該多環中最靠近該開口之一者係作為該內環，而最遠離該開口之一者係作為該外環，供限制該散熱材之佈設範圍於該內環與該外環之間。
前述之電子封裝件及其製法中，該至少一電子元件與該佈線結構之間係配置有金屬層。例如，該金屬層係接觸該佈線結構。或者，該佈線結構係具有接地線路，以連接該金屬層。
前述之電子封裝件及其製法中，復包括配置於該至少一電子模組上之散熱結構。
由上可知，本發明之電子封裝件及其製法中，主要藉由該佈線結構具有散熱墊之設計，使該電子模組與該封裝模組之間可經由該散熱墊沿該散熱件進行散熱，以利於該電子模組與該封裝模組散熱，故相較於習知技術， 該電子模組與該封裝模組的熱能可輕易逸散至外部環境，不僅散熱路徑快速，且透過該散熱墊與該散熱件更能提升散熱效果。
1:半導體封裝件
10,20:線路結構
11,31:第一半導體晶片
12,32:第二半導體晶片
13,23,33a:導電柱
14,24:佈線結構
15:第一封裝膠體
18:第二封裝膠體
19:銲球
2,3,4,5:電子封裝件
2a:封裝模組
200,91:絕緣層
201,301:線路重佈層
202:電性接觸墊
21:電子元件
21a:作用面
21b:非作用面
210:電極墊
211:保護膜
212:導電體
212a,23a,23b:端面
22,52:結合層
240:介電層
241:佈線層
242:功能墊
243,244,343:散熱墊
243a:內環
243b:外環
243c:中環
25:包覆層
25a:第一表面
25b:第二表面
26:承載結構
26a:線路層
260:底膠
27,29,37:導電元件
28:散熱件
28a:環體
28b:支撐腳
280:開口
281:散熱材
282:黏著層
3a:電子模組
30:第一線路部
33:導電結構
34:第二線路部
341,441:接地線路
35:第一封裝層
36:結合材
38:第二封裝層
39:散熱結構
42:金屬層
50:散熱塊
8:支撐板
80:黏膠層
9:承載板
9a:晶種層
90:離型層
A:空腔
S:切割路徑
圖1係為習知半導體封裝件之剖視示意圖。
圖2A至圖2H係為本發明之電子封裝件之製法之第一實施例之剖視示意圖。
圖2I係為圖2F之局部上視示意圖。
圖2J及圖2K係為圖2I之不同態樣之局部上視示意圖。
圖3A至圖3B係為本發明之電子封裝件之製法之第二實施例之剖視示意圖。
圖4A至圖4C係為本發明之電子封裝件之製法之第三實施例之剖視示意圖。
圖4D至圖4E係為對應圖4A至圖4C之另一實施態樣之剖視示意圖。
圖4F係為對應圖4D至圖4E之另一實施態樣之剖視示意圖。
圖5A至圖5C係為本發明之電子封裝件之製法之第四實施例之剖視示意圖。
圖5D係為對應圖5B至圖5C之另一實施態樣之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2G係為本發明之電子封裝件2之製法之第一實施例的剖面示意圖。
如圖2A所示，於一承載板9上形成複數導電柱23，且設置至少一電子元件21於該承載板9上(本圖示中顯示有二個電子元件)，其中，該電子元件21上係結合並電性連接有複數導電體212。
於本實施例中，該承載板9例如為半導體材質(如矽或玻璃)之板體，其上以例如塗佈方式依序形成有一離型層90、一如鈦/銅之晶種層9a與一如介電材或防銲材之絕緣層91，以供該導電柱23藉由該晶種層9a電鍍形成於該晶種層9a(絕緣層91)上。
再者，形成該導電柱23之材質係為如銅之金屬材或銲錫材，且該導電體212係為如導電線路、銲球之圓球狀、或如銅柱、銲錫凸塊等金屬材之柱狀、或銲線機製作之釘狀(stud)導電件，但不限於此。
又，該電子元件21係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於本實施例中，該電子元件21係為半導體晶片，其具有相對之作用面21a與非作用面21b，該電子元件21係以其非作用面21b藉由一如置晶膜(die attached film，簡稱DAF) 之結合層22黏固於該絕緣層91上，而該作用面21a具有複數電極墊210與一如鈍化材之保護膜211，且該導電體212設於該保護膜211中。
如圖2B所示，形成一包覆層25於該承載板9之絕緣層91上，以令該包覆層25包覆該些電子元件21、該些導電體212與該些導電柱23，其中，該包覆層25係具有相對之第一表面25a與第二表面25b，且令該保護膜211、該導電體212之端面212a與該導電柱23之端面23a外露於該包覆層25之第一表面25a，以及令該包覆層25以其第二表面25b結合至該承載板9之絕緣層91上。
於本實施例中，該包覆層25係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)。例如，該包覆層25之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成於該絕緣層91上。
再者，可藉由整平製程，使該包覆層25之第一表面25a齊平該保護膜211、該導電柱23之端面23a與該導電體212之端面212a，以令該導電柱23之端面23a與該導電體212之端面212a外露於該包覆層25之第一表面25a。例如，該整平製程係藉由研磨方式，移除該保護膜211之部分材質、該導電柱23之部分材質、該導電體212之部分材質與該包覆層25之部分材質。
如圖2C所示，形成一線路結構20於該包覆層25之第一表面25a上，且令該線路結構20電性連接該複數導電柱23與該複數導電體212。
於本實施例中，該線路結構20係包括複數絕緣層200及設於該絕緣層200上之複數線路重佈層(redistribution layer，簡稱RDL)201，其中，最外層之絕緣層200可作為防銲層，且令最外層之線路重佈層201外露於該防銲層，俾供作為電性接觸墊202，以形成複數如銲錫凸塊、銅凸塊或其它等之導電元件27 於該電性接觸墊202上，並使該些導電元件27電性連接該電性接觸墊202。或者，該線路結構20亦可僅包括單一絕緣層200及單一線路重佈層201。
再者，形成該線路重佈層201之材質係為銅，且形成該絕緣層200之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(PI)、預浸材(Prepreg，簡稱PP)等之介電材、或如綠漆、油墨等之防銲材。
又，可形成一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)(圖略)於該電性接觸墊202上，以利於結合該導電元件27。
如圖2D所示，將該些導電元件27接置於一支撐板8上，再移除該承載板9及其上之離型層90與該晶種層9a，以外露出該絕緣層91及導電柱23之另一端面23b。接著，於該絕緣層91上形成一電性連接該複數導電柱23之佈線結構24。
於本實施例中，該支撐板8上係具有一黏膠層80，以令該線路結構20貼合該黏膠層80，使該些導電元件27埋入該黏膠層80中，並於剝離該離型層90時，藉由該晶種層9a作為阻障之用，以避免破壞該絕緣層91，且待移除該承載板9及其上之離型層90後，再以蝕刻方式移除該晶種層9a，此時，該導電柱23之另一端面23b係齊平該絕緣層91以外露於該絕緣層91。
再者，該佈線結構24係包含該絕緣層91、至少一介電層240及結合該介電層240之佈線層241。例如，形成該介電層240之材質係如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材，且可採用線路重佈層(redistribution layer，簡稱RDL)製程形成該佈線層241與該介電層240。
又，於最外層之介電層240上係配置有複數電性連接該佈線層241之功能墊242及至少一無電性功能之散熱墊243。例如，該些散熱墊243係呈環狀排設，如圖2I所示，以環繞該些功能墊242
另外，該些散熱墊243係為浮接(floating)狀態之虛設墊(dummy pad)，其電性絕緣該佈線層241。
如圖2E所示，移除該支撐板8，再沿如圖2D所示之切割路徑S進行切單製程，以獲取複數封裝模組2a。之後，將該封裝模組2a藉由其導電元件27接置於一承載結構26上。
於本實施例中，該承載結構26係例如具有核心層之封裝基板(substrate)或無核心層(coreless)式封裝基板，其具有一絕緣基體與結合該絕緣基體之線路層26a，該線路層26a例如為扇出(fan out)型重佈線路層(RDL)。例如，形成該線路層26a之材質係例如為銅，而形成該絕緣基體之材質係例如為聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。應可理解地，該承載結構亦可為其它可供承載電子元件之承載單元，例如導線架(lead frame)或矽中介板(silicon interposer)，並不限於上述。
再者，該導電元件27係結合於該線路層26a上以電性連接該線路層26a。例如，可形成底膠260於該封裝模組2a與該承載結構26之間以包覆該些導電元件27。
如圖2F所示，將一散熱件28設於該封裝模組2a之散熱墊243上，且該散熱件28復結合該承載結構26。
於本實施例中，該散熱件28係具有一環體28a與複數自該環體28a邊緣向下延伸之支撐腳28b，且該環體28a係為散熱片狀型式，其下側以散熱材281結合該散熱墊243。例如，該散熱材281係為導熱介面材(Thermal Interface Material，簡稱TIM)、銲錫材、金屬材或其它導熱材料，且該環體28a具有一開口280，其對應該些功能墊242之位置，以令該些功能墊242外露於該開口280。應可理解地，可依需求將該散熱材281塗佈於該散熱件28及/或該散熱墊243上。
再者，該支撐腳28b係藉由黏著層282結合於該承載結構26上。例如，該支撐腳28b並未接觸該封裝模組2a，使該支撐腳28b與該封裝模組2a之間形成有一空腔A。
又，該些散熱墊243之形狀可為長條形(如圖2I或圖2J所示)、圓形(如圖2K所示之散熱墊244)、L形(如圖2K所示之散熱墊244)或其它幾何形狀，其可依散熱需求排設成單環狀(圖略)或多環狀(如圖2I所示之雙環型或如圖2J所示之三環型)。例如，該些散熱墊243藉由該多環狀之排設方式以依距離該開口280的遠近關係定義出內環243a與外環243b，如圖2I或圖2J所示，該多環中最靠近該開口280之一者係作為該內環243a，而最遠離該開口280之一者係作為該外環243b，供限制該散熱材281之佈設範圍於該內環243a與該外環243b之間，使如底膠或TIM之散熱材281不會溢流至其它區域。應可理解地，該散熱墊243於內環243a與外環243b之間的排設方式可依需求設計而不限定為環狀(如圖2J所示之中環243c)，例如可隨機排設(如圖2K所示之散熱墊244)或依熱能分布進行排設。因此，若無需限制該散熱材281之佈設範圍，該些散熱墊243,244的排設方式可依需求設計，並不限於環狀。
另外，該內環243a係環繞於該開口280周圍，因而可作為擋牆，以防止該散熱材281溢流至該開口280區域而影響散熱效果。
如圖2G所示，將至少一電子模組3a設於該開口280中之功能墊242上，以令該電子模組3a電性連接該功能墊242。接著，於該承載結構26下側之線路層26a上進行植球製程，以形成複數如銲球之導電元件29，供於後續製程中，該承載結構26以其下側之導電元件29設於一電路板(圖略)上，以製得本發明之電子封裝件2。
於本實施例中，該電子模組3a係藉由複數如銲錫凸塊、銅凸塊或其它等之導電元件37接合該功能墊242以電性連接該佈線結構24。例如，可藉由 如底膠或非導電膠(Non-Conductive Paste，簡稱NCP)之結合材36包覆該些導電元件37。因此，該些散熱墊243所組成之內環243a亦可防止底膠或非導電膠(NCP)之結合材36溢流至該散熱件28之下方，以避免影響散熱效果。
再者，若採用非導電膠(NCP)之結合材36，則先將NCP黏於該些導電元件37及其周圍上，再接合該些功能墊242。或者，若採用底膠之結合材36，則先將該些導電元件37接合該些功能墊242，再進行點膠作業以形成該結合材36。
又，該電子模組3a係包含一第一封裝層35、至少一嵌埋於該第一封裝層35中之第一半導體晶片31、複數嵌埋於該第一封裝層35中之導電結構33、一設於該第一封裝層35上側之第一線路部30、至少一設於該第一線路部30上之第二半導體晶片32、一包覆該第二半導體晶片32之第二封裝層38、以及一設於該第一封裝層35下側以結合該些導電元件37之第二線路部34。
另外，該第一半導體晶片31與第二半導體晶片32係電性連接該第一線路部30，且該些導電結構33係電性連接該第一與第二線路部30,34，而該第一封裝層35及第二封裝層38係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)。例如，形成該第一封裝層35之材質可相同或不相同該第二封裝層38之材質。
應可理解地，有關該電子模組3a之態樣繁多，可依該電子封裝件2之需求配置所需之電子模組，並不限於上述。
因此，本發明之製法主要藉由該電子模組3a與該封裝模組2a之間的佈線結構24配置有至少一用以對接該散熱件28之散熱墊243，以利於該電子模組3a與該封裝模組2a散熱，故該電子模組3a與該封裝模組2a集中於中央區域(即該開口280之處)的熱能皆可藉由該散熱件28接觸該散熱墊243而逸散至外部環境。
再者，該散熱件28係直接設於該導電柱23及該佈線結構24上方，不僅散熱路徑快速，且透過金屬材質的散熱墊243與該散熱件28更能提升散熱效果。
又，該電子模組3a上方(該第二封裝層38之頂面或該第二半導體晶片32頂面)還可接置一散熱結構39，如圖2H所示之鰭片型散熱片，以導接採用該電子封裝件2所製成之電子產品之系統端的散熱機制。
圖3A至圖3B係為本發明之電子封裝件3之製法之第二實施例的剖面示意圖。本實施例與第一實施例之差異在於散熱墊343之配置，故以下不再贅述相同處。
如圖3A所示，於圖2D所示之製程中，佈線結構24復包含結合介電層240之接地線路341，其可採用線路重佈層(RDL)製程與佈線層241一併製作，以令散熱墊343連接接地線路341。
於本實施例中，該散熱墊343係作為接地墊，且於複數導電柱23,33a中之至少一導電柱33a係連接該接地線路341，並導通至該線路結構20之部分線路重佈層301，以作為散熱途徑。
如圖3B所示，進行如圖2E至圖2G所示之製程，以獲取電子封裝件3。
因此，相較於第一實施例之散熱墊243係提供一經環體28a而向上之散熱途徑，本實施例主要藉由該散熱墊343(接地墊)連接該佈線結構24之接地用佈線層241(即該接地線路341)，以令該佈線結構24及該導電柱33a導熱至該承載結構26，使該散熱墊343(接地墊)提供另一向下散熱途徑。
圖4A至圖4C係為本發明之電子封裝件4之製法之第三實施例的剖面示意圖。本實施例與第一實施例之差異在於增設散熱機制，故以下不再贅述相同處。
如圖4A所示，於圖2A所示之製程中，電子元件21之非作用面21b藉由複合材料(如一結合層22及一金屬層42)結合於絕緣層91上。
於本實施例中，該金屬層42之材質可為散熱能力佳的金屬材質，如銅。例如，可先濺鍍一金屬層42於該電子元件21之非作用面21b上，再黏著一結合層22於該金屬層42上，使該電子元件21藉由該結合層22結合至該絕緣層91。
如圖4B所示，進行如圖2B至圖2D所示之製程，其中，於佈線結構24與電子元件21之間係配置有該結合層22與該金屬層42。
如圖4C所示，進行如圖2E至圖2G所示之製程，以獲取電子封裝件4，其中，該電子元件21所產生之熱可經由該金屬層42傳遞至該佈線結構24，再經由該佈線結構24上之散熱件28進行散熱。
於本實施例中，該複合材料亦可先濺鍍該金屬層42於該絕緣層91上，再將該結合層22形成於該電子元件21之非作用面21b上，以令該電子元件21藉由該結合層22結合於該金屬層42上，如圖4D所示。例如，於製作該導電柱時，可一併製作該金屬層42。因此，於後續製程中，該佈線結構24可接觸該金屬層42，如圖4E所示，使該電子元件21的散熱途徑可經由該非作用面21b、該結合層22、該金屬層42、該絕緣層91、該佈線結構24(介電層240或佈線層241)、該散熱墊243,343、該散熱件28(或導電柱33a)、該線路結構20及該承載結構26。
進一步，該佈線結構24亦可配置接地線路441，以直接連接該金屬層42，如圖4F所示。例如，該接地線路441可採用線路重佈層(RDL)製程與該佈線層241一併製作。因此，該電子元件21的散熱途徑可經由該非作用面21b、該結合層22、該金屬層42、該佈線結構24(接地線路441)、該散熱墊243,343、該散熱件28(或導電柱33a)、線路結構20及該承載結構26，以提升散熱效果。
因此，本實施例之製法係藉由增設該金屬層42於該電子元件21之非作用面21b上，以強化該電子元件21(晶背)的散熱效果，且可進一步將該金 屬層42與該佈線結構24之接地線路441相接，使熱經由該金屬層42散熱至該散熱墊243,343的途徑係採用高散熱的金屬途徑，因而效果更佳。
圖5A至圖5C係為本發明之電子封裝件5之製法之第四實施例的剖面示意圖。本實施例與第三實施例之差異在於複合材料之組成，故以下不再贅述相同處。
如圖5A至圖5B所示，於圖2A所示之製程中，電子元件21之非作用面21b藉由複合材料(如一結合層52、複數散熱塊50及一金屬層42)結合於絕緣層91上。
於本實施例中，該結合層52係為非導電膜(Non-Conductive Film，簡稱NCF)，且該結合層52中係埋設該些散熱塊50，以令該散熱塊50接觸該非作用面21b上之金屬層42。例如，先濺鍍一金屬層42於該電子元件21之非作用面21b上，再黏著一結合層52於該金屬層42上，且將複數散熱塊50形成於該絕緣層91上(如圖5A所示)，以令該電子元件21藉由該結合層52壓合於該些散熱塊50上，使該結合層52包覆該些散熱塊50(如圖5B所示)。
如圖5C所示，於後續製程中，該佈線結構24透過該絕緣層91(或如圖5D所示之接地線路441)接觸該散熱塊50，使該電子元件21的散熱途徑可經由該非作用面21b、該金屬層42、該散熱塊50、該絕緣層91(或接地線路441)、該散熱墊243,343、該散熱件28(或導電柱33a)、該線路結構20及該承載結構26。
因此，本實施例之製法係藉由增設該散熱塊50於該電子元件21之非作用面21b上，以強化該電子元件21(晶背)的散熱效果，且可進一步將該散熱塊50與該佈線結構24之接地線路441相接，使熱經由該金屬層42與散熱塊50散熱至該散熱墊243,343的途徑係採用高散熱的金屬途徑，因而效果更佳。
本發明亦提供一種電子封裝件2,3,4,5，係包括：一承載結構26、一封裝模組2a、一散熱件28、以及一電子模組3a。
所述之封裝模組2a係藉由複數導電元件27疊設於該承載結構26上且包含一包覆層25、埋設於該包覆層25中之至少一電子元件21與複數導電柱23,33a、及形成於該包覆層25上之佈線結構24，以令該複數導電元件27與該佈線結構24分別設於該包覆層25之相對兩側，且該電子元件21與該複數導電柱23,33a係藉由該複數導電元件27電性連接該承載結構26，並使該佈線結構24電性連接該複數導電柱23,33a，其中，該佈線結構24係具有至少一散熱墊243,343。
所述之散熱件28係設於該散熱墊243,343上且結合該承載結構26，以令該散熱件28遮蓋該佈線結構24之一部分表面。
所述之電子模組3a係接置於該佈線結構24之另一部分表面上且電性連接該佈線結構24。
於一實施例中，該散熱墊243係為無電性功能之虛設墊。
於一實施例中，該佈線結構24係具有接地線路341，以令該散熱墊343作為連接該接地線路341之接地墊。
於一實施例中，該佈線結構24係具有複數該散熱墊243,343，其排設方式係呈環狀，且該散熱件28係具有一結合複數該散熱墊243,343之環體28a，其具有一開口280，以令該佈線結構24之另一部分表面外露於該開口280，使該電子模組3a設於該開口280中之佈線結構24上以電性連接該佈線結構24。例如，該環體28a與該散熱墊243,343之間係配置有散熱材281。進一步，該佈線結構24之複數該散熱墊243,343係環繞於該開口280周圍，以作為擋牆，且該佈線結構24之複數該散熱墊243,343係排設呈多環狀以定義出內環243a與外環243b，供限制該散熱材281之佈設範圍。
於一實施例中，該電子元件21與該佈線結構24之間係配置有金屬層42。例如，該金屬層42係接觸該佈線結構24。或者，該佈線結構24係具有接地線路441，以連接該金屬層42。
於一實施例中，所述之電子封裝件2復包括至少一配置於該電子模組3a上之散熱結構39。
綜上所述，本發明之電子封裝件及其製法，係藉由該電子模組與該封裝模組之間的佈線結構配置有至少一用以對接該散熱件之散熱墊，以利於該電子模組與該封裝模組散熱，故該電子模組與該封裝模組的熱能皆可藉由該散熱件接觸該散熱墊而逸散至外部環境。
再者，該散熱件直接設於該導電柱及該佈線結構上方，不僅散熱路徑快速，且透過金屬材質的散熱墊與該散熱件更能提升散熱效果。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2a:封裝模組
26:承載結構
28:散熱件
29:導電元件
3a:電子模組
39:散熱結構

Claims (22)

  1. 一種電子封裝件，係包括：承載結構；封裝模組，係藉由複數導電元件疊設於該承載結構上且包含一包覆層、埋設於該包覆層中之至少一電子元件與複數導電柱、及形成於該包覆層上之佈線結構，以令該複數導電元件與該佈線結構分別設於該包覆層之相對兩側，且該至少一電子元件與該複數導電柱係藉由該複數導電元件電性連接該承載結構，並使該佈線結構電性連接該複數導電柱，其中，該佈線結構係具有至少一散熱墊；散熱件，係設於該至少一散熱墊上且結合該承載結構，以令該散熱件遮蓋該佈線結構之一部分表面；以及至少一電子模組，係接置於該佈線結構之另一部分表面上且電性連接該佈線結構。
  2. 如請求項1所述之電子封裝件，其中，該至少一散熱墊係為無電性功能之虛設墊。
  3. 如請求項1所述之電子封裝件，其中，該佈線結構係具有接地線路，以令該至少一散熱墊作為連接該接地線路之接地墊。
  4. 如請求項1所述之電子封裝件，其中，該至少一散熱墊係為複數散熱墊，其排設方式係呈環狀，且該散熱件係具有一結合該複數散熱墊之環體，該環體具有一開口，以令該佈線結構之另一部分表面外露於該開口，使該至少一電子模組設於該開口中之佈線結構上以電性連接該佈線結構。
  5. 如請求項4所述之電子封裝件，其中，該環體與該複數散熱墊之間係配置有散熱材。
  6. 如請求項5所述之電子封裝件，其中，該複數散熱墊係環繞於該開口周圍，以作為擋牆，供防止該散熱材溢流至該開口區域。
  7. 如請求項6所述之電子封裝件，其中，該複數散熱墊係排設呈多環狀，並依距離該開口的遠近關係定義出內環與外環，該多環中最靠近該開口之一者係作為該內環，而最遠離該開口之一者係作為該外環，供限制該散熱材之佈設範圍於該內環與該外環之間。
  8. 如請求項1所述之電子封裝件，其中，該至少一電子元件與該佈線結構之間係配置有金屬層。
  9. 如請求項8所述之電子封裝件，其中，該金屬層係接觸該佈線結構。
  10. 如請求項8所述之電子封裝件，其中，該佈線結構係具有接地線路，以連接該金屬層。
  11. 如請求項1所述之電子封裝件，復包括配置於該至少一電子模組上之散熱結構。
  12. 一種電子封裝件之製法，係包括：提供一封裝模組，其包含一包覆層、埋設於該包覆層中之至少一電子元件與複數導電柱、及形成於該包覆層上之佈線結構，且該佈線結構係電性連接該複數導電柱，其中，該佈線結構係具有至少一散熱墊；將該封裝模組藉由複數導電元件疊設於一承載結構上，以令該複數導電元件與該佈線結構分別位於該包覆層之相對兩側，而使該至少一電子元件與該複數導電柱藉由該複數導電元件電性連接該承載結構； 將散熱件設於該至少一散熱墊上且結合該承載結構，以令該散熱件遮蓋該佈線結構之一部分表面；以及將至少一電子模組接置於該佈線結構之另一部分表面上，以令該至少一電子模組電性連接該佈線結構。
  13. 如請求項12所述之電子封裝件之製法，其中，該至少一散熱墊係為無電性功能之虛設墊。
  14. 如請求項12所述之電子封裝件之製法，其中，該佈線結構係具有接地線路，以令該至少一散熱墊作為連接該接地線路之接地墊。
  15. 如請求項12所述之電子封裝件之製法，其中，該至少一散熱墊係為複數散熱墊，其排設方式係呈環狀，且該散熱件係具有一結合該複數散熱墊之環體，該環體具有一開口，以令該佈線結構之另一部分表面外露於該開口，使該至少一電子模組設於該開口中之佈線結構上以電性連接該佈線結構。
  16. 如請求項15所述之電子封裝件之製法，其中，該環體與該複數散熱墊之間係配置有散熱材。
  17. 如請求項16所述之電子封裝件之製法，其中，該複數散熱墊係環繞於該開口周圍，以作為擋牆，供防止該散熱材溢流至該開口區域。
  18. 如請求項17所述之電子封裝件之製法，其中，該複數散熱墊係排設呈多環狀，並依距離該開口的遠近關係定義出內環與外環，該多環中最靠近該開口之一者係作為該內環，而最遠離該開口之一者係作為該外環，供限制該散熱材之佈設範圍於該內環與該外環之間。
  19. 如請求項12所述之電子封裝件之製法，其中，該至少一電子元件與該佈線結構之間係配置有金屬層。
  20. 如請求項19所述之電子封裝件之製法，其中，該金屬層係接觸該佈線結構。
  21. 如請求項19所述之電子封裝件之製法，其中，該佈線結構係具有接地線路，以連接該金屬層。
  22. 如請求項12所述之電子封裝件之製法，復包括於該至少一電子模組上配置一散熱結構。
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TW202133356A (zh) * 2020-02-18 2021-09-01 南韓商三星電子股份有限公司 半導體封裝以及具有其的層疊封裝
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TW202139395A (zh) * 2018-08-30 2021-10-16 恆勁科技股份有限公司 覆晶封裝基板之核心結構及其製法

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TW202139395A (zh) * 2018-08-30 2021-10-16 恆勁科技股份有限公司 覆晶封裝基板之核心結構及其製法
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