CN116978884A - 电子封装件 - Google Patents

电子封装件 Download PDF

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Publication number
CN116978884A
CN116978884A CN202210480179.XA CN202210480179A CN116978884A CN 116978884 A CN116978884 A CN 116978884A CN 202210480179 A CN202210480179 A CN 202210480179A CN 116978884 A CN116978884 A CN 116978884A
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China
Prior art keywords
layer
electronic
electronic package
circuit
package
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CN202210480179.XA
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English (en)
Inventor
钟松桦
陈亮斌
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN116978884A publication Critical patent/CN116978884A/zh
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Abstract

一种电子封装件，包括于封装层中嵌埋电子结构，且于该封装层上结合保护层，并将绝缘层结合于该保护层上，并形成有至少一贯穿该绝缘层与该保护层的盲孔，使该电子结构外露于该盲孔，供后续形成于该绝缘层上的线路层延伸至该盲孔中以电性连接该电子结构，故通过该绝缘层与保护层的双层设计，使制程所产生的气泡无法转移至该绝缘层，避免该气泡残存于该线路层中。

Description

电子封装件
技术领域
本发明有关一种半导体装置，尤指一种可提升可靠度的电子封装件。
背景技术
为了确保电子产品和通信设备的持续小型化和多功能性，半导体封装需朝尺寸微小化发展，以利于多引脚的连接，并具备高功能性。
图1为现有半导体封装件1的剖面示意图。首先，提供一具有相对的转接侧10a与置晶侧10b的硅中介板(Through Silicon interposer，简称TSI)10，且该硅中介板10具有多个连通该置晶侧10b与转接侧10a的导电硅穿孔(Through-silicon via，简称TSV)100，并于该置晶侧10b上形成一如RDL(redistribution layer)型的线路结构11以供接置一具有较小焊锡凸块150间距的半导体芯片15，再将该硅中介板10以其转接侧10a通过多个导电元件18设于一具有较大线距的封装基板13上，并使该封装基板13电性连接该些导电硅穿孔100。接着，形成封装胶体16于该封装基板13上，以令该封装胶体16包覆该半导体芯片15与该硅中介板10。最后，形成多个焊球12于该封装基板13的下侧植球垫130，以供接置于一电路板1a上。
现有半导体封装件1中，该半导体芯片15与该封装基板13之间通过该线路结构11进行电源/信号的传输。
然而，若需增加该半导体封装件1的功能，需于单一硅中介板10上配置多个半导体芯片15，因而需增加该线路结构11的布线的层数(如由图1所示的一层介电层110增加为多层介电层)，导致因布线的层数越多而制程良率越低的缘故，致使该半导体芯片15无法有效电性连接该线路结构11，造成该半导体封装件1的良率与可靠度不佳等问题。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷，本发明提供一种电子封装件，包括：封装层，其具有相对的第一表面与第二表面；电子结构，其嵌埋于该封装层中；保护层，其结合于该封装层的第一表面上；绝缘层，其结合于该保护层上，并形成有至少一贯穿该绝缘层与该保护层的盲孔，使该电子结构外露于该盲孔；以及线路层，其形成于该绝缘层上并延伸至该盲孔中以电性连接该电子结构。
前述的电子封装件中，该电子结构具有多个导电体及包覆该多个导电体的包覆层。
前述的电子封装件中，形成该保护层的材料为绝缘材。
前述的电子封装件中，该保护层的密度至少为3(g/cc)以上。
前述的电子封装件中，该保护层与该绝缘层的弹性模数不同。
前述的电子封装件中，该绝缘层的弹性模数小于该保护层的弹性模数。
前述的电子封装件中，该保护层的弹性模数至少为200Gpa以上。
前述的电子封装件中，该绝缘层的厚度与该保护层的厚度的总和等于该盲孔的深度。
前述的电子封装件中，该保护层的厚度至少为0.6微米。
前述的电子封装件中，该绝缘层的厚度与该保护层的厚度的总和至少为5微米以上。
前述的电子封装件中，还包括嵌埋于该封装层中且电性连接该线路层的多个导电柱。
前述的电子封装件中，还包括形成于该封装层的第二表面上且电性连接该多个导电体的线路结构。进一步，还包括至少一配置于该线路结构上且电性连接该线路结构的电子元件。例如，该线路结构上配置多个该电子元件，使该电子结构作为桥接元件，以电性桥接至少二该电子元件。
前述的电子封装件中，还包括形成于该线路层上且电性连接该线路层的多个导电元件。
前述的电子封装件中，该电子结构为半导体芯片，其具有多个电性连接该线路层的电极垫。
由上可知，本发明的电子封装件中，主要通过该绝缘层与保护层的设计，使该包覆层或封装层所产生的气泡无法转移至该绝缘层，因而能避免该气泡残存于该线路层中，故本发明的电子封装件能大幅提高该线路层的制程良率，使该线路层有效电性连接该电子结构与该导电元件，因而有利于提升该电子封装件的良率与可靠度。
再者，当需增加该电子封装件的功能时，只需于单一线路结构上配置一个电子结构，而无需增加该线路结构的布线的层数，故相比于现有技术，本发明可依需求控管该线路结构的布线的层数而可提高制程良率，使该电子元件可有效电性连接该线路结构，以提升该电子封装件的良率与可靠度。
附图说明
图1为现有半导体封装件的剖视示意图。
图2A为本发明的电子封装件的第一实施例的剖视示意图。
图2B为图2A的局部放大剖视示意图。
图3为图2A的应用的剖视示意图。
图4为本发明的电子封装件的第二实施例的剖视示意图。
图5为图4的另一实施例的剖视示意图。
主要组件符号说明
1 半导体封装件
1a 电路板
2、4 电子封装件
2a、40 电子结构
2b 布线结构
10 硅中介板
10a 转接侧
10b 置晶侧
11、20 线路结构
12、300 焊球
13、30 封装基板
15 半导体芯片
16 封装胶体
18、27 导电元件
21 电子主体
21a 第一导电体
21b 第一包覆层
22 线路部
22a 第二导电体
22b 第二包覆层
23 导电柱
24 绝缘层
25 第一封装层
25a、45a 第一表面
25b、45b 第二表面
26 电子元件
26a 导电凸块
28 第二封装层
29 保护层
31 强固件
40a 作用面
40b 非作用面
45 封装层
48 绝缘保护层
51 包覆层
52 导电体
100 导电硅穿孔
110 介电层
130 植球垫
150 焊锡凸块
200 介电层
201 线路重布层
202 电性接触垫
210 导电穿孔
220 钝化层
221 导电迹线
240 盲孔
241 线路层
260 焊锡材料
262 底胶
270 金属凸块
271 焊锡材料
400 电极垫
H 深度
t1、t2 厚度。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A为本发明的电子封装件2的第一实施例的剖面示意图。如图2A所示，所述的电子封装件2包括：一第一封装层25、一嵌埋于该第一封装层25中的电子结构2a、多个嵌埋于该第一封装层25中的导电柱23、以及一形成于该第一封装层25上的布线结构2b。
所述的第一封装层25具有相对的第一表面25a与第二表面25b。
于本实施例中，该第一封装层25为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dry film)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)。例如，该第一封装层25的制程可选择液态封胶(liquid compound)、喷涂(injection)、压合(lamination)或模压(compression molding)等方式形成。
所述的电子结构2a包含一电子主体21、一形成于该电子主体21上的线路部22、多个形成于该电子主体21上的第一导电体21a、及多个形成于该线路部22上且电性连接该线路部22的第二导电体22a，且通过第一包覆层21b与第二包覆层22b包覆该多个第一导电体21a与该多个第二导电体22a。
于本实施例中，该电子主体21为硅基材，如半导体芯片，其具有多个贯穿该电子主体21的导电穿孔210，如导电硅穿孔(Through-silicon via，简称TSV)，以电性连接位于该电子主体21不同侧的该线路部22与该多个第一导电体21a。例如，该线路部22包含至少一钝化层220及结合该钝化层220的导电迹线221，以令该导电迹线221电性连接该导电穿孔210与该多个第二导电体22a。应可理解地，有关具有该导电穿孔210的元件结构的实施例繁多，并无特别限制。
再者，该第一导电体21a与第二导电体22a为如铜柱的金属柱，且该第一包覆层21b与第二包覆层22b为非导电膜(Non-Conductive Film，简称NCF)、底胶或其它绝缘材料。
所述的导电柱23为如铜柱的金属柱或焊锡球体，其电性连接该布线结构2b。
于本实施例中，该第一封装层25的第一表面25a齐平该导电柱23的端面与该第二导电体22a的端面，且该第一封装层25的第二表面25b齐平该导电柱23的端面与该第一导电体21a的端面。
所述的布线结构2b包含一结合该第一封装层25的保护层29、至少一结合该保护层29的绝缘层24、及结合该绝缘层24与该保护层29的线路层241，以令该线路层241电性连接该多个第二导电体22a与该多个导电柱23。
于本实施例中，该保护层29为绝缘薄膜，如氮化硅(SiN)的氮化物或其它有机介电材，其密度至少为3(g/cc)以上，且形成该绝缘层24的材料如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等的介电材，并可采用线路重布层(redistribution layer，简称RDL)制程形成该线路层241。
再者，该线路层241贯穿该绝缘层24与保护层29以接触该第二导电体22a。例如，先形成一贯穿该绝缘层24与保护层29的盲孔240，如图2B所示，使该第二导电体22a外露于该盲孔240，再通过电镀或其它方式形成铜材于该盲孔240中，使该线路层241延伸至该盲孔240中以电性连接该第二导电体22a，其中，该绝缘层24的厚度t1与该保护层29的厚度t2的总和等于该盲孔240的深度h。进一步，该保护层29的厚度t2至少为0.6微米(um)。较佳者，该绝缘层24的厚度t1与该保护层29的厚度t2的总和至少为5微米以上，以避免应力集中所产生的翘曲或其它问题。
另外，该保护层29与该绝缘层24的弹性模数不同。例如，该绝缘层24的弹性模数(约5.2Gpa)小于该保护层29的弹性模数(至少200Gpa以上)。
另外，可形成多个导电元件27于该布线结构2b上，使该些导电元件27电性连接该线路层241。
于本实施例中，该导电元件27包含一如铜材的金属凸块270及形成于该金属凸块270上的焊锡材料271。例如，该线路层241上可形成凸块底下金属层(Under BumpMetallization，简称UBM)(图略)，以利于结合该金属凸块270。
因此，本发明的电子封装件2主要通过当制作单一线路层241时，于该第一封装层25的第一表面25a上形成该绝缘层24与保护层29等多层结构，以增厚绝缘材，使该第二包覆层22b(NCF)于后续热制程中所产生的气泡(void)无法转移至该绝缘层24，以避免该气泡散逸至该盲孔240中而导致该线路层241的结构强度不足(即包含气泡而非全部实心结构)的问题，故本发明的线路层241的制程良率能大幅提高，以有效电性连接该电子结构2a与该导电元件27，因而有利于提升该电子封装件2的良率与可靠度。
于其它实施例中，该电子封装件2还可包括：一设于该第一封装层25上的线路结构20、设于该线路结构20上的至少一(或多个)电子元件26、以及一包覆该电子元件26的第二封装层28。
所述的线路结构20形成于该第一封装层25的第二表面25b上，以令该线路结构20电性连接该导电柱23与该多个第一导电体21a。
于本实施例中，该线路结构20包括至少一介电层200及设于该介电层200上的线路重布层(redistribution layer，简称RDL)201，使该线路重布层201电性连接该多个导电柱23与该多个第一导电体21a，其中，最外层的介电层200可作为防焊层，且令最外层的线路重布层201外露出该防焊层，从而供作为电性接触垫202，如微垫(micro pad，俗称μ-pad)。
再者，形成该线路重布层201的材料为铜，且形成该介电层200的材料为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)等的介电材、或如绿漆、油墨等的防焊材。
所述的电子元件26为主动元件、被动元件或其二者组合，且该主动元件为例如半导体芯片，而该被动元件为例如电阻、电容及电感。
于本实施例中，该电子元件26例如为图形处理器(graphics processing unit，简称GPU)、高频宽存储器(High Bandwidth Memory，简称HBM)等半导体芯片。例如，该电子元件26可通过覆晶方式、打线方式、直接接触该线路结构20或其它适当方式电性连接该线路重布层201，并无特别限制。
再者，若该电子元件26采用覆晶方式，其可通过多个如铜柱的导电凸块26a配合焊锡材料260电性连接该电性接触垫202。较佳者，可形成一凸块底下金属层(Under BumpMetallurgy，简称UBM)(图略)于该电性接触垫202或该电子元件26上，以利于结合该焊锡材料260或该导电凸块26a。
另外，若该线路结构20上配置多个电子元件26，则可令该电子结构2a作为桥接元件(Bridge die)，使该电子结构2a通过该些第一导电体21a电性连接该线路重布层201，进而电性桥接至少二电子元件26。
所述的第二封装层28为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dryfilm)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该线路结构20上。应可理解地，该第二封装层28与该第一封装层25的材料可相同或相异。
于本实施例中，可先形成底胶262于该电子元件26与该线路结构20之间以包覆该些导电凸块26a与焊锡材料260，再形成该第二封装层28以包覆该底胶262与该电子元件26。或者，直接以该第二封装层28同时包覆该电子元件26与该些导电凸块26a及焊锡材料260。
再者，可通过整平制程，如研磨方式，移除该第二封装层28的部分材料，使该第二封装层28的上表面齐平该电子元件26的上表面，如图3所示，以令该电子元件26外露出该第二封装层28。
因此，本发明通过将该电子结构2a作为桥接元件，以电性桥接至少两个电子元件26，因而当需增加该电子封装件2的功能时，只需于单一线路结构20上配置一个电子结构2a，而无需增加该线路重布层201的层数，故相比于现有技术，本发明的线路结构20因该线路重布层201可依需求控管层数而能提高制程良率，使该电子元件26能有效电性连接该线路重布层201，以提升该电子封装件2的良率与可靠度。
另外，如图3所示，该电子封装件2可通过该些导电元件27设置于一封装基板30上。进一步，该封装基板30下侧进行植球制程以形成多个焊球300，供该封装基板30以其下侧的焊球300设于一电路板(图略)上。
另外，该封装基板30上可依需求设置一强固件31，如图3所示的金属框，以消除应力集中的问题而避免电子封装件2发生翘曲的情况。
图4为本发明的电子封装件4的第二实施例的剖面示意图。如图4所示，所述的电子封装件4采用扇出(fan out)式晶圆级芯片规格进行封装，其包括：一封装层45、一嵌埋于该封装层45中的电子结构40、一结合于该封装层上的保护层29、一结合于该保护层29上的绝缘层24以及一形成于该绝缘层24上的线路层241。
所述的封装层45具有相对的第一表面45a与第二表面45b，以令该保护层29结合于该封装层45的第一表面45a上。
所述的电子结构40为主动元件、被动元件或其组合者，其中，该主动元件为例如半导体芯片，而该被动元件为例如电阻、电容及电感。于本实施例中，该电子结构40为半导体芯片，其具有相对的作用面40a与非作用面40b，该作用面40a具有多个电极垫400，且可依需求外露该非作用面40b(如图5所示的该非作用面40b与该封装层45的第二表面45b共平面)。
所述的绝缘层24形成有至少一贯穿该绝缘层24与该保护层29的盲孔240，使该电子结构40的电极垫400外露于该盲孔240。
所述的线路层241延伸至该盲孔240中以电性连接该电子结构40的电极垫400。于本实施例中，该线路层241上可形成多个导电元件27，以令该电子封装件4通过该多个导电元件27接置于一如图3所示的封装基板30上或电路板(图略)上。进一步，可于该绝缘层24上形成一如防焊层的绝缘保护层48，其外露该线路层241的部分表面，以结合该导电元件27。
因此，本发明的电子封装件4主要通过当制作单一线路层241时，于该封装层45的第一表面45a上形成该绝缘层24与保护层29等多层结构，以增厚绝缘材，使该封装层45于后续热制程中所产生的气泡(void)无法转移至该绝缘层24，以避免该气泡散逸至该盲孔240中而导致该线路层241的结构强度不足(即包含气泡而非全部实心结构)的问题，故本发明的线路层241的制程良率能大幅提高，以有效电性连接该电子结构40与该导电元件27，因而有利于提升该电子封装件4的良率与可靠度。
应可理解地，有关扇出式晶圆级芯片规格的形式繁多，如图5所示，其电子结构40的作用面40a的电极垫400上可配置如金属柱的导电体52，并通过一如胶膜的包覆层51包覆该些导电体52，故无特别限制该扇出式晶圆级芯片规格的形式。
综上所述，本发明的电子封装件，通过该绝缘层与保护层的设计，使该包覆层或第二包覆层(或第一封装层、封装层)所产生的气泡无法转移至该绝缘层，因而能避免该气泡残存于该线路层中，故本发明能大幅提高该线路层的制程良率，以有效电性连接该电子结构与该导电元件，因而有利于提升该电子封装件的良率与可靠度。
再者，通过该电子结构作为桥接元件，以电性桥接至少两个电子元件，因而当需增加该电子封装件的功能时，只需于单一线路结构上配置一个电子结构，而无需增加该线路重布层的层数，故本发明可依需求控管该线路重布层的层数而能提高制程良率，使该电子元件能有效电性连接该线路重布层，以提升该电子封装件的良率与可靠度。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (16)

1.一种电子封装件，包括：
封装层，其具有相对的第一表面与第二表面；
电子结构，其嵌埋于该封装层中；
保护层，其结合于该封装层的第一表面上；
绝缘层，其结合于该保护层上，并形成有至少一贯穿该绝缘层与该保护层的盲孔，使该电子结构外露于该盲孔；以及
线路层，其形成于该绝缘层上并延伸至该盲孔中以电性连接该电子结构。
2.如权利要求1所述的电子封装件，其中，该电子结构具有多个导电体及包覆该多个导电体的包覆层。
3.如权利要求1所述的电子封装件，其中，形成该保护层的材料为绝缘材。
4.如权利要求1所述的电子封装件，其中，该保护层的密度至少为3(g/cc)以上。
5.如权利要求1所述的电子封装件，其中，该保护层与该绝缘层的弹性模数不同。
6.如权利要求1所述的电子封装件，其中，该绝缘层的弹性模数小于该保护层的弹性模数。
7.如权利要求1所述的电子封装件，其中，该保护层的弹性模数至少为200Gpa以上。
8.如权利要求1所述的电子封装件，其中，该绝缘层的厚度与该保护层的厚度的总和等于该盲孔的深度。
9.如权利要求1所述的电子封装件，其中，该保护层的厚度至少为0.6微米。
10.如权利要求1所述的电子封装件，其中，该绝缘层的厚度与该保护层的厚度的总和至少为5微米以上。
11.如权利要求1所述的电子封装件，其中，该电子封装件还包括嵌埋于该封装层中且电性连接该线路层的多个导电柱。
12.如权利要求1所述的电子封装件，其中，该电子封装件还包括形成于该封装层的第二表面上且电性连接该电子结构的线路结构。
13.如权利要求12所述的电子封装件，其中，该电子封装件还包括至少一配置于该线路结构上且电性连接该线路结构的电子元件。
14.如权利要求13所述的电子封装件，其中，该线路结构上配置多个该电子元件，使该电子结构作为桥接元件，以电性桥接至少二该电子元件。
15.如权利要求1所述的电子封装件，其中，该电子封装件还包括形成于该线路层上且电性连接该线路层的多个导电元件。
16.如权利要求1所述的电子封装件，其中，该电子结构为半导体芯片，其具有多个电性连接该线路层的电极垫。
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